src/llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/phi-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
# RUN: | FileCheck -check-prefix=RV32I %s

---
name:            phi_i32
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  ; RV32I-LABEL: name: phi_i32
  ; RV32I: bb.0:
  ; RV32I-NEXT:   liveins: $x10, $x11, $x12
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x10
  ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
  ; RV32I-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x12
  ; RV32I-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1
  ; RV32I-NEXT:   BNE [[ANDI]], $x0, %bb.2
  ; RV32I-NEXT:   PseudoBR %bb.1
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.1:
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.2:
  ; RV32I-NEXT:   [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.1, [[COPY1]], %bb.0
  ; RV32I-NEXT:   $x10 = COPY [[PHI]]
  ; RV32I-NEXT:   PseudoRET implicit $x10
  bb.0:
    liveins: $x10, $x11, $x12

    %0:gprb(s32) = COPY $x10
    %1:gprb(s32) = COPY $x11
    %2:gprb(s32) = COPY $x12
    %3:gprb(s32) = G_CONSTANT i32 1
    %4:gprb(s32) = G_AND %0, %3
    G_BRCOND %4(s32), %bb.2
    G_BR %bb.1

  bb.1:

  bb.2:
    %5:gprb(s32) = G_PHI %2(s32), %bb.1, %1(s32), %bb.0
    $x10 = COPY %5(s32)
    PseudoRET implicit $x10

...
---
name:            phi_ptr
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  ; RV32I-LABEL: name: phi_ptr
  ; RV32I: bb.0.entry:
  ; RV32I-NEXT:   liveins: $x10, $x11, $x12
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x10
  ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
  ; RV32I-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x12
  ; RV32I-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1
  ; RV32I-NEXT:   BNE [[ANDI]], $x0, %bb.2
  ; RV32I-NEXT:   PseudoBR %bb.1
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.1:
  ; RV32I-NEXT: {{  $}}
  ; RV32I-NEXT: bb.2:
  ; RV32I-NEXT:   [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.1, [[COPY1]], %bb.0
  ; RV32I-NEXT:   $x10 = COPY [[PHI]]
  ; RV32I-NEXT:   PseudoRET implicit $x10
  bb.0.entry:
    liveins: $x10, $x11, $x12

    %0:gprb(s32) = COPY $x10
    %1:gprb(p0) = COPY $x11
    %2:gprb(p0) = COPY $x12
    %3:gprb(s32) = G_CONSTANT i32 1
    %4:gprb(s32) = G_AND %0, %3
    G_BRCOND %4(s32), %bb.2
    G_BR %bb.1

  bb.1:

  bb.2:
    %5:gprb(p0) = G_PHI %2(p0), %bb.1, %1(p0), %bb.0
    $x10 = COPY %5(p0)
    PseudoRET implicit $x10

...