src/llvm-project/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir

# RUN: not llc -mtriple=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
---
name: noreg_rsrc_reg
machineFunctionInfo:
  scratchRSrcReg:  '$noreg'
# CHECK: :[[@LINE-1]]:{{[0-9]+}}: incorrect register class for field
body:             |
  bb.0:

    S_ENDPGM
...