| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 |
| # RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass si-wqm -o - %s | FileCheck %s |
| |
| --- | |
| define amdgpu_ps void @exit_to_exact() { |
| ret void |
| } |
| ... |
| --- |
| |
| --- |
| name: exit_to_exact |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: sgpr_32, preferred-register: '' } |
| - { id: 1, class: vreg_64, preferred-register: '' } |
| - { id: 2, class: sgpr_256, preferred-register: '' } |
| - { id: 3, class: sgpr_128, preferred-register: '' } |
| - { id: 4, class: vreg_96, preferred-register: '' } |
| - { id: 5, class: vreg_64, preferred-register: '' } |
| - { id: 6, class: vgpr_32, preferred-register: '' } |
| liveins: |
| - { reg: '$sgpr0', virtual-reg: '%0' } |
| body: | |
| ; CHECK-LABEL: name: exit_to_exact |
| ; CHECK: bb.0: |
| ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) |
| ; CHECK-NEXT: liveins: $sgpr0, $vgpr0_vgpr1 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $exec_lo |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0 |
| ; CHECK-NEXT: $exec_lo = S_WQM_B32 $exec_lo, implicit-def $scc |
| ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 |
| ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF |
| ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF |
| ; CHECK-NEXT: S_CMP_EQ_U32 [[COPY1]], 0, implicit-def $scc |
| ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MUL_F32_e64 0, [[COPY2]].sub0, 0, [[COPY2]].sub1, 0, 0, implicit $mode, implicit $exec |
| ; CHECK-NEXT: %5.sub1:vreg_64 = V_MUL_F32_e64 0, [[COPY2]].sub0, 0, [[COPY2]].sub1, 0, 0, implicit $mode, implicit $exec |
| ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc |
| ; CHECK-NEXT: $exec_lo = S_AND_B32 $exec_lo, [[COPY]], implicit-def $scc |
| ; CHECK-NEXT: $scc = COPY [[COPY3]] |
| ; CHECK-NEXT: [[IMAGE_SAMPLE_V3_V2_gfx10_:%[0-9]+]]:vreg_96 = IMAGE_SAMPLE_V3_V2_gfx10 %5, [[DEF]], [[DEF1]], 7, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s96), align 16, addrspace 8) |
| ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc |
| ; CHECK-NEXT: S_BRANCH %bb.1 |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.1: |
| ; CHECK-NEXT: successors: %bb.2(0x80000000) |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: {{ $}} |
| ; CHECK-NEXT: bb.2: |
| ; CHECK-NEXT: [[V_SUB_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_SUB_F32_e64 0, [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub0, 0, [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub1, 0, 0, implicit $mode, implicit $exec |
| ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET_exact [[V_SUB_F32_e64_]], [[DEF1]], [[COPY1]], 4, 0, 0, implicit $exec |
| ; CHECK-NEXT: EXP 0, [[V_SUB_F32_e64_]], [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub0, [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub1, [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub2, 0, 0, 0, implicit $exec |
| ; CHECK-NEXT: S_ENDPGM 0 |
| bb.0: |
| liveins: $sgpr0, $vgpr0_vgpr1 |
| |
| %0 = COPY $sgpr0 |
| %1 = COPY $vgpr0_vgpr1 |
| %2 = IMPLICIT_DEF |
| %3 = IMPLICIT_DEF |
| |
| S_CMP_EQ_U32 %0, 0, implicit-def $scc |
| undef %5.sub0 = V_MUL_F32_e64 0, %1.sub0, 0, %1.sub1, 0, 0, implicit $mode, implicit $exec |
| %5.sub1 = V_MUL_F32_e64 0, %1.sub0, 0, %1.sub1, 0, 0, implicit $mode, implicit $exec |
| %4 = IMAGE_SAMPLE_V3_V2_gfx10 %5, %2, %3, 7, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s96), align 16, addrspace 8) |
| S_CBRANCH_SCC1 %bb.2, implicit killed $scc |
| S_BRANCH %bb.1 |
| |
| bb.1: |
| |
| bb.2: |
| %6 = nofpexcept V_SUB_F32_e64 0, %4.sub0, 0, %4.sub1, 0, 0, implicit $mode, implicit $exec |
| BUFFER_STORE_DWORD_OFFSET_exact %6, %3, %0, 4, 0, 0, implicit $exec |
| EXP 0, %6, %4.sub0, %4.sub1, %4.sub2, 0, 0, 0, implicit $exec |
| S_ENDPGM 0 |
| |
| ... |