src/llvm-project/llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-dbg.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs -stop-after=rewrite-partial-reg-uses %s -o - | FileCheck -check-prefix=CHECK %s
--- |
  define void @test_vreg_96_w64() !dbg !5 {
  entry:
    call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
    unreachable, !dbg !11
  }

  ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
  declare void @llvm.dbg.value(metadata, metadata, metadata) #0

  attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

  !llvm.dbg.cu = !{!0}
  !llvm.mir.debugify = !{!2, !3}
  !llvm.debugify = !{!3, !3}
  !llvm.module.flags = !{!4}

  !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
  !1 = !DIFile(filename: "t.mir", directory: "/")
  !2 = !{i32 6}
  !3 = !{i32 1}
  !4 = !{i32 2, !"Debug Info Version", i32 3}
  !5 = distinct !DISubprogram(name: "test_vreg_96_w64", linkageName: "test_vreg_96_w64", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8)
  !6 = !DISubroutineType(types: !7)
  !7 = !{}
  !8 = !{!9}
  !9 = !DILocalVariable(name: "1", scope: !5, file: !1, line: 1, type: !10)
  !10 = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_unsigned)
  !11 = !DILocation(line: 1, column: 1, scope: !5)

...
---
name:            test_vreg_96_w64
body:             |
  bb.0:
    ; CHECK-LABEL: name: test_vreg_96_w64
    ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec, debug-location !11
    ; CHECK-NEXT: DBG_VALUE %3.sub0, $noreg, !9, !DIExpression(), debug-location !11
    ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec, debug-location !DILocation(line: 2, column: 1, scope: !5)
    ; CHECK-NEXT: DBG_VALUE %3.sub1, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 2, column: 1, scope: !5)
    ; CHECK-NEXT: S_NOP 0, implicit %3, debug-location !DILocation(line: 3, column: 1, scope: !5)
    ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec, debug-location !DILocation(line: 4, column: 1, scope: !5)
    ; CHECK-NEXT: DBG_VALUE %4.sub0, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5)
    ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec, debug-location !DILocation(line: 5, column: 1, scope: !5)
    ; CHECK-NEXT: DBG_VALUE %4.sub1, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5)
    ; CHECK-NEXT: S_NOP 0, implicit %4, debug-location !DILocation(line: 6, column: 1, scope: !5)
    ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec, debug-location !DILocation(line: 4, column: 1, scope: !5)
    ; CHECK-NEXT: DBG_VALUE %5, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5)
    ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec, debug-location !DILocation(line: 5, column: 1, scope: !5)
    ; CHECK-NEXT: DBG_VALUE %5, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5)
    ; CHECK-NEXT: S_NOP 0, implicit %5, debug-location !DILocation(line: 6, column: 1, scope: !5)
    undef %0.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec, debug-location !11
    DBG_VALUE %0.sub0, $noreg, !9, !DIExpression(), debug-location !11
    %0.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec, debug-location !DILocation(line: 2, column: 1, scope: !5)
    DBG_VALUE %0.sub1, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 2, column: 1, scope: !5)
    S_NOP 0, implicit %0.sub0_sub1, debug-location !DILocation(line: 3, column: 1, scope: !5)

    undef %1.sub1:vreg_96 = V_MOV_B32_e32 11, implicit $exec, debug-location !DILocation(line: 4, column: 1, scope: !5)
    DBG_VALUE %1.sub1, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5)
    %1.sub2:vreg_96 = V_MOV_B32_e32 12, implicit $exec, debug-location !DILocation(line: 5, column: 1, scope: !5)
    DBG_VALUE %1.sub2, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5)
    S_NOP 0, implicit %1.sub1_sub2, debug-location !DILocation(line: 6, column: 1, scope: !5)

    undef %2.sub1:vreg_96 = V_MOV_B32_e32 11, implicit $exec, debug-location !DILocation(line: 4, column: 1, scope: !5)
    DBG_VALUE %2, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5)
    %2.sub2:vreg_96 = V_MOV_B32_e32 12, implicit $exec, debug-location !DILocation(line: 5, column: 1, scope: !5)
    DBG_VALUE %2, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5)
    S_NOP 0, implicit %2.sub1_sub2, debug-location !DILocation(line: 6, column: 1, scope: !5)
...