src/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s

---
name:            rcp_sqrt_test
body:             |
  bb.0:
    liveins: $sgpr0

    ; GCN-LABEL: name: rcp_sqrt_test
    ; GCN: liveins: $sgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; GCN-NEXT: [[INT:%[0-9]+]]:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[COPY]](s32)
    ; GCN-NEXT: $vgpr0 = COPY [[INT]](s32)
    ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = G_FSQRT %0:_
    %3:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %2:_(s32)
    $vgpr0 = COPY %3:_(s32)
    SI_RETURN_TO_EPILOG implicit $vgpr0

...

---
name:            sqrt_rcp_test
body:             |
  bb.0:
    liveins: $sgpr0

    ; GCN-LABEL: name: sqrt_rcp_test
    ; GCN: liveins: $sgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; GCN-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[COPY]](s32)
    ; GCN-NEXT: $vgpr0 = COPY [[INT]](s32)
    ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0:_(s32)
    %3:_(s32) = G_FSQRT %2:_
    $vgpr0 = COPY %3:_(s32)
    SI_RETURN_TO_EPILOG implicit $vgpr0

...