src/llvm-project/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-mi-peephole-opt -mtriple=aarch64-unknown-linux -verify-machineinstrs -o - %s | FileCheck %s
--- |
  define void @insert_vec_v6i64_uaddlv_from_v4i32(ptr %0) {
  entry:
    ret void
  }

  define void @insert_vec_v2i32_uaddlv_from_v8i16(ptr %0) {
  entry:
    ret void
  }

  define void @insert_vec_v8i16_uaddlv_from_v8i16(ptr %0) {
  entry:
    ret void
  }

  define void @insert_vec_v16i8_uaddlv_from_v4i32(ptr %0) {
  entry:
    ret void
  }

  define void @insert_vec_v2i32_uaddlv_from_v8i16_nz_index(ptr %0) {
  entry:
    ret void
  }

  ; The optimization is not applicable when the source is not a virtual register
  define void @insert_vec_from_gpr(i32 %v, ptr %p) {
  entry:
    ret void
  }

  define void @fadd(double %v, double %p) {
  entry:
    ret void
  }

  define void @asm(ptr %hist) {
  entry:
    ret void
  }

  attributes #0 = { nocallback nofree nosync nounwind willreturn memory(none) }

...
---
name:            insert_vec_v6i64_uaddlv_from_v4i32
registers:
  - { id: 0, class: gpr64common, preferred-register: '' }
  - { id: 1, class: fpr128, preferred-register: '' }
  - { id: 2, class: fpr64, preferred-register: '' }
  - { id: 3, class: fpr128, preferred-register: '' }
  - { id: 4, class: fpr128, preferred-register: '' }
  - { id: 5, class: gpr64, preferred-register: '' }
  - { id: 6, class: fpr128, preferred-register: '' }
  - { id: 7, class: fpr128, preferred-register: '' }
  - { id: 8, class: fpr64, preferred-register: '' }
  - { id: 9, class: fpr128, preferred-register: '' }
  - { id: 10, class: fpr128, preferred-register: '' }
  - { id: 11, class: fpr128, preferred-register: '' }
  - { id: 12, class: fpr64, preferred-register: '' }
  - { id: 13, class: fpr128, preferred-register: '' }
  - { id: 14, class: fpr128, preferred-register: '' }
  - { id: 15, class: fpr128, preferred-register: '' }
  - { id: 16, class: gpr64all, preferred-register: '' }
  - { id: 17, class: fpr64, preferred-register: '' }
liveins:
  - { reg: '$x0', virtual-reg: '%0' }
body:             |
  bb.0.entry:
    liveins: $x0

    ; CHECK-LABEL: name: insert_vec_v6i64_uaddlv_from_v4i32
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
    ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
    ; CHECK-NEXT: [[UADDLVv4i32v:%[0-9]+]]:fpr64 = UADDLVv4i32v [[MOVIv2d_ns]]
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], killed [[UADDLVv4i32v]], %subreg.dsub
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY [[INSERT_SUBREG]].dsub
    ; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[MOVIv2d_ns]], 0, [[INSERT_SUBREG]], 0
    ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 0
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], killed [[MOVID]], %subreg.dsub
    ; CHECK-NEXT: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv2f64 killed [[INSvi64lane]], implicit $fpcr
    ; CHECK-NEXT: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv2i32 killed [[UCVTFv2f64_]], implicit $fpcr
    ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], killed [[FCVTNv2i32_]], %subreg.dsub
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub
    ; CHECK-NEXT: STRDui killed [[COPY2]], [[COPY]], 2 :: (store (s64) into %ir.0 + 16)
    ; CHECK-NEXT: STRQui killed [[INSERT_SUBREG2]], [[COPY]], 0 :: (store (s128) into %ir.0, align 8)
    ; CHECK-NEXT: RET_ReallyLR
    %0:gpr64common = COPY $x0
    %1:fpr128 = MOVIv2d_ns 0
    %2:fpr64 = UADDLVv4i32v %1
    %4:fpr128 = IMPLICIT_DEF
    %3:fpr128 = INSERT_SUBREG %4, killed %2, %subreg.dsub
    %5:gpr64 = COPY %3.dsub
    %7:fpr128 = INSvi64gpr %1, 0, killed %5
    %8:fpr64 = MOVID 0
    %10:fpr128 = IMPLICIT_DEF
    %9:fpr128 = INSERT_SUBREG %10, killed %8, %subreg.dsub
    %11:fpr128 = nofpexcept UCVTFv2f64 killed %7, implicit $fpcr
    %12:fpr64 = nofpexcept FCVTNv2i32 killed %11, implicit $fpcr
    %14:fpr128 = IMPLICIT_DEF
    %13:fpr128 = INSERT_SUBREG %14, killed %12, %subreg.dsub
    %15:fpr128 = INSvi64lane %13, 1, killed %9, 0
    %17:fpr64 = COPY %1.dsub
    STRDui killed %17, %0, 2 :: (store (s64) into %ir.0 + 16)
    STRQui killed %15, %0, 0 :: (store (s128) into %ir.0, align 8)
    RET_ReallyLR

...
---
name:            insert_vec_v2i32_uaddlv_from_v8i16
registers:
  - { id: 0, class: gpr64common, preferred-register: '' }
  - { id: 1, class: fpr128, preferred-register: '' }
  - { id: 2, class: fpr32, preferred-register: '' }
  - { id: 3, class: fpr128, preferred-register: '' }
  - { id: 4, class: fpr128, preferred-register: '' }
  - { id: 5, class: gpr32, preferred-register: '' }
  - { id: 6, class: fpr64, preferred-register: '' }
  - { id: 7, class: fpr128, preferred-register: '' }
  - { id: 8, class: fpr128, preferred-register: '' }
  - { id: 9, class: fpr128, preferred-register: '' }
  - { id: 10, class: fpr64, preferred-register: '' }
  - { id: 11, class: fpr64, preferred-register: '' }
liveins:
  - { reg: '$x0', virtual-reg: '%0' }
body:             |
  bb.0.entry:
    liveins: $x0

    ; CHECK-LABEL: name: insert_vec_v2i32_uaddlv_from_v8i16
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
    ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
    ; CHECK-NEXT: [[UADDLVv8i16v:%[0-9]+]]:fpr32 = UADDLVv8i16v killed [[MOVIv2d_ns]]
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], killed [[UADDLVv8i16v]], %subreg.ssub
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].ssub
    ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 0
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], killed [[MOVID]], %subreg.dsub
    ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG1]], 0, [[INSERT_SUBREG]], 0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub
    ; CHECK-NEXT: [[UCVTFv2f32_:%[0-9]+]]:fpr64 = nofpexcept UCVTFv2f32 killed [[COPY2]], implicit $fpcr
    ; CHECK-NEXT: STRDui killed [[UCVTFv2f32_]], [[COPY]], 0 :: (store (s64) into %ir.0)
    ; CHECK-NEXT: RET_ReallyLR
    %0:gpr64common = COPY $x0
    %1:fpr128 = MOVIv2d_ns 0
    %2:fpr32 = UADDLVv8i16v killed %1
    %4:fpr128 = IMPLICIT_DEF
    %3:fpr128 = INSERT_SUBREG %4, killed %2, %subreg.ssub
    %5:gpr32 = COPY %3.ssub
    %6:fpr64 = MOVID 0
    %8:fpr128 = IMPLICIT_DEF
    %7:fpr128 = INSERT_SUBREG %8, killed %6, %subreg.dsub
    %9:fpr128 = INSvi32gpr %7, 0, killed %5
    %10:fpr64 = COPY %9.dsub
    %11:fpr64 = nofpexcept UCVTFv2f32 killed %10, implicit $fpcr
    STRDui killed %11, %0, 0 :: (store (s64) into %ir.0)
    RET_ReallyLR

...
---
name:            insert_vec_v8i16_uaddlv_from_v8i16
registers:
  - { id: 0, class: gpr64common, preferred-register: '' }
  - { id: 1, class: fpr128, preferred-register: '' }
  - { id: 2, class: fpr32, preferred-register: '' }
  - { id: 3, class: fpr128, preferred-register: '' }
  - { id: 4, class: fpr128, preferred-register: '' }
  - { id: 5, class: gpr32, preferred-register: '' }
  - { id: 6, class: fpr64, preferred-register: '' }
  - { id: 7, class: fpr128, preferred-register: '' }
  - { id: 8, class: fpr128, preferred-register: '' }
  - { id: 9, class: fpr128, preferred-register: '' }
  - { id: 10, class: fpr64, preferred-register: '' }
  - { id: 11, class: fpr128, preferred-register: '' }
  - { id: 12, class: fpr128, preferred-register: '' }
  - { id: 13, class: gpr32, preferred-register: '' }
liveins:
  - { reg: '$x0', virtual-reg: '%0' }
body:             |
  bb.0.entry:
    liveins: $x0

    ; CHECK-LABEL: name: insert_vec_v8i16_uaddlv_from_v8i16
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
    ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
    ; CHECK-NEXT: [[UADDLVv8i16v:%[0-9]+]]:fpr32 = UADDLVv8i16v killed [[MOVIv2d_ns]]
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], killed [[UADDLVv8i16v]], %subreg.ssub
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].ssub
    ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 0
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], killed [[MOVID]], %subreg.dsub
    ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG1]], 0, [[INSERT_SUBREG]], 0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane]].dsub
    ; CHECK-NEXT: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift killed [[COPY2]], 0
    ; CHECK-NEXT: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv4f32 killed [[USHLLv4i16_shift]], implicit $fpcr
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK-NEXT: STRWui [[COPY3]], [[COPY]], 7 :: (store (s32) into %ir.0 + 28)
    ; CHECK-NEXT: STRWui [[COPY3]], [[COPY]], 6 :: (store (s32) into %ir.0 + 24, align 8)
    ; CHECK-NEXT: STRWui [[COPY3]], [[COPY]], 5 :: (store (s32) into %ir.0 + 20)
    ; CHECK-NEXT: STRWui [[COPY3]], [[COPY]], 4 :: (store (s32) into %ir.0 + 16, align 8)
    ; CHECK-NEXT: STRQui killed [[UCVTFv4f32_]], [[COPY]], 0 :: (store (s128) into %ir.0, align 8)
    ; CHECK-NEXT: RET_ReallyLR
    %0:gpr64common = COPY $x0
    %1:fpr128 = MOVIv2d_ns 0
    %2:fpr32 = UADDLVv8i16v killed %1
    %4:fpr128 = IMPLICIT_DEF
    %3:fpr128 = INSERT_SUBREG %4, killed %2, %subreg.ssub
    %5:gpr32 = COPY %3.ssub
    %6:fpr64 = MOVID 0
    %8:fpr128 = IMPLICIT_DEF
    %7:fpr128 = INSERT_SUBREG %8, killed %6, %subreg.dsub
    %9:fpr128 = INSvi16gpr %7, 0, killed %5
    %10:fpr64 = COPY %9.dsub
    %11:fpr128 = USHLLv4i16_shift killed %10, 0
    %12:fpr128 = nofpexcept UCVTFv4f32 killed %11, implicit $fpcr
    %13:gpr32 = COPY $wzr
    STRWui %13, %0, 7 :: (store (s32) into %ir.0 + 28)
    STRWui %13, %0, 6 :: (store (s32) into %ir.0 + 24, align 8)
    STRWui %13, %0, 5 :: (store (s32) into %ir.0 + 20)
    STRWui %13, %0, 4 :: (store (s32) into %ir.0 + 16, align 8)
    STRQui killed %12, %0, 0 :: (store (s128) into %ir.0, align 8)
    RET_ReallyLR

...
---
name:            insert_vec_v16i8_uaddlv_from_v4i32
registers:
  - { id: 0, class: gpr64common, preferred-register: '' }
  - { id: 1, class: fpr128, preferred-register: '' }
  - { id: 2, class: fpr64, preferred-register: '' }
  - { id: 3, class: fpr128, preferred-register: '' }
  - { id: 4, class: fpr128, preferred-register: '' }
  - { id: 5, class: gpr64all, preferred-register: '' }
  - { id: 6, class: gpr32, preferred-register: '' }
  - { id: 7, class: fpr64, preferred-register: '' }
  - { id: 8, class: fpr128, preferred-register: '' }
  - { id: 9, class: fpr128, preferred-register: '' }
  - { id: 10, class: fpr128, preferred-register: '' }
  - { id: 11, class: fpr64, preferred-register: '' }
  - { id: 12, class: fpr64, preferred-register: '' }
  - { id: 13, class: fpr64, preferred-register: '' }
  - { id: 14, class: fpr64, preferred-register: '' }
  - { id: 15, class: fpr128, preferred-register: '' }
  - { id: 16, class: fpr128, preferred-register: '' }
  - { id: 17, class: fpr128, preferred-register: '' }
liveins:
  - { reg: '$x0', virtual-reg: '%0' }
body:             |
  bb.0.entry:
    liveins: $x0

    ; CHECK-LABEL: name: insert_vec_v16i8_uaddlv_from_v4i32
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
    ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
    ; CHECK-NEXT: [[UADDLVv4i32v:%[0-9]+]]:fpr64 = UADDLVv4i32v [[MOVIv2d_ns]]
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], killed [[UADDLVv4i32v]], %subreg.dsub
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64all = COPY [[INSERT_SUBREG]].dsub
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]].sub_32
    ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 0
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], killed [[MOVID]], %subreg.dsub
    ; CHECK-NEXT: [[INSvi8lane:%[0-9]+]]:fpr128 = INSvi8lane [[INSERT_SUBREG1]], 0, [[INSERT_SUBREG]], 0
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[INSvi8lane]].dsub
    ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr64 = IMPLICIT_DEF
    ; CHECK-NEXT: [[ZIP1v8i8_:%[0-9]+]]:fpr64 = ZIP1v8i8 killed [[COPY3]], killed [[DEF2]]
    ; CHECK-NEXT: [[BICv4i16_:%[0-9]+]]:fpr64 = BICv4i16 [[ZIP1v8i8_]], 255, 8
    ; CHECK-NEXT: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift killed [[BICv4i16_]], 0
    ; CHECK-NEXT: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv4f32 killed [[USHLLv4i16_shift]], implicit $fpcr
    ; CHECK-NEXT: STRQui [[MOVIv2d_ns]], [[COPY]], 3 :: (store (s128) into %ir.0 + 48, align 8)
    ; CHECK-NEXT: STRQui [[MOVIv2d_ns]], [[COPY]], 2 :: (store (s128) into %ir.0 + 32, align 8)
    ; CHECK-NEXT: STRQui [[MOVIv2d_ns]], [[COPY]], 1 :: (store (s128) into %ir.0 + 16, align 8)
    ; CHECK-NEXT: STRQui killed [[UCVTFv4f32_]], [[COPY]], 0 :: (store (s128) into %ir.0, align 8)
    ; CHECK-NEXT: RET_ReallyLR
    %0:gpr64common = COPY $x0
    %1:fpr128 = MOVIv2d_ns 0
    %2:fpr64 = UADDLVv4i32v %1
    %4:fpr128 = IMPLICIT_DEF
    %3:fpr128 = INSERT_SUBREG %4, killed %2, %subreg.dsub
    %5:gpr64all = COPY %3.dsub
    %6:gpr32 = COPY %5.sub_32
    %7:fpr64 = MOVID 0
    %9:fpr128 = IMPLICIT_DEF
    %8:fpr128 = INSERT_SUBREG %9, killed %7, %subreg.dsub
    %10:fpr128 = INSvi8gpr %8, 0, killed %6
    %11:fpr64 = COPY %10.dsub
    %13:fpr64 = IMPLICIT_DEF
    %12:fpr64 = ZIP1v8i8 killed %11, killed %13
    %14:fpr64 = BICv4i16 %12, 255, 8
    %15:fpr128 = USHLLv4i16_shift killed %14, 0
    %16:fpr128 = nofpexcept UCVTFv4f32 killed %15, implicit $fpcr
    STRQui %1, %0, 3 :: (store (s128) into %ir.0 + 48, align 8)
    STRQui %1, %0, 2 :: (store (s128) into %ir.0 + 32, align 8)
    STRQui %1, %0, 1 :: (store (s128) into %ir.0 + 16, align 8)
    STRQui killed %16, %0, 0 :: (store (s128) into %ir.0, align 8)
    RET_ReallyLR

...
---
name:            insert_vec_v2i32_uaddlv_from_v8i16_nz_index
registers:
  - { id: 0, class: gpr64common, preferred-register: '' }
  - { id: 1, class: fpr128, preferred-register: '' }
  - { id: 2, class: fpr32, preferred-register: '' }
  - { id: 3, class: fpr128, preferred-register: '' }
  - { id: 4, class: fpr128, preferred-register: '' }
  - { id: 5, class: gpr32, preferred-register: '' }
  - { id: 6, class: fpr128, preferred-register: '' }
  - { id: 7, class: fpr128, preferred-register: '' }
  - { id: 8, class: fpr128, preferred-register: '' }
liveins:
  - { reg: '$x0', virtual-reg: '%0' }
body:             |
  bb.0.entry:
    liveins: $x0

    ; CHECK-LABEL: name: insert_vec_v2i32_uaddlv_from_v8i16_nz_index
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
    ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
    ; CHECK-NEXT: [[UADDLVv8i16v:%[0-9]+]]:fpr32 = UADDLVv8i16v [[MOVIv2d_ns]]
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], killed [[UADDLVv8i16v]], %subreg.ssub
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].ssub
    ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[MOVIv2d_ns]], 2, [[INSERT_SUBREG]], 0
    ; CHECK-NEXT: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv4f32 killed [[INSvi32lane]], implicit $fpcr
    ; CHECK-NEXT: STRQui killed [[UCVTFv4f32_]], [[COPY]], 0 :: (store (s128) into %ir.0, align 8)
    ; CHECK-NEXT: RET_ReallyLR
    %0:gpr64common = COPY $x0
    %1:fpr128 = MOVIv2d_ns 0
    %2:fpr32 = UADDLVv8i16v %1
    %4:fpr128 = IMPLICIT_DEF
    %3:fpr128 = INSERT_SUBREG %4, killed %2, %subreg.ssub
    %5:gpr32 = COPY %3.ssub
    %7:fpr128 = INSvi32gpr %1, 2, killed %5
    %8:fpr128 = nofpexcept UCVTFv4f32 killed %7, implicit $fpcr
    STRQui killed %8, %0, 0 :: (store (s128) into %ir.0, align 8)
    RET_ReallyLR

...
---
name:            insert_vec_from_gpr
registers:
  - { id: 0, class: gpr32, preferred-register: '' }
  - { id: 1, class: gpr64common, preferred-register: '' }
  - { id: 2, class: gpr64, preferred-register: '' }
  - { id: 3, class: gpr64all, preferred-register: '' }
  - { id: 4, class: gpr64common, preferred-register: '' }
  - { id: 5, class: gpr64common, preferred-register: '' }
  - { id: 6, class: fpr128, preferred-register: '' }
  - { id: 7, class: fpr128, preferred-register: '' }
liveins:
  - { reg: '$w0', virtual-reg: '%0' }
  - { reg: '$x1', virtual-reg: '%1' }
stack:
  - { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 16,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      local-offset: -16, debug-info-variable: '', debug-info-expression: '',
      debug-info-location: '' }
body:             |
  bb.0.entry:
    liveins: $w0, $x1

    ; CHECK-LABEL: name: insert_vec_from_gpr
    ; CHECK: liveins: $w0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_32
    ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64common = ADDXri %stack.0, 0, 0
    ; CHECK-NEXT: [[BFMXri:%[0-9]+]]:gpr64common = BFMXri [[ADDXri]], killed [[INSERT_SUBREG]], 62, 1
    ; CHECK-NEXT: STRWui [[COPY1]], killed [[BFMXri]], 0 :: (store (s32))
    ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui %stack.0, 0 :: (load (s128) from %stack.0)
    ; CHECK-NEXT: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[LDRQui]], 1, [[COPY1]]
    ; CHECK-NEXT: STRQui killed [[INSvi32gpr]], [[COPY]], 0 :: (store (s128) into %ir.p, align 4)
    ; CHECK-NEXT: RET_ReallyLR
    %1:gpr64common = COPY $x1
    %0:gpr32 = COPY $w0
    %3:gpr64all = IMPLICIT_DEF
    %2:gpr64 = INSERT_SUBREG %3, %0, %subreg.sub_32
    %4:gpr64common = ADDXri %stack.0, 0, 0
    %5:gpr64common = BFMXri %4, killed %2, 62, 1
    STRWui %0, killed %5, 0 :: (store (s32))
    %6:fpr128 = LDRQui %stack.0, 0 :: (load (s128) from %stack.0)
    %7:fpr128 = INSvi32gpr %6, 1, %0
    STRQui killed %7, %1, 0 :: (store (s128) into %ir.p, align 4)
    RET_ReallyLR

...
---
name:            fadd
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: fpr64, preferred-register: '' }
  - { id: 1, class: fpr64, preferred-register: '' }
  - { id: 2, class: fpr64, preferred-register: '' }
  - { id: 3, class: fpr128, preferred-register: '' }
  - { id: 4, class: fpr64, preferred-register: '' }
  - { id: 5, class: fpr128, preferred-register: '' }
  - { id: 6, class: fpr128, preferred-register: '' }
  - { id: 7, class: fpr128, preferred-register: '' }
  - { id: 8, class: fpr128, preferred-register: '' }
  - { id: 9, class: fpr128, preferred-register: '' }
liveins:
  - { reg: '$d0', virtual-reg: '%0' }
  - { reg: '$d1', virtual-reg: '%1' }
body:             |
  bb.0.entry:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: fadd
    ; CHECK: liveins: $d0, $d1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY1]], [[COPY]], implicit $fpcr
    ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], killed [[COPY2]], %subreg.dsub
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], killed [[FADDDrr]], %subreg.dsub
    ; CHECK-NEXT: $q0 = COPY [[INSERT_SUBREG1]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %1:fpr64 = COPY $d1
    %0:fpr64 = COPY $d0
    %2:fpr64 = nofpexcept FADDDrr %0, %1, implicit $fpcr
    %3:fpr128 = MOVIv2d_ns 0
    %4:fpr64 = COPY %3.dsub
    %6:fpr128 = IMPLICIT_DEF
    %5:fpr128 = INSERT_SUBREG %6, killed %4, %subreg.dsub
    %8:fpr128 = IMPLICIT_DEF
    %7:fpr128 = INSERT_SUBREG %8, killed %2, %subreg.dsub
    %9:fpr128 = INSvi64lane %7, 1, killed %5, 0
    $q0 = COPY %9
    RET_ReallyLR implicit $q0

...
---
name:            asm
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr64common, preferred-register: '' }
  - { id: 1, class: fpr64, preferred-register: '' }
  - { id: 2, class: gpr64all, preferred-register: '' }
  - { id: 3, class: gpr64sp, preferred-register: '' }
  - { id: 4, class: fpr128, preferred-register: '' }
  - { id: 5, class: fpr64, preferred-register: '' }
  - { id: 6, class: fpr128, preferred-register: '' }
  - { id: 7, class: fpr128, preferred-register: '' }
  - { id: 8, class: fpr128, preferred-register: '' }
  - { id: 9, class: fpr128, preferred-register: '' }
  - { id: 10, class: fpr128, preferred-register: '' }
  - { id: 11, class: fpr64, preferred-register: '' }
  - { id: 12, class: fpr64, preferred-register: '' }
  - { id: 13, class: fpr128, preferred-register: '' }
  - { id: 14, class: fpr128, preferred-register: '' }
  - { id: 15, class: gpr32all, preferred-register: '' }
  - { id: 16, class: fpr32, preferred-register: '' }
liveins:
  - { reg: '$x0', virtual-reg: '%0' }
body:             |
  bb.0.entry:
    liveins: $x0

    ; CHECK-LABEL: name: asm
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[DEF]]
    ; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 2359306 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed [[COPY1]]
    ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], killed [[COPY2]], %subreg.dsub
    ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], %1, %subreg.dsub
    ; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, killed [[INSERT_SUBREG]], 0
    ; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr64 = IMPLICIT_DEF
    ; CHECK-NEXT: [[TBLv8i8One:%[0-9]+]]:fpr64 = TBLv8i8One killed [[INSvi64lane]], killed [[DEF3]]
    ; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
    ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], killed [[TBLv8i8One]], %subreg.dsub
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[INSERT_SUBREG2]].ssub
    ; CHECK-NEXT: STRSui killed [[COPY3]], [[COPY]], 0 :: (store (s32) into %ir.hist)
    ; CHECK-NEXT: RET_ReallyLR
    %0:gpr64common = COPY $x0
    %2:gpr64all = IMPLICIT_DEF
    %3:gpr64sp = COPY %2
    INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 2359306 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed %3
    %4:fpr128 = MOVIv2d_ns 0
    %5:fpr64 = COPY %4.dsub
    %7:fpr128 = IMPLICIT_DEF
    %6:fpr128 = INSERT_SUBREG %7, killed %5, %subreg.dsub
    %9:fpr128 = IMPLICIT_DEF
    %8:fpr128 = INSERT_SUBREG %9, %1, %subreg.dsub
    %10:fpr128 = INSvi64lane %8, 1, killed %6, 0
    %12:fpr64 = IMPLICIT_DEF
    %11:fpr64 = TBLv8i8One killed %10, killed %12
    %14:fpr128 = IMPLICIT_DEF
    %13:fpr128 = INSERT_SUBREG %14, killed %11, %subreg.dsub
    %16:fpr32 = COPY %13.ssub
    STRSui killed %16, %0, 0 :: (store (s32) into %ir.hist)
    RET_ReallyLR

...