src/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-divrem-insertpt-conflict.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s

---
name:            test
alignment:       4
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: test
    ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
    ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
    ; CHECK-NEXT: [[UDIVREM:%[0-9]+]]:_(s32), [[UDIVREM1:%[0-9]+]]:_ = G_UDIVREM [[SEXT]], [[SEXT1]]
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UDIVREM1]](s32)
    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UDIVREM]](s32)
    ; CHECK-NEXT: [[SEXT2:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s8)
    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ZEXT]], [[SEXT2]]
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[OR]](s64)
    ; CHECK-NEXT: $w0 = COPY [[TRUNC1]](s32)
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:_(s16) = G_CONSTANT i16 0
    %2:_(s1) = G_CONSTANT i1 true
    %1:_(s1) = G_ICMP intpred(sge), %0(s16), %0
    %3:_(s8) = G_SEXT %2(s1)
    %4:_(s32) = G_SEXT %3(s8)
    %5:_(s32) = G_SEXT %1(s1)
    %6:_(s32) = G_UDIV %4, %5
    %7:_(s32) = COPY %5(s32)
    %8:_(s32) = G_SEXT %2(s1)
    %9:_(s32) = G_UREM %7, %8
    %10:_(s8) = G_TRUNC %9(s32)
    %11:_(s64) = G_ZEXT %6(s32)
    %12:_(s64) = G_SEXT %10(s8)
    %13:_(s64) = G_OR %11, %12
    %14:_(s32) = G_TRUNC %13(s64)
    $w0 = COPY %14(s32)
    RET_ReallyLR implicit $w0

...

# Check with the div and rem the other way around
---
name:            test_inverted_div_rem
alignment:       4
tracksRegLiveness: true
body:             |
  bb.1:
    ; CHECK-LABEL: name: test_inverted_div_rem
    ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
    ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
    ; CHECK-NEXT: [[UDIVREM:%[0-9]+]]:_(s32), [[UDIVREM1:%[0-9]+]]:_ = G_UDIVREM [[SEXT]], [[SEXT1]]
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UDIVREM]](s32)
    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UDIVREM1]](s32)
    ; CHECK-NEXT: [[SEXT2:%[0-9]+]]:_(s64) = G_SEXT [[TRUNC]](s8)
    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ZEXT]], [[SEXT2]]
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[OR]](s64)
    ; CHECK-NEXT: $w0 = COPY [[TRUNC1]](s32)
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:_(s16) = G_CONSTANT i16 0
    %2:_(s1) = G_CONSTANT i1 true
    %1:_(s1) = G_ICMP intpred(sge), %0(s16), %0
    %3:_(s8) = G_SEXT %2(s1)
    %4:_(s32) = G_SEXT %3(s8)
    %5:_(s32) = G_SEXT %1(s1)
    %6:_(s32) = G_UREM %4, %5
    %7:_(s32) = COPY %5(s32)
    %8:_(s32) = G_SEXT %2(s1)
    %9:_(s32) = G_UDIV %7, %8
    %10:_(s8) = G_TRUNC %9(s32)
    %11:_(s64) = G_ZEXT %6(s32)
    %12:_(s64) = G_SEXT %10(s8)
    %13:_(s64) = G_OR %11, %12
    %14:_(s32) = G_TRUNC %13(s64)
    $w0 = COPY %14(s32)
    RET_ReallyLR implicit $w0

...