| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 |
| // REQUIRES: riscv-registered-target |
| // RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \ |
| // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ |
| // RUN: FileCheck --check-prefix=CHECK-RV64 %s |
| |
| #include <riscv_vector.h> |
| |
| // CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vlm_v_b1 |
| // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK-RV64-NEXT: entry: |
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1.i64(ptr [[BASE]], i64 [[VL]]) |
| // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]] |
| // |
| vbool1_t test_vlm_v_b1(const uint8_t *base, size_t vl) { |
| return __riscv_vlm_v_b1(base, vl); |
| } |
| |
| // CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vlm_v_b2 |
| // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { |
| // CHECK-RV64-NEXT: entry: |
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1.i64(ptr [[BASE]], i64 [[VL]]) |
| // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]] |
| // |
| vbool2_t test_vlm_v_b2(const uint8_t *base, size_t vl) { |
| return __riscv_vlm_v_b2(base, vl); |
| } |
| |
| // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vlm_v_b4 |
| // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { |
| // CHECK-RV64-NEXT: entry: |
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1.i64(ptr [[BASE]], i64 [[VL]]) |
| // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]] |
| // |
| vbool4_t test_vlm_v_b4(const uint8_t *base, size_t vl) { |
| return __riscv_vlm_v_b4(base, vl); |
| } |
| |
| // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vlm_v_b8 |
| // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { |
| // CHECK-RV64-NEXT: entry: |
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1.i64(ptr [[BASE]], i64 [[VL]]) |
| // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]] |
| // |
| vbool8_t test_vlm_v_b8(const uint8_t *base, size_t vl) { |
| return __riscv_vlm_v_b8(base, vl); |
| } |
| |
| // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vlm_v_b16 |
| // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { |
| // CHECK-RV64-NEXT: entry: |
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1.i64(ptr [[BASE]], i64 [[VL]]) |
| // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]] |
| // |
| vbool16_t test_vlm_v_b16(const uint8_t *base, size_t vl) { |
| return __riscv_vlm_v_b16(base, vl); |
| } |
| |
| // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vlm_v_b32 |
| // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { |
| // CHECK-RV64-NEXT: entry: |
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1.i64(ptr [[BASE]], i64 [[VL]]) |
| // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]] |
| // |
| vbool32_t test_vlm_v_b32(const uint8_t *base, size_t vl) { |
| return __riscv_vlm_v_b32(base, vl); |
| } |
| |
| // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vlm_v_b64 |
| // CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { |
| // CHECK-RV64-NEXT: entry: |
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1.i64(ptr [[BASE]], i64 [[VL]]) |
| // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]] |
| // |
| vbool64_t test_vlm_v_b64(const uint8_t *base, size_t vl) { |
| return __riscv_vlm_v_b64(base, vl); |
| } |
| |