src/llvm-project/llvm/test/CodeGen/AArch64/machine-cp-sub-reg.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -o - %s --run-pass=machine-cp -mcp-use-is-copy-instr -mtriple=arm64-apple-macos --verify-machineinstrs | FileCheck %s

---
name: test
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $w0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $x8 = ORRXrs $xzr, $x0, 0, implicit $w0
  ; CHECK-NEXT:   $w8 = ORRWrs $wzr, $w0, 0, implicit-def $x8
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   liveins: $x8
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $x0 = ADDXri $x8, 1, 0
  ; CHECK-NEXT:   RET undef $lr, implicit $x0
  bb.0:
    successors: %bb.1(0x80000000)
    liveins: $w0

    $x8 = ORRXrs $xzr, $x0, 0, implicit $w0
    $w8 = ORRWrs $wzr, $w0, 0, implicit-def $x8

  bb.1:
    liveins: $x8
    $x0 = ADDXri $x8, 1, 0

    RET undef $lr, implicit $x0
...