Snap for 10453563 from 93b2587c31be5eacdf1ab77cad1867b39f82fbfe to mainline-permission-release
Change-Id: I3c8f72111602c09d57ed916b32ea2785584c62cc
diff --git a/.cargo_vcs_info.json b/.cargo_vcs_info.json
index 66f2471..d77758c 100644
--- a/.cargo_vcs_info.json
+++ b/.cargo_vcs_info.json
@@ -1,5 +1,6 @@
{
"git": {
- "sha1": "4e14680234812020427385521d7d6cad585c4905"
- }
-}
+ "sha1": "eb9d7be4a4095440171986b41d6ffc9fb3be1d74"
+ },
+ "path_in_vcs": "gdbstub_arch"
+}
\ No newline at end of file
diff --git a/Android.bp b/Android.bp
index 8d3cccd..141e1ae 100644
--- a/Android.bp
+++ b/Android.bp
@@ -23,7 +23,7 @@
host_supported: true,
crate_name: "gdbstub_arch",
cargo_env_compat: true,
- cargo_pkg_version: "0.1.1",
+ cargo_pkg_version: "0.2.4",
srcs: ["src/lib.rs"],
test_suites: ["general-tests"],
auto_gen_config: true,
@@ -42,11 +42,17 @@
host_supported: true,
crate_name: "gdbstub_arch",
cargo_env_compat: true,
- cargo_pkg_version: "0.1.1",
+ cargo_pkg_version: "0.2.4",
srcs: ["src/lib.rs"],
edition: "2018",
rustlibs: [
"libgdbstub",
"libnum_traits",
],
+ apex_available: [
+ "//apex_available:platform",
+ "//apex_available:anyapex",
+ ],
+ product_available: true,
+ vendor_available: true,
}
diff --git a/CHANGELOG.md b/CHANGELOG.md
new file mode 100644
index 0000000..ae6d63f
--- /dev/null
+++ b/CHANGELOG.md
@@ -0,0 +1,40 @@
+All notable changes to this project will be documented in this file.
+
+This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
+
+# 0.2.4
+
+- Add support for AArch64 [\#109](https://github.com/daniel5151/gdbstub/pull/109) ([ptosi](https://github.com/ptosi))
+
+# 0.2.3
+
+- Fix missing reg_id mapping in `Armv4t` (24 => Fps)
+
+# 0.2.2
+
+- Remove faulty target.xml from mips64 arch
+
+# 0.2.1
+
+- Removed all remaining instances of `SingleStepGdbBehavior::Unknown` [\#95](https://github.com/daniel5151/gdbstub/pull/95) ([bet4it](https://github.com/bet4it))
+
+# 0.2.0
+
+**Bumps required `gdbstub` version to 0.6.0**.
+
+#### Breaking Arch Changes
+
+- Improved support + fixes for `Msp430` [\#62](https://github.com/daniel5151/gdbstub/pull/62) ([mchesser](https://github.com/mchesser))
+- `X86_64CoreRegId`: Change rip size to 8 [\#87](https://github.com/daniel5151/gdbstub/pull/87) ([gz](https://github.com/gz))
+- Removed `RegId` template parameters from the following `Arch` implementations:
+ - x86/x64
+ - MIPS
+ - MSP-430
+
+# 0.1.0
+
+**Bumps required `gdbstub` version to 0.5.0**.
+
+- **`gdbstub::arch` has been moved into a separate `gdbstub_arch` crate**
+ - _See [\#45](https://github.com/daniel5151/gdbstub/issues/45) for details on why this was done._
+- (x86) Break GPRs & SRs into individual fields/variants [\#34](https://github.com/daniel5151/gdbstub/issues/34)
diff --git a/Cargo.toml b/Cargo.toml
index 7190872..f195a38 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -3,28 +3,38 @@
# When uploading crates to the registry Cargo will automatically
# "normalize" Cargo.toml files for maximal compatibility
# with all versions of Cargo and also rewrite `path` dependencies
-# to registry (e.g., crates.io) dependencies
+# to registry (e.g., crates.io) dependencies.
#
-# If you believe there's an error in this file please file an
-# issue against the rust-lang/cargo repository. If you're
-# editing this file be aware that the upstream Cargo.toml
-# will likely look very different (and much more reasonable)
+# If you are reading this file be aware that the original Cargo.toml
+# will likely look very different (and much more reasonable).
+# See Cargo.toml.orig for the original contents.
[package]
edition = "2018"
name = "gdbstub_arch"
-version = "0.1.1"
+version = "0.2.4"
authors = ["Daniel Prilik <danielprilik@gmail.com>"]
description = "Implementations of `gdbstub::arch::Arch` for various architectures."
homepage = "https://github.com/daniel5151/gdbstub"
documentation = "https://docs.rs/gdbstub_arch"
readme = "README.md"
-keywords = ["gdb", "emulation", "no_std", "debugging"]
-categories = ["development-tools::debugging", "embedded", "emulators", "no-std"]
-license = "MIT"
+keywords = [
+ "gdb",
+ "emulation",
+ "no_std",
+ "debugging",
+]
+categories = [
+ "development-tools::debugging",
+ "embedded",
+ "emulators",
+ "no-std",
+]
+license = "MIT OR Apache-2.0"
repository = "https://github.com/daniel5151/gdbstub"
+
[dependencies.gdbstub]
-version = "0.5"
+version = "0.6"
default-features = false
[dependencies.num-traits]
diff --git a/Cargo.toml.orig b/Cargo.toml.orig
index b518f6c..56fec5c 100644
--- a/Cargo.toml.orig
+++ b/Cargo.toml.orig
@@ -2,8 +2,8 @@
name = "gdbstub_arch"
description = "Implementations of `gdbstub::arch::Arch` for various architectures."
authors = ["Daniel Prilik <danielprilik@gmail.com>"]
-version = "0.1.1"
-license = "MIT"
+version = "0.2.4"
+license = "MIT OR Apache-2.0"
edition = "2018"
readme = "README.md"
documentation = "https://docs.rs/gdbstub_arch"
@@ -13,6 +13,6 @@
categories = ["development-tools::debugging", "embedded", "emulators", "no-std"]
[dependencies]
-gdbstub = { path = "../", version = "0.5", default-features = false }
+gdbstub = { path = "../", version = "0.6", default-features = false }
num-traits = { version = "0.2", default-features = false }
diff --git a/LICENSE b/LICENSE
index 62c6168..a9503b1 100644
--- a/LICENSE
+++ b/LICENSE
@@ -1,21 +1,6 @@
-MIT License
+gdbstub_arch is dual-licensed under either
-Copyright (c) 2021 Daniel Prilik
+* MIT License (../docs/LICENSE-MIT or http://opensource.org/licenses/MIT)
+* Apache License, Version 2.0 (../docs/LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
+at your option.
diff --git a/METADATA b/METADATA
index 46123e2..24787ac 100644
--- a/METADATA
+++ b/METADATA
@@ -7,13 +7,13 @@
}
url {
type: ARCHIVE
- value: "https://static.crates.io/crates/gdbstub_arch/gdbstub_arch-0.1.1.crate"
+ value: "https://static.crates.io/crates/gdbstub_arch/gdbstub_arch-0.2.4.crate"
}
- version: "0.1.1"
+ version: "0.2.4"
license_type: NOTICE
last_upgrade_date {
- year: 2021
- month: 9
+ year: 2022
+ month: 8
day: 22
}
}
diff --git a/README.md b/README.md
index 92a2e6e..9c62ef2 100644
--- a/README.md
+++ b/README.md
@@ -1,7 +1,8 @@
# gdbstub_arch
-[](https://crates.io/crates/gdbstub_arch)
+[](https://crates.io/crates/gdbstub_arch)
[](https://docs.rs/gdbstub_arch)
+[](./LICENSE)
Community-contributed implementations of `gdbstub::arch::Arch` for various
architectures.
diff --git a/TEST_MAPPING b/TEST_MAPPING
index 571f133..182c85e 100644
--- a/TEST_MAPPING
+++ b/TEST_MAPPING
@@ -1,5 +1,10 @@
// Generated by update_crate_tests.py for tests that depend on this crate.
{
+ "imports": [
+ {
+ "path": "packages/modules/Virtualization/virtualizationmanager"
+ }
+ ],
"presubmit": [
{
"name": "gdbstub_arch_test_src_lib"
diff --git a/src/aarch64/core.xml b/src/aarch64/core.xml
new file mode 100644
index 0000000..4ed85b5
--- /dev/null
+++ b/src/aarch64/core.xml
@@ -0,0 +1,94 @@
+<feature name="org.gnu.gdb.aarch64.core">
+
+<!-- source: binutils-gdb/blob/master/gdb/features/aarch64-core.xml -->
+
+<!-- Copyright (C) 2009-2022 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+ <reg name="x0" bitsize="64"/>
+ <reg name="x1" bitsize="64"/>
+ <reg name="x2" bitsize="64"/>
+ <reg name="x3" bitsize="64"/>
+ <reg name="x4" bitsize="64"/>
+ <reg name="x5" bitsize="64"/>
+ <reg name="x6" bitsize="64"/>
+ <reg name="x7" bitsize="64"/>
+ <reg name="x8" bitsize="64"/>
+ <reg name="x9" bitsize="64"/>
+ <reg name="x10" bitsize="64"/>
+ <reg name="x11" bitsize="64"/>
+ <reg name="x12" bitsize="64"/>
+ <reg name="x13" bitsize="64"/>
+ <reg name="x14" bitsize="64"/>
+ <reg name="x15" bitsize="64"/>
+ <reg name="x16" bitsize="64"/>
+ <reg name="x17" bitsize="64"/>
+ <reg name="x18" bitsize="64"/>
+ <reg name="x19" bitsize="64"/>
+ <reg name="x20" bitsize="64"/>
+ <reg name="x21" bitsize="64"/>
+ <reg name="x22" bitsize="64"/>
+ <reg name="x23" bitsize="64"/>
+ <reg name="x24" bitsize="64"/>
+ <reg name="x25" bitsize="64"/>
+ <reg name="x26" bitsize="64"/>
+ <reg name="x27" bitsize="64"/>
+ <reg name="x28" bitsize="64"/>
+ <reg name="x29" bitsize="64"/>
+ <reg name="x30" bitsize="64"/>
+ <reg name="sp" bitsize="64" type="data_ptr"/>
+
+ <reg name="pc" bitsize="64" type="code_ptr"/>
+
+ <flags id="cpsr_flags" size="4">
+ <!-- Stack Pointer. -->
+ <field name="SP" start="0" end="0"/>
+
+ <!-- Exception Level. -->
+ <field name="EL" start="2" end="3"/>
+ <!-- Execution state. -->
+ <field name="nRW" start="4" end="4"/>
+
+ <!-- FIQ interrupt mask. -->
+ <field name="F" start="6" end="6"/>
+ <!-- IRQ interrupt mask. -->
+ <field name="I" start="7" end="7"/>
+ <!-- SError interrupt mask. -->
+ <field name="A" start="8" end="8"/>
+ <!-- Debug exception mask. -->
+ <field name="D" start="9" end="9"/>
+
+ <!-- ARMv8.5-A: Branch Target Identification BTYPE. -->
+ <field name="BTYPE" start="10" end="11"/>
+
+ <!-- ARMv8.0-A: Speculative Store Bypass. -->
+ <field name="SSBS" start="12" end="12"/>
+
+ <!-- Illegal Execution state. -->
+ <field name="IL" start="20" end="20"/>
+ <!-- Software Step. -->
+ <field name="SS" start="21" end="21"/>
+ <!-- ARMv8.1-A: Privileged Access Never. -->
+ <field name="PAN" start="22" end="22"/>
+ <!-- ARMv8.2-A: User Access Override. -->
+ <field name="UAO" start="23" end="23"/>
+ <!-- ARMv8.4-A: Data Independent Timing. -->
+ <field name="DIT" start="24" end="24"/>
+ <!-- ARMv8.5-A: Tag Check Override. -->
+ <field name="TCO" start="25" end="25"/>
+
+ <!-- Overflow Condition flag. -->
+ <field name="V" start="28" end="28"/>
+ <!-- Carry Condition flag. -->
+ <field name="C" start="29" end="29"/>
+ <!-- Zero Condition flag. -->
+ <field name="Z" start="30" end="30"/>
+ <!-- Negative Condition flag. -->
+ <field name="N" start="31" end="31"/>
+ </flags>
+ <reg name="cpsr" bitsize="32" type="cpsr_flags"/>
+
+</feature>
diff --git a/src/aarch64/fpu.xml b/src/aarch64/fpu.xml
new file mode 100644
index 0000000..ac8c477
--- /dev/null
+++ b/src/aarch64/fpu.xml
@@ -0,0 +1,160 @@
+<feature name="org.gnu.gdb.aarch64.fpu">
+
+ <!-- source: binutils-gdb/blob/master/gdb/features/aarch64-fpu.xml -->
+
+ <!-- Copyright (C) 2009-2022 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+ <vector id="v2d" type="ieee_double" count="2"/>
+ <vector id="v2u" type="uint64" count="2"/>
+ <vector id="v2i" type="int64" count="2"/>
+ <vector id="v4f" type="ieee_single" count="4"/>
+ <vector id="v4u" type="uint32" count="4"/>
+ <vector id="v4i" type="int32" count="4"/>
+ <vector id="v8f" type="ieee_half" count="8"/>
+ <vector id="v8u" type="uint16" count="8"/>
+ <vector id="v8i" type="int16" count="8"/>
+ <vector id="v8bf16" type="bfloat16" count="8"/>
+ <vector id="v16u" type="uint8" count="16"/>
+ <vector id="v16i" type="int8" count="16"/>
+ <vector id="v1u" type="uint128" count="1"/>
+ <vector id="v1i" type="int128" count="1"/>
+ <union id="vnd">
+ <field name="f" type="v2d"/>
+ <field name="u" type="v2u"/>
+ <field name="s" type="v2i"/>
+ </union>
+ <union id="vns">
+ <field name="f" type="v4f"/>
+ <field name="u" type="v4u"/>
+ <field name="s" type="v4i"/>
+ </union>
+ <union id="vnh">
+ <field name="bf" type="v8bf16"/>
+ <field name="f" type="v8f"/>
+ <field name="u" type="v8u"/>
+ <field name="s" type="v8i"/>
+ </union>
+ <union id="vnb">
+ <field name="u" type="v16u"/>
+ <field name="s" type="v16i"/>
+ </union>
+ <union id="vnq">
+ <field name="u" type="v1u"/>
+ <field name="s" type="v1i"/>
+ </union>
+ <union id="aarch64v">
+ <field name="d" type="vnd"/>
+ <field name="s" type="vns"/>
+ <field name="h" type="vnh"/>
+ <field name="b" type="vnb"/>
+ <field name="q" type="vnq"/>
+ </union>
+ <reg name="v0" bitsize="128" type="aarch64v" regnum="34"/>
+ <reg name="v1" bitsize="128" type="aarch64v" />
+ <reg name="v2" bitsize="128" type="aarch64v" />
+ <reg name="v3" bitsize="128" type="aarch64v" />
+ <reg name="v4" bitsize="128" type="aarch64v" />
+ <reg name="v5" bitsize="128" type="aarch64v" />
+ <reg name="v6" bitsize="128" type="aarch64v" />
+ <reg name="v7" bitsize="128" type="aarch64v" />
+ <reg name="v8" bitsize="128" type="aarch64v" />
+ <reg name="v9" bitsize="128" type="aarch64v" />
+ <reg name="v10" bitsize="128" type="aarch64v"/>
+ <reg name="v11" bitsize="128" type="aarch64v"/>
+ <reg name="v12" bitsize="128" type="aarch64v"/>
+ <reg name="v13" bitsize="128" type="aarch64v"/>
+ <reg name="v14" bitsize="128" type="aarch64v"/>
+ <reg name="v15" bitsize="128" type="aarch64v"/>
+ <reg name="v16" bitsize="128" type="aarch64v"/>
+ <reg name="v17" bitsize="128" type="aarch64v"/>
+ <reg name="v18" bitsize="128" type="aarch64v"/>
+ <reg name="v19" bitsize="128" type="aarch64v"/>
+ <reg name="v20" bitsize="128" type="aarch64v"/>
+ <reg name="v21" bitsize="128" type="aarch64v"/>
+ <reg name="v22" bitsize="128" type="aarch64v"/>
+ <reg name="v23" bitsize="128" type="aarch64v"/>
+ <reg name="v24" bitsize="128" type="aarch64v"/>
+ <reg name="v25" bitsize="128" type="aarch64v"/>
+ <reg name="v26" bitsize="128" type="aarch64v"/>
+ <reg name="v27" bitsize="128" type="aarch64v"/>
+ <reg name="v28" bitsize="128" type="aarch64v"/>
+ <reg name="v29" bitsize="128" type="aarch64v"/>
+ <reg name="v30" bitsize="128" type="aarch64v"/>
+ <reg name="v31" bitsize="128" type="aarch64v"/>
+
+ <flags id="fpsr_flags" size="4">
+ <!-- Invalid Operation cumulative floating-point exception bit. -->
+ <field name="IOC" start="0" end="0"/>
+ <!-- Divide by Zero cumulative floating-point exception bit. -->
+ <field name="DZC" start="1" end="1"/>
+ <!-- Overflow cumulative floating-point exception bit. -->
+ <field name="OFC" start="2" end="2"/>
+ <!-- Underflow cumulative floating-point exception bit. -->
+ <field name="UFC" start="3" end="3"/>
+ <!-- Inexact cumulative floating-point exception bit.. -->
+ <field name="IXC" start="4" end="4"/>
+ <!-- Input Denormal cumulative floating-point exception bit. -->
+ <field name="IDC" start="7" end="7"/>
+ <!-- Cumulative saturation bit, Advanced SIMD only. -->
+ <field name="QC" start="27" end="27"/>
+ <!-- When AArch32 is supported at any Exception level and AArch32
+ floating-point is implemented: Overflow condition flag for AArch32
+ floating-point comparison operations. -->
+ <field name="V" start="28" end="28"/>
+ <!-- When AArch32 is supported at any Exception level and AArch32
+ floating-point is implemented:
+ Carry condition flag for AArch32 floating-point comparison operations.
+ -->
+ <field name="C" start="29" end="29"/>
+ <!-- When AArch32 is supported at any Exception level and AArch32
+ floating-point is implemented:
+ Zero condition flag for AArch32 floating-point comparison operations.
+ -->
+ <field name="Z" start="30" end="30"/>
+ <!-- When AArch32 is supported at any Exception level and AArch32
+ floating-point is implemented:
+ Negative condition flag for AArch32 floating-point comparison
+ operations. -->
+ <field name="N" start="31" end="31"/>
+ </flags>
+ <reg name="fpsr" bitsize="32" type="fpsr_flags"/>
+
+ <flags id="fpcr_flags" size="4">
+ <!-- Flush Inputs to Zero (part of Armv8.7). -->
+ <field name="FIZ" start="0" end="0"/>
+ <!-- Alternate Handling (part of Armv8.7). -->
+ <field name="AH" start="1" end="1"/>
+ <!-- Controls how the output elements other than the lowest element of the
+ vector are determined for Advanced SIMD scalar instructions (part of
+ Armv8.7). -->
+ <field name="NEP" start="2" end="2"/>
+ <!-- Invalid Operation floating-point exception trap enable. -->
+ <field name="IOE" start="8" end="8"/>
+ <!-- Divide by Zero floating-point exception trap enable. -->
+ <field name="DZE" start="9" end="9"/>
+ <!-- Overflow floating-point exception trap enable. -->
+ <field name="OFE" start="10" end="10"/>
+ <!-- Underflow floating-point exception trap enable. -->
+ <field name="UFE" start="11" end="11"/>
+ <!-- Inexact floating-point exception trap enable. -->
+ <field name="IXE" start="12" end="12"/>
+ <!-- Input Denormal floating-point exception trap enable. -->
+ <field name="IDE" start="15" end="15"/>
+ <!-- Flush-to-zero mode control bit on half-precision data-processing
+ instructions. -->
+ <field name="FZ16" start="19" end="19"/>
+ <!-- Rounding Mode control field. -->
+ <field name="RMode" start="22" end="23"/>
+ <!-- Flush-to-zero mode control bit. -->
+ <field name="FZ" start="24" end="24"/>
+ <!-- Default NaN mode control bit. -->
+ <field name="DN" start="25" end="25"/>
+ <!-- Alternative half-precision control bit. -->
+ <field name="AHP" start="26" end="26"/>
+ </flags>
+ <reg name="fpcr" bitsize="32" type="fpcr_flags"/>
+</feature>
diff --git a/src/aarch64/mod.rs b/src/aarch64/mod.rs
new file mode 100644
index 0000000..b5d0052
--- /dev/null
+++ b/src/aarch64/mod.rs
@@ -0,0 +1,40 @@
+//! Implementation for the [AArch64](https://developer.arm.com/documentation/102374)
+//! ARM architecture.
+//!
+//! See PR [#109](https://github.com/daniel5151/gdbstub/pull/109) for more info.
+//!
+//! *Note*: doesn't support the AArch32 execution mode.
+//! *Note*: the target XML currently advertises all system registers to the GDB
+//! client.
+
+use gdbstub::arch::{Arch, SingleStepGdbBehavior};
+
+pub mod reg;
+
+/// Implements `Arch` for ARM AArch64.
+pub struct AArch64 {}
+
+impl Arch for AArch64 {
+ type Usize = u64;
+ type Registers = reg::AArch64CoreRegs;
+ type RegId = reg::id::AArch64RegId;
+ type BreakpointKind = usize;
+
+ fn target_description_xml() -> Option<&'static str> {
+ static DESCRIPTION_XML: &str = concat!(
+ r#"<target version="1.0">"#,
+ "<architecture>aarch64</architecture>",
+ include_str!("core.xml"), // feature "org.gnu.gdb.aarch64.core"
+ include_str!("fpu.xml"), // feature "org.gnu.gdb.aarch64.fpu"
+ include_str!("sysregs.xml"),
+ "</target>",
+ );
+
+ Some(DESCRIPTION_XML)
+ }
+
+ #[inline(always)]
+ fn single_step_gdb_behavior() -> SingleStepGdbBehavior {
+ SingleStepGdbBehavior::Required
+ }
+}
diff --git a/src/aarch64/reg/aarch64_core.rs b/src/aarch64/reg/aarch64_core.rs
new file mode 100644
index 0000000..083c8c1
--- /dev/null
+++ b/src/aarch64/reg/aarch64_core.rs
@@ -0,0 +1,99 @@
+use core::convert::TryInto;
+
+use gdbstub::arch::Registers;
+
+/// AArch64 core registers.
+///
+/// Registers from the `org.gnu.gdb.aarch64.core` and `org.gnu.gdb.aarch64.fpu`
+/// [AArch64 Standard GDB Target Features](https://sourceware.org/gdb/onlinedocs/gdb/AArch64-Features.html).
+#[derive(Debug, Default, Clone, Eq, PartialEq)]
+pub struct AArch64CoreRegs {
+ /// General Purpose Registers (X0-X30)
+ pub x: [u64; 31],
+ /// Stack Pointer
+ pub sp: u64,
+ /// Program Counter
+ pub pc: u64,
+ /// Process State (GDB uses the AArch32 CPSR name)
+ pub cpsr: u32,
+ /// FP & SIMD Registers (V0-V31)
+ pub v: [u128; 32],
+ /// Floating-point Control Register
+ pub fpcr: u32,
+ /// Floating-point Status Register
+ pub fpsr: u32,
+}
+
+impl Registers for AArch64CoreRegs {
+ type ProgramCounter = u64;
+
+ fn pc(&self) -> Self::ProgramCounter {
+ self.pc
+ }
+
+ fn gdb_serialize(&self, mut write_byte: impl FnMut(Option<u8>)) {
+ macro_rules! write_bytes {
+ ($var: expr) => {
+ for b in $var.to_le_bytes() {
+ write_byte(Some(b))
+ }
+ };
+ }
+
+ for reg in self.x.iter() {
+ write_bytes!(reg);
+ }
+ write_bytes!(self.sp);
+ write_bytes!(self.pc);
+ write_bytes!(self.cpsr);
+ for reg in self.v.iter() {
+ write_bytes!(reg);
+ }
+ write_bytes!(self.fpcr);
+ write_bytes!(self.fpsr);
+ }
+
+ fn gdb_deserialize(&mut self, bytes: &[u8]) -> Result<(), ()> {
+ const CPSR_OFF: usize = core::mem::size_of::<u64>() * 33;
+ const FPSIMD_OFF: usize = CPSR_OFF + core::mem::size_of::<u32>();
+ const FPCR_OFF: usize = FPSIMD_OFF + core::mem::size_of::<u128>() * 32;
+ const END: usize = FPCR_OFF + core::mem::size_of::<u32>() * 2;
+
+ if bytes.len() < END {
+ return Err(());
+ }
+
+ let mut regs = bytes[0..CPSR_OFF]
+ .chunks_exact(core::mem::size_of::<u64>())
+ .map(|c| u64::from_le_bytes(c.try_into().unwrap()));
+
+ for reg in self.x.iter_mut() {
+ *reg = regs.next().ok_or(())?
+ }
+ self.sp = regs.next().ok_or(())?;
+ self.pc = regs.next().ok_or(())?;
+
+ let mut regs = bytes[CPSR_OFF..FPSIMD_OFF]
+ .chunks_exact(core::mem::size_of::<u32>())
+ .map(|c| u32::from_le_bytes(c.try_into().unwrap()));
+
+ self.cpsr = regs.next().ok_or(())?;
+
+ let mut regs = bytes[FPSIMD_OFF..FPCR_OFF]
+ .chunks_exact(core::mem::size_of::<u128>())
+ .map(|c| u128::from_le_bytes(c.try_into().unwrap()));
+
+ for reg in self.v.iter_mut() {
+ *reg = regs.next().ok_or(())?
+ }
+
+ let mut regs = bytes[FPCR_OFF..]
+ .chunks_exact(core::mem::size_of::<u32>())
+ .map(|c| u32::from_le_bytes(c.try_into().unwrap()));
+
+ self.fpcr = regs.next().ok_or(())?;
+ self.fpsr = regs.next().ok_or(())?;
+
+ Ok(())
+ }
+}
diff --git a/src/aarch64/reg/id.rs b/src/aarch64/reg/id.rs
new file mode 100644
index 0000000..3d4acc1
--- /dev/null
+++ b/src/aarch64/reg/id.rs
@@ -0,0 +1,1833 @@
+use core::num::NonZeroUsize;
+
+use gdbstub::arch::RegId;
+
+/// AArch64 Architectural Registers.
+///
+/// Represents architectural registers as
+///
+/// - individual variants for those described in section B1.2. _Registers in
+/// AArch64 Execution state_ of the Architecture Reference Manual (DDI
+/// 0487H.a), accessed through their own respective subsets of instructions
+/// _e.g._ GPRs, FP & SIMD, ...
+/// - a generic variant for system registers, accessed through MSR/MRS
+/// instructions, based on their encoding as described in section C5.1. _The
+/// System instruction class encoding space_ when `op0` is `0b10` (_Debug and
+/// trace registers_) or `0b11` (_Non-debug System registers_ and
+/// _Special-purpose registers_), as `0b0x` do not encode registers;
+/// - a variant for the abstraction of process state information, `PSTATE`
+/// (section D1.4.), which should be preferred over field-specific
+/// special-purpose registers (`NZCV`, `DAIF`, ...)
+///
+/// Provides `const` aliases for most system registers as syntactic sugar for
+/// the `System` variant. When those aren't available (_e.g._ for newly-added
+/// registers), the literal representation `System(0baa_bbb_xxxx_yyyy_cc)` may
+/// be used, similarly to the standard assembly symbol,
+/// `S<op0>_<op1>_<CRn>_<CRm>_<op2>`.
+///
+/// To future-proof and greatly simplify the implementation, the target's XML
+/// must encode system registers by using their 16-bit encoding as the `regnum`
+/// property; no clash with architectural registers is possible as the top bit
+/// of the 16-bit value is guaranteed to be set.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[non_exhaustive]
+pub enum AArch64RegId {
+ /// General-purpose Register File (X0 - X30)
+ X(u8),
+ /// Stack Pointer
+ Sp,
+ /// Program Counter
+ Pc,
+ /// Process State (Pseudo-Register)
+ Pstate,
+ /// SIMD & FP Register File (V0 - V31)
+ V(u8),
+ /// System Registers encoded as (Op0:2, Op1:3, CRn:4, CRm:4, Op2:2)
+ System(u16),
+}
+
+impl RegId for AArch64RegId {
+ fn from_raw_id(id: usize) -> Option<(Self, Option<NonZeroUsize>)> {
+ let reg = match id {
+ 0..=30 => Self::X(id as u8),
+ 31 => Self::Sp,
+ 32 => Self::Pc,
+ 33 => Self::Pstate,
+ 34..=65 => Self::V((id - 34) as u8),
+ 66 => Self::FPSR,
+ 67 => Self::FPCR,
+ #[allow(clippy::unusual_byte_groupings)]
+ // We configure GDB to use regnums that correspond to the architectural u16 opcode
+ // and avoid clashes with core registers thanks to op0==0b00 and op0==0b01 not being
+ // allocated for system registers.
+ 0b10_000_0000_0000_000..=0b11_111_1111_1111_111 => Self::System(id as u16),
+ _ => return None,
+ };
+
+ Some((reg, Some(NonZeroUsize::new(reg.len()?)?)))
+ }
+}
+
+#[allow(clippy::unusual_byte_groupings)]
+impl AArch64RegId {
+ #[allow(clippy::len_without_is_empty)]
+ /// Gives the size of the register.
+ pub fn len(&self) -> Option<usize> {
+ match self {
+ Self::Pstate => Some(core::mem::size_of::<u32>()),
+ Self::X(_n @ 0..=30) => Some(core::mem::size_of::<u64>()),
+ Self::V(_n @ 0..=31) => Some(core::mem::size_of::<u128>()),
+ Self::Pc | Self::Sp | Self::System(_) => Some(core::mem::size_of::<u64>()),
+ _ => None,
+ }
+ }
+
+ /// Main ID Register
+ pub const MIDR_EL1: Self = Self::System(0b11_000_0000_0000_000);
+ /// Multiprocessor Affinity Register
+ pub const MPIDR_EL1: Self = Self::System(0b11_000_0000_0000_101);
+ /// Revision ID Register
+ pub const REVIDR_EL1: Self = Self::System(0b11_000_0000_0000_110);
+ /// AArch32 Processor Feature Register 0
+ pub const ID_PFR0_EL1: Self = Self::System(0b11_000_0000_0001_000);
+ /// AArch32 Processor Feature Register 1
+ pub const ID_PFR1_EL1: Self = Self::System(0b11_000_0000_0001_001);
+ /// AArch32 Debug Feature Register 0
+ pub const ID_DFR0_EL1: Self = Self::System(0b11_000_0000_0001_010);
+ /// AArch32 Auxiliary Feature Register 0
+ pub const ID_AFR0_EL1: Self = Self::System(0b11_000_0000_0001_011);
+ /// AArch32 Memory Model Feature Register 0
+ pub const ID_MMFR0_EL1: Self = Self::System(0b11_000_0000_0001_100);
+ /// AArch32 Memory Model Feature Register 1
+ pub const ID_MMFR1_EL1: Self = Self::System(0b11_000_0000_0001_101);
+ /// AArch32 Memory Model Feature Register 2
+ pub const ID_MMFR2_EL1: Self = Self::System(0b11_000_0000_0001_110);
+ /// AArch32 Memory Model Feature Register 3
+ pub const ID_MMFR3_EL1: Self = Self::System(0b11_000_0000_0001_111);
+ /// AArch32 Instruction Set Attribute Register 0
+ pub const ID_ISAR0_EL1: Self = Self::System(0b11_000_0000_0010_000);
+ /// AArch32 Instruction Set Attribute Register 1
+ pub const ID_ISAR1_EL1: Self = Self::System(0b11_000_0000_0010_001);
+ /// AArch32 Instruction Set Attribute Register 2
+ pub const ID_ISAR2_EL1: Self = Self::System(0b11_000_0000_0010_010);
+ /// AArch32 Instruction Set Attribute Register 3
+ pub const ID_ISAR3_EL1: Self = Self::System(0b11_000_0000_0010_011);
+ /// AArch32 Instruction Set Attribute Register 4
+ pub const ID_ISAR4_EL1: Self = Self::System(0b11_000_0000_0010_100);
+ /// AArch32 Instruction Set Attribute Register 5
+ pub const ID_ISAR5_EL1: Self = Self::System(0b11_000_0000_0010_101);
+ /// AArch32 Memory Model Feature Register 4
+ pub const ID_MMFR4_EL1: Self = Self::System(0b11_000_0000_0010_110);
+ /// AArch32 Instruction Set Attribute Register 6
+ pub const ID_ISAR6_EL1: Self = Self::System(0b11_000_0000_0010_111);
+ /// AArch32 Media And VFP Feature Register 0
+ pub const MVFR0_EL1: Self = Self::System(0b11_000_0000_0011_000);
+ /// AArch32 Media And VFP Feature Register 1
+ pub const MVFR1_EL1: Self = Self::System(0b11_000_0000_0011_001);
+ /// AArch32 Media And VFP Feature Register 2
+ pub const MVFR2_EL1: Self = Self::System(0b11_000_0000_0011_010);
+ /// AArch32 Processor Feature Register 2
+ pub const ID_PFR2_EL1: Self = Self::System(0b11_000_0000_0011_100);
+ /// Debug Feature Register 1
+ pub const ID_DFR1_EL1: Self = Self::System(0b11_000_0000_0011_101);
+ /// AArch32 Memory Model Feature Register 5
+ pub const ID_MMFR5_EL1: Self = Self::System(0b11_000_0000_0011_110);
+ /// AArch64 Processor Feature Register 0
+ pub const ID_AA64PFR0_EL1: Self = Self::System(0b11_000_0000_0100_000);
+ /// AArch64 Processor Feature Register 1
+ pub const ID_AA64PFR1_EL1: Self = Self::System(0b11_000_0000_0100_001);
+ /// SVE Feature ID Register 0
+ pub const ID_AA64ZFR0_EL1: Self = Self::System(0b11_000_0000_0100_100);
+ /// SME Feature ID Register 0
+ pub const ID_AA64SMFR0_EL1: Self = Self::System(0b11_000_0000_0100_101);
+ /// AArch64 Debug Feature Register 0
+ pub const ID_AA64DFR0_EL1: Self = Self::System(0b11_000_0000_0101_000);
+ /// AArch64 Debug Feature Register 1
+ pub const ID_AA64DFR1_EL1: Self = Self::System(0b11_000_0000_0101_001);
+ /// AArch64 Auxiliary Feature Register 0
+ pub const ID_AA64AFR0_EL1: Self = Self::System(0b11_000_0000_0101_100);
+ /// AArch64 Auxiliary Feature Register 1
+ pub const ID_AA64AFR1_EL1: Self = Self::System(0b11_000_0000_0101_101);
+ /// AArch64 Instruction Set Attribute Register 0
+ pub const ID_AA64ISAR0_EL1: Self = Self::System(0b11_000_0000_0110_000);
+ /// AArch64 Instruction Set Attribute Register 1
+ pub const ID_AA64ISAR1_EL1: Self = Self::System(0b11_000_0000_0110_001);
+ /// AArch64 Instruction Set Attribute Register 2
+ pub const ID_AA64ISAR2_EL1: Self = Self::System(0b11_000_0000_0110_010);
+ /// AArch64 Memory Model Feature Register 0
+ pub const ID_AA64MMFR0_EL1: Self = Self::System(0b11_000_0000_0111_000);
+ /// AArch64 Memory Model Feature Register 1
+ pub const ID_AA64MMFR1_EL1: Self = Self::System(0b11_000_0000_0111_001);
+ /// AArch64 Memory Model Feature Register 2
+ pub const ID_AA64MMFR2_EL1: Self = Self::System(0b11_000_0000_0111_010);
+ /// System Control Register (EL1)
+ pub const SCTLR_EL1: Self = Self::System(0b11_000_0001_0000_000);
+ /// Auxiliary Control Register (EL1)
+ pub const ACTLR_EL1: Self = Self::System(0b11_000_0001_0000_001);
+ /// Architectural Feature Access Control Register
+ pub const CPACR_EL1: Self = Self::System(0b11_000_0001_0000_010);
+ /// Random Allocation Tag Seed Register
+ pub const RGSR_EL1: Self = Self::System(0b11_000_0001_0000_101);
+ /// Tag Control Register
+ pub const GCR_EL1: Self = Self::System(0b11_000_0001_0000_110);
+ /// SVE Control Register (EL1)
+ pub const ZCR_EL1: Self = Self::System(0b11_000_0001_0010_000);
+ /// Trace Filter Control Register (EL1)
+ pub const TRFCR_EL1: Self = Self::System(0b11_000_0001_0010_001);
+ /// Streaming Mode Priority Register
+ pub const SMPRI_EL1: Self = Self::System(0b11_000_0001_0010_100);
+ /// SME Control Register (EL1)
+ pub const SMCR_EL1: Self = Self::System(0b11_000_0001_0010_110);
+ /// Translation Table Base Register 0 (EL1)
+ pub const TTBR0_EL1: Self = Self::System(0b11_000_0010_0000_000);
+ /// Translation Table Base Register 1 (EL1)
+ pub const TTBR1_EL1: Self = Self::System(0b11_000_0010_0000_001);
+ /// Translation Control Register (EL1)
+ pub const TCR_EL1: Self = Self::System(0b11_000_0010_0000_010);
+ /// Pointer Authentication Key A For Instruction (bits[63:0])
+ pub const APIAKEYLO_EL1: Self = Self::System(0b11_000_0010_0001_000);
+ /// Pointer Authentication Key A For Instruction (bits[127:64])
+ pub const APIAKEYHI_EL1: Self = Self::System(0b11_000_0010_0001_001);
+ /// Pointer Authentication Key B For Instruction (bits[63:0])
+ pub const APIBKEYLO_EL1: Self = Self::System(0b11_000_0010_0001_010);
+ /// Pointer Authentication Key B For Instruction (bits[127:64])
+ pub const APIBKEYHI_EL1: Self = Self::System(0b11_000_0010_0001_011);
+ /// Pointer Authentication Key A For Data (bits[63:0])
+ pub const APDAKEYLO_EL1: Self = Self::System(0b11_000_0010_0010_000);
+ /// Pointer Authentication Key A For Data (bits[127:64])
+ pub const APDAKEYHI_EL1: Self = Self::System(0b11_000_0010_0010_001);
+ /// Pointer Authentication Key B For Data (bits[63:0])
+ pub const APDBKEYLO_EL1: Self = Self::System(0b11_000_0010_0010_010);
+ /// Pointer Authentication Key B For Data (bits[127:64])
+ pub const APDBKEYHI_EL1: Self = Self::System(0b11_000_0010_0010_011);
+ /// Pointer Authentication Key A For Code (bits[63:0])
+ pub const APGAKEYLO_EL1: Self = Self::System(0b11_000_0010_0011_000);
+ /// Pointer Authentication Key A For Code (bits[127:64])
+ pub const APGAKEYHI_EL1: Self = Self::System(0b11_000_0010_0011_001);
+ /// Saved Program Status Register (EL1)
+ pub const SPSR_EL1: Self = Self::System(0b11_000_0100_0000_000);
+ /// Exception Link Register (EL1)
+ pub const ELR_EL1: Self = Self::System(0b11_000_0100_0000_001);
+ /// Stack Pointer (EL0)
+ pub const SP_EL0: Self = Self::System(0b11_000_0100_0001_000);
+ /// Interrupt Controller Interrupt Priority Mask Register
+ pub const ICC_PMR_EL1: Self = Self::System(0b11_000_0100_0110_000);
+ /// Interrupt Controller Virtual Interrupt Priority Mask Register
+ pub const ICV_PMR_EL1: Self = Self::System(0b11_000_0100_0110_000);
+ /// Auxiliary Fault Status Register 0 (EL1)
+ pub const AFSR0_EL1: Self = Self::System(0b11_000_0101_0001_000);
+ /// Auxiliary Fault Status Register 1 (EL1)
+ pub const AFSR1_EL1: Self = Self::System(0b11_000_0101_0001_001);
+ /// Exception Syndrome Register (EL1)
+ pub const ESR_EL1: Self = Self::System(0b11_000_0101_0010_000);
+ /// Error Record ID Register
+ pub const ERRIDR_EL1: Self = Self::System(0b11_000_0101_0011_000);
+ /// Error Record Select Register
+ pub const ERRSELR_EL1: Self = Self::System(0b11_000_0101_0011_001);
+ /// Selected Error Record Feature Register
+ pub const ERXFR_EL1: Self = Self::System(0b11_000_0101_0100_000);
+ /// Selected Error Record Control Register
+ pub const ERXCTLR_EL1: Self = Self::System(0b11_000_0101_0100_001);
+ /// Selected Error Record Primary Status Register
+ pub const ERXSTATUS_EL1: Self = Self::System(0b11_000_0101_0100_010);
+ /// Selected Error Record Address Register
+ pub const ERXADDR_EL1: Self = Self::System(0b11_000_0101_0100_011);
+ /// Selected Pseudo-fault Generation Feature Register
+ pub const ERXPFGF_EL1: Self = Self::System(0b11_000_0101_0100_100);
+ /// Selected Pseudo-fault Generation Control Register
+ pub const ERXPFGCTL_EL1: Self = Self::System(0b11_000_0101_0100_101);
+ /// Selected Pseudo-fault Generation Countdown Register
+ pub const ERXPFGCDN_EL1: Self = Self::System(0b11_000_0101_0100_110);
+ /// Selected Error Record Miscellaneous Register 0
+ pub const ERXMISC0_EL1: Self = Self::System(0b11_000_0101_0101_000);
+ /// Selected Error Record Miscellaneous Register 1
+ pub const ERXMISC1_EL1: Self = Self::System(0b11_000_0101_0101_001);
+ /// Selected Error Record Miscellaneous Register 2
+ pub const ERXMISC2_EL1: Self = Self::System(0b11_000_0101_0101_010);
+ /// Selected Error Record Miscellaneous Register 3
+ pub const ERXMISC3_EL1: Self = Self::System(0b11_000_0101_0101_011);
+ /// Tag Fault Status Register (EL1)
+ pub const TFSR_EL1: Self = Self::System(0b11_000_0101_0110_000);
+ /// Tag Fault Status Register (EL0)
+ pub const TFSRE0_EL1: Self = Self::System(0b11_000_0101_0110_001);
+ /// Fault Address Register (EL1)
+ pub const FAR_EL1: Self = Self::System(0b11_000_0110_0000_000);
+ /// Physical Address Register
+ pub const PAR_EL1: Self = Self::System(0b11_000_0111_0100_000);
+ /// Statistical Profiling Control Register (EL1)
+ pub const PMSCR_EL1: Self = Self::System(0b11_000_1001_1001_000);
+ /// Sampling Inverted Event Filter Register
+ pub const PMSNEVFR_EL1: Self = Self::System(0b11_000_1001_1001_001);
+ /// Sampling Interval Counter Register
+ pub const PMSICR_EL1: Self = Self::System(0b11_000_1001_1001_010);
+ /// Sampling Interval Reload Register
+ pub const PMSIRR_EL1: Self = Self::System(0b11_000_1001_1001_011);
+ /// Sampling Filter Control Register
+ pub const PMSFCR_EL1: Self = Self::System(0b11_000_1001_1001_100);
+ /// Sampling Event Filter Register
+ pub const PMSEVFR_EL1: Self = Self::System(0b11_000_1001_1001_101);
+ /// Sampling Latency Filter Register
+ pub const PMSLATFR_EL1: Self = Self::System(0b11_000_1001_1001_110);
+ /// Sampling Profiling ID Register
+ pub const PMSIDR_EL1: Self = Self::System(0b11_000_1001_1001_111);
+ /// Profiling Buffer Limit Address Register
+ pub const PMBLIMITR_EL1: Self = Self::System(0b11_000_1001_1010_000);
+ /// Profiling Buffer Write Pointer Register
+ pub const PMBPTR_EL1: Self = Self::System(0b11_000_1001_1010_001);
+ /// Profiling Buffer Status/syndrome Register
+ pub const PMBSR_EL1: Self = Self::System(0b11_000_1001_1010_011);
+ /// Profiling Buffer ID Register
+ pub const PMBIDR_EL1: Self = Self::System(0b11_000_1001_1010_111);
+ /// Trace Buffer Limit Address Register
+ pub const TRBLIMITR_EL1: Self = Self::System(0b11_000_1001_1011_000);
+ /// Trace Buffer Write Pointer Register
+ pub const TRBPTR_EL1: Self = Self::System(0b11_000_1001_1011_001);
+ /// Trace Buffer Base Address Register
+ pub const TRBBASER_EL1: Self = Self::System(0b11_000_1001_1011_010);
+ /// Trace Buffer Status/syndrome Register
+ pub const TRBSR_EL1: Self = Self::System(0b11_000_1001_1011_011);
+ /// Trace Buffer Memory Attribute Register
+ pub const TRBMAR_EL1: Self = Self::System(0b11_000_1001_1011_100);
+ /// Trace Buffer Trigger Counter Register
+ pub const TRBTRG_EL1: Self = Self::System(0b11_000_1001_1011_110);
+ /// Trace Buffer ID Register
+ pub const TRBIDR_EL1: Self = Self::System(0b11_000_1001_1011_111);
+ /// Performance Monitors Interrupt Enable Set Register
+ pub const PMINTENSET_EL1: Self = Self::System(0b11_000_1001_1110_001);
+ /// Performance Monitors Interrupt Enable Clear Register
+ pub const PMINTENCLR_EL1: Self = Self::System(0b11_000_1001_1110_010);
+ /// Performance Monitors Machine Identification Register
+ pub const PMMIR_EL1: Self = Self::System(0b11_000_1001_1110_110);
+ /// Memory Attribute Indirection Register (EL1)
+ pub const MAIR_EL1: Self = Self::System(0b11_000_1010_0010_000);
+ /// Auxiliary Memory Attribute Indirection Register (EL1)
+ pub const AMAIR_EL1: Self = Self::System(0b11_000_1010_0011_000);
+ /// LORegion Start Address (EL1)
+ pub const LORSA_EL1: Self = Self::System(0b11_000_1010_0100_000);
+ /// LORegion End Address (EL1)
+ pub const LOREA_EL1: Self = Self::System(0b11_000_1010_0100_001);
+ /// LORegion Number (EL1)
+ pub const LORN_EL1: Self = Self::System(0b11_000_1010_0100_010);
+ /// LORegion Control (EL1)
+ pub const LORC_EL1: Self = Self::System(0b11_000_1010_0100_011);
+ /// MPAM ID Register (EL1)
+ pub const MPAMIDR_EL1: Self = Self::System(0b11_000_1010_0100_100);
+ /// LORegionID (EL1)
+ pub const LORID_EL1: Self = Self::System(0b11_000_1010_0100_111);
+ /// MPAM1 Register (EL1)
+ pub const MPAM1_EL1: Self = Self::System(0b11_000_1010_0101_000);
+ /// MPAM0 Register (EL1)
+ pub const MPAM0_EL1: Self = Self::System(0b11_000_1010_0101_001);
+ /// MPAM Streaming Mode Register
+ pub const MPAMSM_EL1: Self = Self::System(0b11_000_1010_0101_011);
+ /// Vector Base Address Register (EL1)
+ pub const VBAR_EL1: Self = Self::System(0b11_000_1100_0000_000);
+ /// Reset Vector Base Address Register (if EL2 And EL3 Not Implemented)
+ pub const RVBAR_EL1: Self = Self::System(0b11_000_1100_0000_001);
+ /// Reset Management Register (EL1)
+ pub const RMR_EL1: Self = Self::System(0b11_000_1100_0000_010);
+ /// Interrupt Status Register
+ pub const ISR_EL1: Self = Self::System(0b11_000_1100_0001_000);
+ /// Deferred Interrupt Status Register
+ pub const DISR_EL1: Self = Self::System(0b11_000_1100_0001_001);
+ /// Interrupt Controller Interrupt Acknowledge Register 0
+ pub const ICC_IAR0_EL1: Self = Self::System(0b11_000_1100_1000_000);
+ /// Interrupt Controller Virtual Interrupt Acknowledge Register 0
+ pub const ICV_IAR0_EL1: Self = Self::System(0b11_000_1100_1000_000);
+ /// Interrupt Controller End Of Interrupt Register 0
+ pub const ICC_EOIR0_EL1: Self = Self::System(0b11_000_1100_1000_001);
+ /// Interrupt Controller Virtual End Of Interrupt Register 0
+ pub const ICV_EOIR0_EL1: Self = Self::System(0b11_000_1100_1000_001);
+ /// Interrupt Controller Highest Priority Pending Interrupt Register 0
+ pub const ICC_HPPIR0_EL1: Self = Self::System(0b11_000_1100_1000_010);
+ /// Interrupt Controller Virtual Highest Priority Pending Interrupt Register
+ /// 0
+ pub const ICV_HPPIR0_EL1: Self = Self::System(0b11_000_1100_1000_010);
+ /// Interrupt Controller Binary Point Register 0
+ pub const ICC_BPR0_EL1: Self = Self::System(0b11_000_1100_1000_011);
+ /// Interrupt Controller Virtual Binary Point Register 0
+ pub const ICV_BPR0_EL1: Self = Self::System(0b11_000_1100_1000_011);
+ /// Interrupt Controller Active Priorities Group 0 Registers - 0
+ pub const ICC_AP0R0_EL1: Self = Self::System(0b11_000_1100_1000_100);
+ /// Interrupt Controller Virtual Active Priorities Group 0 Registers - 0
+ pub const ICV_AP0R0_EL1: Self = Self::System(0b11_000_1100_1000_100);
+ /// Interrupt Controller Active Priorities Group 0 Registers - 1
+ pub const ICC_AP0R1_EL1: Self = Self::System(0b11_000_1100_1000_101);
+ /// Interrupt Controller Virtual Active Priorities Group 0 Registers - 1
+ pub const ICV_AP0R1_EL1: Self = Self::System(0b11_000_1100_1000_101);
+ /// Interrupt Controller Active Priorities Group 0 Registers - 2
+ pub const ICC_AP0R2_EL1: Self = Self::System(0b11_000_1100_1000_110);
+ /// Interrupt Controller Virtual Active Priorities Group 0 Registers - 2
+ pub const ICV_AP0R2_EL1: Self = Self::System(0b11_000_1100_1000_110);
+ /// Interrupt Controller Active Priorities Group 0 Registers - 3
+ pub const ICC_AP0R3_EL1: Self = Self::System(0b11_000_1100_1000_111);
+ /// Interrupt Controller Virtual Active Priorities Group 0 Registers - 3
+ pub const ICV_AP0R3_EL1: Self = Self::System(0b11_000_1100_1000_111);
+ /// Interrupt Controller Active Priorities Group 1 Registers - 0
+ pub const ICC_AP1R0_EL1: Self = Self::System(0b11_000_1100_1001_000);
+ /// Interrupt Controller Virtual Active Priorities Group 1 Registers - 0
+ pub const ICV_AP1R0_EL1: Self = Self::System(0b11_000_1100_1001_000);
+ /// Interrupt Controller Active Priorities Group 1 Registers - 1
+ pub const ICC_AP1R1_EL1: Self = Self::System(0b11_000_1100_1001_001);
+ /// Interrupt Controller Virtual Active Priorities Group 1 Registers - 1
+ pub const ICV_AP1R1_EL1: Self = Self::System(0b11_000_1100_1001_001);
+ /// Interrupt Controller Active Priorities Group 1 Registers - 2
+ pub const ICC_AP1R2_EL1: Self = Self::System(0b11_000_1100_1001_010);
+ /// Interrupt Controller Virtual Active Priorities Group 1 Registers - 2
+ pub const ICV_AP1R2_EL1: Self = Self::System(0b11_000_1100_1001_010);
+ /// Interrupt Controller Active Priorities Group 1 Registers - 3
+ pub const ICC_AP1R3_EL1: Self = Self::System(0b11_000_1100_1001_011);
+ /// Interrupt Controller Virtual Active Priorities Group 1 Registers - 3
+ pub const ICV_AP1R3_EL1: Self = Self::System(0b11_000_1100_1001_011);
+ /// Interrupt Controller Non-maskable Interrupt Acknowledge Register 1
+ pub const ICC_NMIAR1_EL1: Self = Self::System(0b11_000_1100_1001_101);
+ /// Interrupt Controller Virtual Non-maskable Interrupt Acknowledge Register
+ /// 1
+ pub const ICV_NMIAR1_EL1: Self = Self::System(0b11_000_1100_1001_101);
+ /// Interrupt Controller Deactivate Interrupt Register
+ pub const ICC_DIR_EL1: Self = Self::System(0b11_000_1100_1011_001);
+ /// Interrupt Controller Deactivate Virtual Interrupt Register
+ pub const ICV_DIR_EL1: Self = Self::System(0b11_000_1100_1011_001);
+ /// Interrupt Controller Running Priority Register
+ pub const ICC_RPR_EL1: Self = Self::System(0b11_000_1100_1011_011);
+ /// Interrupt Controller Virtual Running Priority Register
+ pub const ICV_RPR_EL1: Self = Self::System(0b11_000_1100_1011_011);
+ /// Interrupt Controller Software Generated Interrupt Group 1 Register
+ pub const ICC_SGI1R_EL1: Self = Self::System(0b11_000_1100_1011_101);
+ /// Interrupt Controller Alias Software Generated Interrupt Group 1 Register
+ pub const ICC_ASGI1R_EL1: Self = Self::System(0b11_000_1100_1011_110);
+ /// Interrupt Controller Software Generated Interrupt Group 0 Register
+ pub const ICC_SGI0R_EL1: Self = Self::System(0b11_000_1100_1011_111);
+ /// Interrupt Controller Interrupt Acknowledge Register 1
+ pub const ICC_IAR1_EL1: Self = Self::System(0b11_000_1100_1100_000);
+ /// Interrupt Controller Virtual Interrupt Acknowledge Register 1
+ pub const ICV_IAR1_EL1: Self = Self::System(0b11_000_1100_1100_000);
+ /// Interrupt Controller End Of Interrupt Register 1
+ pub const ICC_EOIR1_EL1: Self = Self::System(0b11_000_1100_1100_001);
+ /// Interrupt Controller Virtual End Of Interrupt Register 1
+ pub const ICV_EOIR1_EL1: Self = Self::System(0b11_000_1100_1100_001);
+ /// Interrupt Controller Highest Priority Pending Interrupt Register 1
+ pub const ICC_HPPIR1_EL1: Self = Self::System(0b11_000_1100_1100_010);
+ /// Interrupt Controller Virtual Highest Priority Pending Interrupt Register
+ /// 1
+ pub const ICV_HPPIR1_EL1: Self = Self::System(0b11_000_1100_1100_010);
+ /// Interrupt Controller Binary Point Register 1
+ pub const ICC_BPR1_EL1: Self = Self::System(0b11_000_1100_1100_011);
+ /// Interrupt Controller Virtual Binary Point Register 1
+ pub const ICV_BPR1_EL1: Self = Self::System(0b11_000_1100_1100_011);
+ /// Interrupt Controller Control Register (EL1)
+ pub const ICC_CTLR_EL1: Self = Self::System(0b11_000_1100_1100_100);
+ /// Interrupt Controller Virtual Control Register
+ pub const ICV_CTLR_EL1: Self = Self::System(0b11_000_1100_1100_100);
+ /// Interrupt Controller System Register Enable Register (EL1)
+ pub const ICC_SRE_EL1: Self = Self::System(0b11_000_1100_1100_101);
+ /// Interrupt Controller Interrupt Group 0 Enable Register
+ pub const ICC_IGRPEN0_EL1: Self = Self::System(0b11_000_1100_1100_110);
+ /// Interrupt Controller Virtual Interrupt Group 0 Enable Register
+ pub const ICV_IGRPEN0_EL1: Self = Self::System(0b11_000_1100_1100_110);
+ /// Interrupt Controller Interrupt Group 1 Enable Register
+ pub const ICC_IGRPEN1_EL1: Self = Self::System(0b11_000_1100_1100_111);
+ /// Interrupt Controller Virtual Interrupt Group 1 Enable Register
+ pub const ICV_IGRPEN1_EL1: Self = Self::System(0b11_000_1100_1100_111);
+ /// Context ID Register (EL1)
+ pub const CONTEXTIDR_EL1: Self = Self::System(0b11_000_1101_0000_001);
+ /// EL1 Software Thread ID Register
+ pub const TPIDR_EL1: Self = Self::System(0b11_000_1101_0000_100);
+ /// Accelerator Data
+ pub const ACCDATA_EL1: Self = Self::System(0b11_000_1101_0000_101);
+ /// EL1 Read/Write Software Context Number
+ pub const SCXTNUM_EL1: Self = Self::System(0b11_000_1101_0000_111);
+ /// Counter-timer Kernel Control Register
+ pub const CNTKCTL_EL1: Self = Self::System(0b11_000_1110_0001_000);
+ /// Current Cache Size ID Register
+ pub const CCSIDR_EL1: Self = Self::System(0b11_001_0000_0000_000);
+ /// Cache Level ID Register
+ pub const CLIDR_EL1: Self = Self::System(0b11_001_0000_0000_001);
+ /// Current Cache Size ID Register 2
+ pub const CCSIDR2_EL1: Self = Self::System(0b11_001_0000_0000_010);
+ /// Multiple Tag Transfer ID Register
+ pub const GMID_EL1: Self = Self::System(0b11_001_0000_0000_100);
+ /// Streaming Mode Identification Register
+ pub const SMIDR_EL1: Self = Self::System(0b11_001_0000_0000_110);
+ /// Auxiliary ID Register
+ pub const AIDR_EL1: Self = Self::System(0b11_001_0000_0000_111);
+ /// Cache Size Selection Register
+ pub const CSSELR_EL1: Self = Self::System(0b11_010_0000_0000_000);
+ /// Cache Type Register
+ pub const CTR_EL0: Self = Self::System(0b11_011_0000_0000_001);
+ /// Data Cache Zero ID Register
+ pub const DCZID_EL0: Self = Self::System(0b11_011_0000_0000_111);
+ /// Random Number
+ pub const RNDR: Self = Self::System(0b11_011_0010_0100_000);
+ /// Reseeded Random Number
+ pub const RNDRRS: Self = Self::System(0b11_011_0010_0100_001);
+ /// Streaming Vector Control Register
+ pub const SVCR: Self = Self::System(0b11_011_0100_0010_010);
+ /// Floating-point Control Register
+ pub const FPCR: Self = Self::System(0b11_011_0100_0100_000);
+ /// Floating-point Status Register
+ pub const FPSR: Self = Self::System(0b11_011_0100_0100_001);
+ /// Debug Saved Program Status Register
+ pub const DSPSR_EL0: Self = Self::System(0b11_011_0100_0101_000);
+ /// Debug Link Register
+ pub const DLR_EL0: Self = Self::System(0b11_011_0100_0101_001);
+ /// Performance Monitors Control Register
+ pub const PMCR_EL0: Self = Self::System(0b11_011_1001_1100_000);
+ /// Performance Monitors Count Enable Set Register
+ pub const PMCNTENSET_EL0: Self = Self::System(0b11_011_1001_1100_001);
+ /// Performance Monitors Count Enable Clear Register
+ pub const PMCNTENCLR_EL0: Self = Self::System(0b11_011_1001_1100_010);
+ /// Performance Monitors Overflow Flag Status Clear Register
+ pub const PMOVSCLR_EL0: Self = Self::System(0b11_011_1001_1100_011);
+ /// Performance Monitors Software Increment Register
+ pub const PMSWINC_EL0: Self = Self::System(0b11_011_1001_1100_100);
+ /// Performance Monitors Event Counter Selection Register
+ pub const PMSELR_EL0: Self = Self::System(0b11_011_1001_1100_101);
+ /// Performance Monitors Common Event Identification Register 0
+ pub const PMCEID0_EL0: Self = Self::System(0b11_011_1001_1100_110);
+ /// Performance Monitors Common Event Identification Register 1
+ pub const PMCEID1_EL0: Self = Self::System(0b11_011_1001_1100_111);
+ /// Performance Monitors Cycle Count Register
+ pub const PMCCNTR_EL0: Self = Self::System(0b11_011_1001_1101_000);
+ /// Performance Monitors Selected Event Type Register
+ pub const PMXEVTYPER_EL0: Self = Self::System(0b11_011_1001_1101_001);
+ /// Performance Monitors Selected Event Count Register
+ pub const PMXEVCNTR_EL0: Self = Self::System(0b11_011_1001_1101_010);
+ /// Performance Monitors User Enable Register
+ pub const PMUSERENR_EL0: Self = Self::System(0b11_011_1001_1110_000);
+ /// Performance Monitors Overflow Flag Status Set Register
+ pub const PMOVSSET_EL0: Self = Self::System(0b11_011_1001_1110_011);
+ /// EL0 Read/Write Software Thread ID Register
+ pub const TPIDR_EL0: Self = Self::System(0b11_011_1101_0000_010);
+ /// EL0 Read-Only Software Thread ID Register
+ pub const TPIDRRO_EL0: Self = Self::System(0b11_011_1101_0000_011);
+ /// EL0 Read/Write Software Thread ID Register 2
+ pub const TPIDR2_EL0: Self = Self::System(0b11_011_1101_0000_101);
+ /// EL0 Read/Write Software Context Number
+ pub const SCXTNUM_EL0: Self = Self::System(0b11_011_1101_0000_111);
+ /// Activity Monitors Control Register
+ pub const AMCR_EL0: Self = Self::System(0b11_011_1101_0010_000);
+ /// Activity Monitors Configuration Register
+ pub const AMCFGR_EL0: Self = Self::System(0b11_011_1101_0010_001);
+ /// Activity Monitors Counter Group Configuration Register
+ pub const AMCGCR_EL0: Self = Self::System(0b11_011_1101_0010_010);
+ /// Activity Monitors User Enable Register
+ pub const AMUSERENR_EL0: Self = Self::System(0b11_011_1101_0010_011);
+ /// Activity Monitors Count Enable Clear Register 0
+ pub const AMCNTENCLR0_EL0: Self = Self::System(0b11_011_1101_0010_100);
+ /// Activity Monitors Count Enable Set Register 0
+ pub const AMCNTENSET0_EL0: Self = Self::System(0b11_011_1101_0010_101);
+ /// Activity Monitors Counter Group 1 Identification Register
+ pub const AMCG1IDR_EL0: Self = Self::System(0b11_011_1101_0010_110);
+ /// Activity Monitors Count Enable Clear Register 1
+ pub const AMCNTENCLR1_EL0: Self = Self::System(0b11_011_1101_0011_000);
+ /// Activity Monitors Count Enable Set Register 1
+ pub const AMCNTENSET1_EL0: Self = Self::System(0b11_011_1101_0011_001);
+ /// Activity Monitors Event Counter Registers 0 - 0
+ pub const AMEVCNTR00_EL0: Self = Self::System(0b11_011_1101_0100_000);
+ /// Activity Monitors Event Counter Registers 0 - 1
+ pub const AMEVCNTR01_EL0: Self = Self::System(0b11_011_1101_0100_001);
+ /// Activity Monitors Event Counter Registers 0 - 2
+ pub const AMEVCNTR02_EL0: Self = Self::System(0b11_011_1101_0100_010);
+ /// Activity Monitors Event Counter Registers 0 - 3
+ pub const AMEVCNTR03_EL0: Self = Self::System(0b11_011_1101_0100_011);
+ /// Activity Monitors Event Type Registers 0 - 0
+ pub const AMEVTYPER00_EL0: Self = Self::System(0b11_011_1101_0110_000);
+ /// Activity Monitors Event Type Registers 0 - 1
+ pub const AMEVTYPER01_EL0: Self = Self::System(0b11_011_1101_0110_001);
+ /// Activity Monitors Event Type Registers 0 - 2
+ pub const AMEVTYPER02_EL0: Self = Self::System(0b11_011_1101_0110_010);
+ /// Activity Monitors Event Type Registers 0 - 3
+ pub const AMEVTYPER03_EL0: Self = Self::System(0b11_011_1101_0110_011);
+ /// Activity Monitors Event Counter Registers 1 - 0
+ pub const AMEVCNTR10_EL0: Self = Self::System(0b11_011_1101_1100_000);
+ /// Activity Monitors Event Counter Registers 1 - 1
+ pub const AMEVCNTR11_EL0: Self = Self::System(0b11_011_1101_1100_001);
+ /// Activity Monitors Event Counter Registers 1 - 2
+ pub const AMEVCNTR12_EL0: Self = Self::System(0b11_011_1101_1100_010);
+ /// Activity Monitors Event Counter Registers 1 - 3
+ pub const AMEVCNTR13_EL0: Self = Self::System(0b11_011_1101_1100_011);
+ /// Activity Monitors Event Counter Registers 1 - 4
+ pub const AMEVCNTR14_EL0: Self = Self::System(0b11_011_1101_1100_100);
+ /// Activity Monitors Event Counter Registers 1 - 5
+ pub const AMEVCNTR15_EL0: Self = Self::System(0b11_011_1101_1100_101);
+ /// Activity Monitors Event Counter Registers 1 - 6
+ pub const AMEVCNTR16_EL0: Self = Self::System(0b11_011_1101_1100_110);
+ /// Activity Monitors Event Counter Registers 1 - 7
+ pub const AMEVCNTR17_EL0: Self = Self::System(0b11_011_1101_1100_111);
+ /// Activity Monitors Event Counter Registers 1 - 8
+ pub const AMEVCNTR18_EL0: Self = Self::System(0b11_011_1101_1101_000);
+ /// Activity Monitors Event Counter Registers 1 - 9
+ pub const AMEVCNTR19_EL0: Self = Self::System(0b11_011_1101_1101_001);
+ /// Activity Monitors Event Counter Registers 1 - 10
+ pub const AMEVCNTR110_EL0: Self = Self::System(0b11_011_1101_1101_010);
+ /// Activity Monitors Event Counter Registers 1 - 11
+ pub const AMEVCNTR111_EL0: Self = Self::System(0b11_011_1101_1101_011);
+ /// Activity Monitors Event Counter Registers 1 - 12
+ pub const AMEVCNTR112_EL0: Self = Self::System(0b11_011_1101_1101_100);
+ /// Activity Monitors Event Counter Registers 1 - 13
+ pub const AMEVCNTR113_EL0: Self = Self::System(0b11_011_1101_1101_101);
+ /// Activity Monitors Event Counter Registers 1 - 14
+ pub const AMEVCNTR114_EL0: Self = Self::System(0b11_011_1101_1101_110);
+ /// Activity Monitors Event Counter Registers 1 - 15
+ pub const AMEVCNTR115_EL0: Self = Self::System(0b11_011_1101_1101_111);
+ /// Activity Monitors Event Type Registers 1 - 0
+ pub const AMEVTYPER10_EL0: Self = Self::System(0b11_011_1101_1110_000);
+ /// Activity Monitors Event Type Registers 1 - 1
+ pub const AMEVTYPER11_EL0: Self = Self::System(0b11_011_1101_1110_001);
+ /// Activity Monitors Event Type Registers 1 - 2
+ pub const AMEVTYPER12_EL0: Self = Self::System(0b11_011_1101_1110_010);
+ /// Activity Monitors Event Type Registers 1 - 3
+ pub const AMEVTYPER13_EL0: Self = Self::System(0b11_011_1101_1110_011);
+ /// Activity Monitors Event Type Registers 1 - 4
+ pub const AMEVTYPER14_EL0: Self = Self::System(0b11_011_1101_1110_100);
+ /// Activity Monitors Event Type Registers 1 - 5
+ pub const AMEVTYPER15_EL0: Self = Self::System(0b11_011_1101_1110_101);
+ /// Activity Monitors Event Type Registers 1 - 6
+ pub const AMEVTYPER16_EL0: Self = Self::System(0b11_011_1101_1110_110);
+ /// Activity Monitors Event Type Registers 1 - 7
+ pub const AMEVTYPER17_EL0: Self = Self::System(0b11_011_1101_1110_111);
+ /// Activity Monitors Event Type Registers 1 - 8
+ pub const AMEVTYPER18_EL0: Self = Self::System(0b11_011_1101_1111_000);
+ /// Activity Monitors Event Type Registers 1 - 9
+ pub const AMEVTYPER19_EL0: Self = Self::System(0b11_011_1101_1111_001);
+ /// Activity Monitors Event Type Registers 1 - 10
+ pub const AMEVTYPER110_EL0: Self = Self::System(0b11_011_1101_1111_010);
+ /// Activity Monitors Event Type Registers 1 - 11
+ pub const AMEVTYPER111_EL0: Self = Self::System(0b11_011_1101_1111_011);
+ /// Activity Monitors Event Type Registers 1 - 12
+ pub const AMEVTYPER112_EL0: Self = Self::System(0b11_011_1101_1111_100);
+ /// Activity Monitors Event Type Registers 1 - 13
+ pub const AMEVTYPER113_EL0: Self = Self::System(0b11_011_1101_1111_101);
+ /// Activity Monitors Event Type Registers 1 - 14
+ pub const AMEVTYPER114_EL0: Self = Self::System(0b11_011_1101_1111_110);
+ /// Activity Monitors Event Type Registers 1 - 15
+ pub const AMEVTYPER115_EL0: Self = Self::System(0b11_011_1101_1111_111);
+ /// Counter-timer Frequency Register
+ pub const CNTFRQ_EL0: Self = Self::System(0b11_011_1110_0000_000);
+ /// Counter-timer Physical Count Register
+ pub const CNTPCT_EL0: Self = Self::System(0b11_011_1110_0000_001);
+ /// Counter-timer Virtual Count Register
+ pub const CNTVCT_EL0: Self = Self::System(0b11_011_1110_0000_010);
+ /// Counter-timer Self-Synchronized Physical Count Register
+ pub const CNTPCTSS_EL0: Self = Self::System(0b11_011_1110_0000_101);
+ /// Counter-timer Self-Synchronized Virtual Count Register
+ pub const CNTVCTSS_EL0: Self = Self::System(0b11_011_1110_0000_110);
+ /// Counter-timer Physical Timer TimerValue Register
+ pub const CNTP_TVAL_EL0: Self = Self::System(0b11_011_1110_0010_000);
+ /// Counter-timer Physical Timer Control Register
+ pub const CNTP_CTL_EL0: Self = Self::System(0b11_011_1110_0010_001);
+ /// Counter-timer Physical Timer CompareValue Register
+ pub const CNTP_CVAL_EL0: Self = Self::System(0b11_011_1110_0010_010);
+ /// Counter-timer Virtual Timer TimerValue Register
+ pub const CNTV_TVAL_EL0: Self = Self::System(0b11_011_1110_0011_000);
+ /// Counter-timer Virtual Timer Control Register
+ pub const CNTV_CTL_EL0: Self = Self::System(0b11_011_1110_0011_001);
+ /// Counter-timer Virtual Timer CompareValue Register
+ pub const CNTV_CVAL_EL0: Self = Self::System(0b11_011_1110_0011_010);
+ /// Performance Monitors Event Count Registers - 0
+ pub const PMEVCNTR0_EL0: Self = Self::System(0b11_011_1110_1000_000);
+ /// Performance Monitors Event Count Registers - 1
+ pub const PMEVCNTR1_EL0: Self = Self::System(0b11_011_1110_1000_001);
+ /// Performance Monitors Event Count Registers - 2
+ pub const PMEVCNTR2_EL0: Self = Self::System(0b11_011_1110_1000_010);
+ /// Performance Monitors Event Count Registers - 3
+ pub const PMEVCNTR3_EL0: Self = Self::System(0b11_011_1110_1000_011);
+ /// Performance Monitors Event Count Registers - 4
+ pub const PMEVCNTR4_EL0: Self = Self::System(0b11_011_1110_1000_100);
+ /// Performance Monitors Event Count Registers - 5
+ pub const PMEVCNTR5_EL0: Self = Self::System(0b11_011_1110_1000_101);
+ /// Performance Monitors Event Count Registers - 6
+ pub const PMEVCNTR6_EL0: Self = Self::System(0b11_011_1110_1000_110);
+ /// Performance Monitors Event Count Registers - 7
+ pub const PMEVCNTR7_EL0: Self = Self::System(0b11_011_1110_1000_111);
+ /// Performance Monitors Event Count Registers - 8
+ pub const PMEVCNTR8_EL0: Self = Self::System(0b11_011_1110_1001_000);
+ /// Performance Monitors Event Count Registers - 9
+ pub const PMEVCNTR9_EL0: Self = Self::System(0b11_011_1110_1001_001);
+ /// Performance Monitors Event Count Registers - 10
+ pub const PMEVCNTR10_EL0: Self = Self::System(0b11_011_1110_1001_010);
+ /// Performance Monitors Event Count Registers - 11
+ pub const PMEVCNTR11_EL0: Self = Self::System(0b11_011_1110_1001_011);
+ /// Performance Monitors Event Count Registers - 12
+ pub const PMEVCNTR12_EL0: Self = Self::System(0b11_011_1110_1001_100);
+ /// Performance Monitors Event Count Registers - 13
+ pub const PMEVCNTR13_EL0: Self = Self::System(0b11_011_1110_1001_101);
+ /// Performance Monitors Event Count Registers - 14
+ pub const PMEVCNTR14_EL0: Self = Self::System(0b11_011_1110_1001_110);
+ /// Performance Monitors Event Count Registers - 15
+ pub const PMEVCNTR15_EL0: Self = Self::System(0b11_011_1110_1001_111);
+ /// Performance Monitors Event Count Registers - 16
+ pub const PMEVCNTR16_EL0: Self = Self::System(0b11_011_1110_1010_000);
+ /// Performance Monitors Event Count Registers - 17
+ pub const PMEVCNTR17_EL0: Self = Self::System(0b11_011_1110_1010_001);
+ /// Performance Monitors Event Count Registers - 18
+ pub const PMEVCNTR18_EL0: Self = Self::System(0b11_011_1110_1010_010);
+ /// Performance Monitors Event Count Registers - 19
+ pub const PMEVCNTR19_EL0: Self = Self::System(0b11_011_1110_1010_011);
+ /// Performance Monitors Event Count Registers - 20
+ pub const PMEVCNTR20_EL0: Self = Self::System(0b11_011_1110_1010_100);
+ /// Performance Monitors Event Count Registers - 21
+ pub const PMEVCNTR21_EL0: Self = Self::System(0b11_011_1110_1010_101);
+ /// Performance Monitors Event Count Registers - 22
+ pub const PMEVCNTR22_EL0: Self = Self::System(0b11_011_1110_1010_110);
+ /// Performance Monitors Event Count Registers - 23
+ pub const PMEVCNTR23_EL0: Self = Self::System(0b11_011_1110_1010_111);
+ /// Performance Monitors Event Count Registers - 24
+ pub const PMEVCNTR24_EL0: Self = Self::System(0b11_011_1110_1011_000);
+ /// Performance Monitors Event Count Registers - 25
+ pub const PMEVCNTR25_EL0: Self = Self::System(0b11_011_1110_1011_001);
+ /// Performance Monitors Event Count Registers - 26
+ pub const PMEVCNTR26_EL0: Self = Self::System(0b11_011_1110_1011_010);
+ /// Performance Monitors Event Count Registers - 27
+ pub const PMEVCNTR27_EL0: Self = Self::System(0b11_011_1110_1011_011);
+ /// Performance Monitors Event Count Registers - 28
+ pub const PMEVCNTR28_EL0: Self = Self::System(0b11_011_1110_1011_100);
+ /// Performance Monitors Event Count Registers - 29
+ pub const PMEVCNTR29_EL0: Self = Self::System(0b11_011_1110_1011_101);
+ /// Performance Monitors Event Count Registers - 30
+ pub const PMEVCNTR30_EL0: Self = Self::System(0b11_011_1110_1011_110);
+ /// Performance Monitors Event Type Registers - 0
+ pub const PMEVTYPER0_EL0: Self = Self::System(0b11_011_1110_1100_000);
+ /// Performance Monitors Event Type Registers - 1
+ pub const PMEVTYPER1_EL0: Self = Self::System(0b11_011_1110_1100_001);
+ /// Performance Monitors Event Type Registers - 2
+ pub const PMEVTYPER2_EL0: Self = Self::System(0b11_011_1110_1100_010);
+ /// Performance Monitors Event Type Registers - 3
+ pub const PMEVTYPER3_EL0: Self = Self::System(0b11_011_1110_1100_011);
+ /// Performance Monitors Event Type Registers - 4
+ pub const PMEVTYPER4_EL0: Self = Self::System(0b11_011_1110_1100_100);
+ /// Performance Monitors Event Type Registers - 5
+ pub const PMEVTYPER5_EL0: Self = Self::System(0b11_011_1110_1100_101);
+ /// Performance Monitors Event Type Registers - 6
+ pub const PMEVTYPER6_EL0: Self = Self::System(0b11_011_1110_1100_110);
+ /// Performance Monitors Event Type Registers - 7
+ pub const PMEVTYPER7_EL0: Self = Self::System(0b11_011_1110_1100_111);
+ /// Performance Monitors Event Type Registers - 8
+ pub const PMEVTYPER8_EL0: Self = Self::System(0b11_011_1110_1101_000);
+ /// Performance Monitors Event Type Registers - 9
+ pub const PMEVTYPER9_EL0: Self = Self::System(0b11_011_1110_1101_001);
+ /// Performance Monitors Event Type Registers - 10
+ pub const PMEVTYPER10_EL0: Self = Self::System(0b11_011_1110_1101_010);
+ /// Performance Monitors Event Type Registers - 11
+ pub const PMEVTYPER11_EL0: Self = Self::System(0b11_011_1110_1101_011);
+ /// Performance Monitors Event Type Registers - 12
+ pub const PMEVTYPER12_EL0: Self = Self::System(0b11_011_1110_1101_100);
+ /// Performance Monitors Event Type Registers - 13
+ pub const PMEVTYPER13_EL0: Self = Self::System(0b11_011_1110_1101_101);
+ /// Performance Monitors Event Type Registers - 14
+ pub const PMEVTYPER14_EL0: Self = Self::System(0b11_011_1110_1101_110);
+ /// Performance Monitors Event Type Registers - 15
+ pub const PMEVTYPER15_EL0: Self = Self::System(0b11_011_1110_1101_111);
+ /// Performance Monitors Event Type Registers - 16
+ pub const PMEVTYPER16_EL0: Self = Self::System(0b11_011_1110_1110_000);
+ /// Performance Monitors Event Type Registers - 17
+ pub const PMEVTYPER17_EL0: Self = Self::System(0b11_011_1110_1110_001);
+ /// Performance Monitors Event Type Registers - 18
+ pub const PMEVTYPER18_EL0: Self = Self::System(0b11_011_1110_1110_010);
+ /// Performance Monitors Event Type Registers - 19
+ pub const PMEVTYPER19_EL0: Self = Self::System(0b11_011_1110_1110_011);
+ /// Performance Monitors Event Type Registers - 20
+ pub const PMEVTYPER20_EL0: Self = Self::System(0b11_011_1110_1110_100);
+ /// Performance Monitors Event Type Registers - 21
+ pub const PMEVTYPER21_EL0: Self = Self::System(0b11_011_1110_1110_101);
+ /// Performance Monitors Event Type Registers - 22
+ pub const PMEVTYPER22_EL0: Self = Self::System(0b11_011_1110_1110_110);
+ /// Performance Monitors Event Type Registers - 23
+ pub const PMEVTYPER23_EL0: Self = Self::System(0b11_011_1110_1110_111);
+ /// Performance Monitors Event Type Registers - 24
+ pub const PMEVTYPER24_EL0: Self = Self::System(0b11_011_1110_1111_000);
+ /// Performance Monitors Event Type Registers - 25
+ pub const PMEVTYPER25_EL0: Self = Self::System(0b11_011_1110_1111_001);
+ /// Performance Monitors Event Type Registers - 26
+ pub const PMEVTYPER26_EL0: Self = Self::System(0b11_011_1110_1111_010);
+ /// Performance Monitors Event Type Registers - 27
+ pub const PMEVTYPER27_EL0: Self = Self::System(0b11_011_1110_1111_011);
+ /// Performance Monitors Event Type Registers - 28
+ pub const PMEVTYPER28_EL0: Self = Self::System(0b11_011_1110_1111_100);
+ /// Performance Monitors Event Type Registers - 29
+ pub const PMEVTYPER29_EL0: Self = Self::System(0b11_011_1110_1111_101);
+ /// Performance Monitors Event Type Registers - 30
+ pub const PMEVTYPER30_EL0: Self = Self::System(0b11_011_1110_1111_110);
+ /// Performance Monitors Cycle Count Filter Register
+ pub const PMCCFILTR_EL0: Self = Self::System(0b11_011_1110_1111_111);
+ /// Virtualization Processor ID Register
+ pub const VPIDR_EL2: Self = Self::System(0b11_100_0000_0000_000);
+ /// Virtualization Multiprocessor ID Register
+ pub const VMPIDR_EL2: Self = Self::System(0b11_100_0000_0000_101);
+ /// System Control Register (EL2)
+ pub const SCTLR_EL2: Self = Self::System(0b11_100_0001_0000_000);
+ /// Auxiliary Control Register (EL2)
+ pub const ACTLR_EL2: Self = Self::System(0b11_100_0001_0000_001);
+ /// Hypervisor Configuration Register
+ pub const HCR_EL2: Self = Self::System(0b11_100_0001_0001_000);
+ /// Monitor Debug Configuration Register (EL2)
+ pub const MDCR_EL2: Self = Self::System(0b11_100_0001_0001_001);
+ /// Architectural Feature Trap Register (EL2)
+ pub const CPTR_EL2: Self = Self::System(0b11_100_0001_0001_010);
+ /// Hypervisor System Trap Register
+ pub const HSTR_EL2: Self = Self::System(0b11_100_0001_0001_011);
+ /// Hypervisor Fine-Grained Read Trap Register
+ pub const HFGRTR_EL2: Self = Self::System(0b11_100_0001_0001_100);
+ /// Hypervisor Fine-Grained Write Trap Register
+ pub const HFGWTR_EL2: Self = Self::System(0b11_100_0001_0001_101);
+ /// Hypervisor Fine-Grained Instruction Trap Register
+ pub const HFGITR_EL2: Self = Self::System(0b11_100_0001_0001_110);
+ /// Hypervisor Auxiliary Control Register
+ pub const HACR_EL2: Self = Self::System(0b11_100_0001_0001_111);
+ /// SVE Control Register (EL2)
+ pub const ZCR_EL2: Self = Self::System(0b11_100_0001_0010_000);
+ /// Trace Filter Control Register (EL2)
+ pub const TRFCR_EL2: Self = Self::System(0b11_100_0001_0010_001);
+ /// Extended Hypervisor Configuration Register
+ pub const HCRX_EL2: Self = Self::System(0b11_100_0001_0010_010);
+ /// Streaming Mode Priority Mapping Register
+ pub const SMPRIMAP_EL2: Self = Self::System(0b11_100_0001_0010_101);
+ /// SME Control Register (EL2)
+ pub const SMCR_EL2: Self = Self::System(0b11_100_0001_0010_110);
+ /// AArch32 Secure Debug Enable Register
+ pub const SDER32_EL2: Self = Self::System(0b11_100_0001_0011_001);
+ /// Translation Table Base Register 0 (EL2)
+ pub const TTBR0_EL2: Self = Self::System(0b11_100_0010_0000_000);
+ /// Translation Table Base Register 1 (EL2)
+ pub const TTBR1_EL2: Self = Self::System(0b11_100_0010_0000_001);
+ /// Translation Control Register (EL2)
+ pub const TCR_EL2: Self = Self::System(0b11_100_0010_0000_010);
+ /// Virtualization Translation Table Base Register
+ pub const VTTBR_EL2: Self = Self::System(0b11_100_0010_0001_000);
+ /// Virtualization Translation Control Register
+ pub const VTCR_EL2: Self = Self::System(0b11_100_0010_0001_010);
+ /// Virtual Nested Control Register
+ pub const VNCR_EL2: Self = Self::System(0b11_100_0010_0010_000);
+ /// Virtualization Secure Translation Table Base Register
+ pub const VSTTBR_EL2: Self = Self::System(0b11_100_0010_0110_000);
+ /// Virtualization Secure Translation Control Register
+ pub const VSTCR_EL2: Self = Self::System(0b11_100_0010_0110_010);
+ /// Domain Access Control Register
+ pub const DACR32_EL2: Self = Self::System(0b11_100_0011_0000_000);
+ /// Hypervisor Debug Fine-Grained Read Trap Register
+ pub const HDFGRTR_EL2: Self = Self::System(0b11_100_0011_0001_100);
+ /// Hypervisor Debug Fine-Grained Write Trap Register
+ pub const HDFGWTR_EL2: Self = Self::System(0b11_100_0011_0001_101);
+ /// Hypervisor Activity Monitors Fine-Grained Read Trap Register
+ pub const HAFGRTR_EL2: Self = Self::System(0b11_100_0011_0001_110);
+ /// Saved Program Status Register (EL2)
+ pub const SPSR_EL2: Self = Self::System(0b11_100_0100_0000_000);
+ /// Exception Link Register (EL2)
+ pub const ELR_EL2: Self = Self::System(0b11_100_0100_0000_001);
+ /// Stack Pointer (EL1)
+ pub const SP_EL1: Self = Self::System(0b11_100_0100_0001_000);
+ /// Saved Program Status Register (IRQ Mode)
+ pub const SPSR_IRQ: Self = Self::System(0b11_100_0100_0011_000);
+ /// Saved Program Status Register (Abort Mode)
+ pub const SPSR_ABT: Self = Self::System(0b11_100_0100_0011_001);
+ /// Saved Program Status Register (Undefined Mode)
+ pub const SPSR_UND: Self = Self::System(0b11_100_0100_0011_010);
+ /// Saved Program Status Register (FIQ Mode)
+ pub const SPSR_FIQ: Self = Self::System(0b11_100_0100_0011_011);
+ /// Instruction Fault Status Register (EL2)
+ pub const IFSR32_EL2: Self = Self::System(0b11_100_0101_0000_001);
+ /// Auxiliary Fault Status Register 0 (EL2)
+ pub const AFSR0_EL2: Self = Self::System(0b11_100_0101_0001_000);
+ /// Auxiliary Fault Status Register 1 (EL2)
+ pub const AFSR1_EL2: Self = Self::System(0b11_100_0101_0001_001);
+ /// Exception Syndrome Register (EL2)
+ pub const ESR_EL2: Self = Self::System(0b11_100_0101_0010_000);
+ /// Virtual SError Exception Syndrome Register
+ pub const VSESR_EL2: Self = Self::System(0b11_100_0101_0010_011);
+ /// Floating-Point Exception Control Register
+ pub const FPEXC32_EL2: Self = Self::System(0b11_100_0101_0011_000);
+ /// Tag Fault Status Register (EL2)
+ pub const TFSR_EL2: Self = Self::System(0b11_100_0101_0110_000);
+ /// Fault Address Register (EL2)
+ pub const FAR_EL2: Self = Self::System(0b11_100_0110_0000_000);
+ /// Hypervisor IPA Fault Address Register
+ pub const HPFAR_EL2: Self = Self::System(0b11_100_0110_0000_100);
+ /// Statistical Profiling Control Register (EL2)
+ pub const PMSCR_EL2: Self = Self::System(0b11_100_1001_1001_000);
+ /// Memory Attribute Indirection Register (EL2)
+ pub const MAIR_EL2: Self = Self::System(0b11_100_1010_0010_000);
+ /// Auxiliary Memory Attribute Indirection Register (EL2)
+ pub const AMAIR_EL2: Self = Self::System(0b11_100_1010_0011_000);
+ /// MPAM Hypervisor Control Register (EL2)
+ pub const MPAMHCR_EL2: Self = Self::System(0b11_100_1010_0100_000);
+ /// MPAM Virtual Partition Mapping Valid Register
+ pub const MPAMVPMV_EL2: Self = Self::System(0b11_100_1010_0100_001);
+ /// MPAM2 Register (EL2)
+ pub const MPAM2_EL2: Self = Self::System(0b11_100_1010_0101_000);
+ /// MPAM Virtual PARTID Mapping Register 0
+ pub const MPAMVPM0_EL2: Self = Self::System(0b11_100_1010_0110_000);
+ /// MPAM Virtual PARTID Mapping Register 1
+ pub const MPAMVPM1_EL2: Self = Self::System(0b11_100_1010_0110_001);
+ /// MPAM Virtual PARTID Mapping Register 2
+ pub const MPAMVPM2_EL2: Self = Self::System(0b11_100_1010_0110_010);
+ /// MPAM Virtual PARTID Mapping Register 3
+ pub const MPAMVPM3_EL2: Self = Self::System(0b11_100_1010_0110_011);
+ /// MPAM Virtual PARTID Mapping Register 4
+ pub const MPAMVPM4_EL2: Self = Self::System(0b11_100_1010_0110_100);
+ /// MPAM Virtual PARTID Mapping Register 5
+ pub const MPAMVPM5_EL2: Self = Self::System(0b11_100_1010_0110_101);
+ /// MPAM Virtual PARTID Mapping Register 6
+ pub const MPAMVPM6_EL2: Self = Self::System(0b11_100_1010_0110_110);
+ /// MPAM Virtual PARTID Mapping Register 7
+ pub const MPAMVPM7_EL2: Self = Self::System(0b11_100_1010_0110_111);
+ /// Vector Base Address Register (EL2)
+ pub const VBAR_EL2: Self = Self::System(0b11_100_1100_0000_000);
+ /// Reset Vector Base Address Register (if EL3 Not Implemented)
+ pub const RVBAR_EL2: Self = Self::System(0b11_100_1100_0000_001);
+ /// Reset Management Register (EL2)
+ pub const RMR_EL2: Self = Self::System(0b11_100_1100_0000_010);
+ /// Virtual Deferred Interrupt Status Register
+ pub const VDISR_EL2: Self = Self::System(0b11_100_1100_0001_001);
+ /// Interrupt Controller Hyp Active Priorities Group 0 Registers - 0
+ pub const ICH_AP0R0_EL2: Self = Self::System(0b11_100_1100_1000_000);
+ /// Interrupt Controller Hyp Active Priorities Group 0 Registers - 1
+ pub const ICH_AP0R1_EL2: Self = Self::System(0b11_100_1100_1000_001);
+ /// Interrupt Controller Hyp Active Priorities Group 0 Registers - 2
+ pub const ICH_AP0R2_EL2: Self = Self::System(0b11_100_1100_1000_010);
+ /// Interrupt Controller Hyp Active Priorities Group 0 Registers - 3
+ pub const ICH_AP0R3_EL2: Self = Self::System(0b11_100_1100_1000_011);
+ /// Interrupt Controller Hyp Active Priorities Group 1 Registers - 0
+ pub const ICH_AP1R0_EL2: Self = Self::System(0b11_100_1100_1001_000);
+ /// Interrupt Controller Hyp Active Priorities Group 1 Registers - 1
+ pub const ICH_AP1R1_EL2: Self = Self::System(0b11_100_1100_1001_001);
+ /// Interrupt Controller Hyp Active Priorities Group 1 Registers - 2
+ pub const ICH_AP1R2_EL2: Self = Self::System(0b11_100_1100_1001_010);
+ /// Interrupt Controller Hyp Active Priorities Group 1 Registers - 3
+ pub const ICH_AP1R3_EL2: Self = Self::System(0b11_100_1100_1001_011);
+ /// Interrupt Controller System Register Enable Register (EL2)
+ pub const ICC_SRE_EL2: Self = Self::System(0b11_100_1100_1001_101);
+ /// Interrupt Controller Hyp Control Register
+ pub const ICH_HCR_EL2: Self = Self::System(0b11_100_1100_1011_000);
+ /// Interrupt Controller VGIC Type Register
+ pub const ICH_VTR_EL2: Self = Self::System(0b11_100_1100_1011_001);
+ /// Interrupt Controller Maintenance Interrupt State Register
+ pub const ICH_MISR_EL2: Self = Self::System(0b11_100_1100_1011_010);
+ /// Interrupt Controller End Of Interrupt Status Register
+ pub const ICH_EISR_EL2: Self = Self::System(0b11_100_1100_1011_011);
+ /// Interrupt Controller Empty List Register Status Register
+ pub const ICH_ELRSR_EL2: Self = Self::System(0b11_100_1100_1011_101);
+ /// Interrupt Controller Virtual Machine Control Register
+ pub const ICH_VMCR_EL2: Self = Self::System(0b11_100_1100_1011_111);
+ /// Interrupt Controller List Registers - 0
+ pub const ICH_LR0_EL2: Self = Self::System(0b11_100_1100_1100_000);
+ /// Interrupt Controller List Registers - 1
+ pub const ICH_LR1_EL2: Self = Self::System(0b11_100_1100_1100_001);
+ /// Interrupt Controller List Registers - 2
+ pub const ICH_LR2_EL2: Self = Self::System(0b11_100_1100_1100_010);
+ /// Interrupt Controller List Registers - 3
+ pub const ICH_LR3_EL2: Self = Self::System(0b11_100_1100_1100_011);
+ /// Interrupt Controller List Registers - 4
+ pub const ICH_LR4_EL2: Self = Self::System(0b11_100_1100_1100_100);
+ /// Interrupt Controller List Registers - 5
+ pub const ICH_LR5_EL2: Self = Self::System(0b11_100_1100_1100_101);
+ /// Interrupt Controller List Registers - 6
+ pub const ICH_LR6_EL2: Self = Self::System(0b11_100_1100_1100_110);
+ /// Interrupt Controller List Registers - 7
+ pub const ICH_LR7_EL2: Self = Self::System(0b11_100_1100_1100_111);
+ /// Interrupt Controller List Registers - 8
+ pub const ICH_LR8_EL2: Self = Self::System(0b11_100_1100_1101_000);
+ /// Interrupt Controller List Registers - 9
+ pub const ICH_LR9_EL2: Self = Self::System(0b11_100_1100_1101_001);
+ /// Interrupt Controller List Registers - 10
+ pub const ICH_LR10_EL2: Self = Self::System(0b11_100_1100_1101_010);
+ /// Interrupt Controller List Registers - 11
+ pub const ICH_LR11_EL2: Self = Self::System(0b11_100_1100_1101_011);
+ /// Interrupt Controller List Registers - 12
+ pub const ICH_LR12_EL2: Self = Self::System(0b11_100_1100_1101_100);
+ /// Interrupt Controller List Registers - 13
+ pub const ICH_LR13_EL2: Self = Self::System(0b11_100_1100_1101_101);
+ /// Interrupt Controller List Registers - 14
+ pub const ICH_LR14_EL2: Self = Self::System(0b11_100_1100_1101_110);
+ /// Interrupt Controller List Registers - 15
+ pub const ICH_LR15_EL2: Self = Self::System(0b11_100_1100_1101_111);
+ /// Context ID Register (EL2)
+ pub const CONTEXTIDR_EL2: Self = Self::System(0b11_100_1101_0000_001);
+ /// EL2 Software Thread ID Register
+ pub const TPIDR_EL2: Self = Self::System(0b11_100_1101_0000_010);
+ /// EL2 Read/Write Software Context Number
+ pub const SCXTNUM_EL2: Self = Self::System(0b11_100_1101_0000_111);
+ /// Activity Monitors Event Counter Virtual Offset Registers 0 - 0
+ pub const AMEVCNTVOFF00_EL2: Self = Self::System(0b11_100_1101_1000_000);
+ /// Activity Monitors Event Counter Virtual Offset Registers 0 - 1
+ pub const AMEVCNTVOFF01_EL2: Self = Self::System(0b11_100_1101_1000_001);
+ /// Activity Monitors Event Counter Virtual Offset Registers 0 - 2
+ pub const AMEVCNTVOFF02_EL2: Self = Self::System(0b11_100_1101_1000_010);
+ /// Activity Monitors Event Counter Virtual Offset Registers 0 - 3
+ pub const AMEVCNTVOFF03_EL2: Self = Self::System(0b11_100_1101_1000_011);
+ /// Activity Monitors Event Counter Virtual Offset Registers 0 - 4
+ pub const AMEVCNTVOFF04_EL2: Self = Self::System(0b11_100_1101_1000_100);
+ /// Activity Monitors Event Counter Virtual Offset Registers 0 - 5
+ pub const AMEVCNTVOFF05_EL2: Self = Self::System(0b11_100_1101_1000_101);
+ /// Activity Monitors Event Counter Virtual Offset Registers 0 - 6
+ pub const AMEVCNTVOFF06_EL2: Self = Self::System(0b11_100_1101_1000_110);
+ /// Activity Monitors Event Counter Virtual Offset Registers 0 - 7
+ pub const AMEVCNTVOFF07_EL2: Self = Self::System(0b11_100_1101_1000_111);
+ /// Activity Monitors Event Counter Virtual Offset Registers 0 - 8
+ pub const AMEVCNTVOFF08_EL2: Self = Self::System(0b11_100_1101_1001_000);
+ /// Activity Monitors Event Counter Virtual Offset Registers 0 - 9
+ pub const AMEVCNTVOFF09_EL2: Self = Self::System(0b11_100_1101_1001_001);
+ /// Activity Monitors Event Counter Virtual Offset Registers 0 - 10
+ pub const AMEVCNTVOFF010_EL2: Self = Self::System(0b11_100_1101_1001_010);
+ /// Activity Monitors Event Counter Virtual Offset Registers 0 - 11
+ pub const AMEVCNTVOFF011_EL2: Self = Self::System(0b11_100_1101_1001_011);
+ /// Activity Monitors Event Counter Virtual Offset Registers 0 - 12
+ pub const AMEVCNTVOFF012_EL2: Self = Self::System(0b11_100_1101_1001_100);
+ /// Activity Monitors Event Counter Virtual Offset Registers 0 - 13
+ pub const AMEVCNTVOFF013_EL2: Self = Self::System(0b11_100_1101_1001_101);
+ /// Activity Monitors Event Counter Virtual Offset Registers 0 - 14
+ pub const AMEVCNTVOFF014_EL2: Self = Self::System(0b11_100_1101_1001_110);
+ /// Activity Monitors Event Counter Virtual Offset Registers 0 - 15
+ pub const AMEVCNTVOFF015_EL2: Self = Self::System(0b11_100_1101_1001_111);
+ /// Activity Monitors Event Counter Virtual Offset Registers 1 - 0
+ pub const AMEVCNTVOFF10_EL2: Self = Self::System(0b11_100_1101_1010_000);
+ /// Activity Monitors Event Counter Virtual Offset Registers 1 - 1
+ pub const AMEVCNTVOFF11_EL2: Self = Self::System(0b11_100_1101_1010_001);
+ /// Activity Monitors Event Counter Virtual Offset Registers 1 - 2
+ pub const AMEVCNTVOFF12_EL2: Self = Self::System(0b11_100_1101_1010_010);
+ /// Activity Monitors Event Counter Virtual Offset Registers 1 - 3
+ pub const AMEVCNTVOFF13_EL2: Self = Self::System(0b11_100_1101_1010_011);
+ /// Activity Monitors Event Counter Virtual Offset Registers 1 - 4
+ pub const AMEVCNTVOFF14_EL2: Self = Self::System(0b11_100_1101_1010_100);
+ /// Activity Monitors Event Counter Virtual Offset Registers 1 - 5
+ pub const AMEVCNTVOFF15_EL2: Self = Self::System(0b11_100_1101_1010_101);
+ /// Activity Monitors Event Counter Virtual Offset Registers 1 - 6
+ pub const AMEVCNTVOFF16_EL2: Self = Self::System(0b11_100_1101_1010_110);
+ /// Activity Monitors Event Counter Virtual Offset Registers 1 - 7
+ pub const AMEVCNTVOFF17_EL2: Self = Self::System(0b11_100_1101_1010_111);
+ /// Activity Monitors Event Counter Virtual Offset Registers 1 - 8
+ pub const AMEVCNTVOFF18_EL2: Self = Self::System(0b11_100_1101_1011_000);
+ /// Activity Monitors Event Counter Virtual Offset Registers 1 - 9
+ pub const AMEVCNTVOFF19_EL2: Self = Self::System(0b11_100_1101_1011_001);
+ /// Activity Monitors Event Counter Virtual Offset Registers 1 - 10
+ pub const AMEVCNTVOFF110_EL2: Self = Self::System(0b11_100_1101_1011_010);
+ /// Activity Monitors Event Counter Virtual Offset Registers 1 - 11
+ pub const AMEVCNTVOFF111_EL2: Self = Self::System(0b11_100_1101_1011_011);
+ /// Activity Monitors Event Counter Virtual Offset Registers 1 - 12
+ pub const AMEVCNTVOFF112_EL2: Self = Self::System(0b11_100_1101_1011_100);
+ /// Activity Monitors Event Counter Virtual Offset Registers 1 - 13
+ pub const AMEVCNTVOFF113_EL2: Self = Self::System(0b11_100_1101_1011_101);
+ /// Activity Monitors Event Counter Virtual Offset Registers 1 - 14
+ pub const AMEVCNTVOFF114_EL2: Self = Self::System(0b11_100_1101_1011_110);
+ /// Activity Monitors Event Counter Virtual Offset Registers 1 - 15
+ pub const AMEVCNTVOFF115_EL2: Self = Self::System(0b11_100_1101_1011_111);
+ /// Counter-timer Virtual Offset Register
+ pub const CNTVOFF_EL2: Self = Self::System(0b11_100_1110_0000_011);
+ /// Counter-timer Physical Offset Register
+ pub const CNTPOFF_EL2: Self = Self::System(0b11_100_1110_0000_110);
+ /// Counter-timer Hypervisor Control Register
+ pub const CNTHCTL_EL2: Self = Self::System(0b11_100_1110_0001_000);
+ /// Counter-timer Physical Timer TimerValue Register (EL2)
+ pub const CNTHP_TVAL_EL2: Self = Self::System(0b11_100_1110_0010_000);
+ /// Counter-timer Hypervisor Physical Timer Control Register
+ pub const CNTHP_CTL_EL2: Self = Self::System(0b11_100_1110_0010_001);
+ /// Counter-timer Physical Timer CompareValue Register (EL2)
+ pub const CNTHP_CVAL_EL2: Self = Self::System(0b11_100_1110_0010_010);
+ /// Counter-timer Virtual Timer TimerValue Register (EL2)
+ pub const CNTHV_TVAL_EL2: Self = Self::System(0b11_100_1110_0011_000);
+ /// Counter-timer Virtual Timer Control Register (EL2)
+ pub const CNTHV_CTL_EL2: Self = Self::System(0b11_100_1110_0011_001);
+ /// Counter-timer Virtual Timer CompareValue Register (EL2)
+ pub const CNTHV_CVAL_EL2: Self = Self::System(0b11_100_1110_0011_010);
+ /// Counter-timer Secure Virtual Timer TimerValue Register (EL2)
+ pub const CNTHVS_TVAL_EL2: Self = Self::System(0b11_100_1110_0100_000);
+ /// Counter-timer Secure Virtual Timer Control Register (EL2)
+ pub const CNTHVS_CTL_EL2: Self = Self::System(0b11_100_1110_0100_001);
+ /// Counter-timer Secure Virtual Timer CompareValue Register (EL2)
+ pub const CNTHVS_CVAL_EL2: Self = Self::System(0b11_100_1110_0100_010);
+ /// Counter-timer Secure Physical Timer TimerValue Register (EL2)
+ pub const CNTHPS_TVAL_EL2: Self = Self::System(0b11_100_1110_0101_000);
+ /// Counter-timer Secure Physical Timer Control Register (EL2)
+ pub const CNTHPS_CTL_EL2: Self = Self::System(0b11_100_1110_0101_001);
+ /// Counter-timer Secure Physical Timer CompareValue Register (EL2)
+ pub const CNTHPS_CVAL_EL2: Self = Self::System(0b11_100_1110_0101_010);
+ /// System Control Register (EL3)
+ pub const SCTLR_EL3: Self = Self::System(0b11_110_0001_0000_000);
+ /// Auxiliary Control Register (EL3)
+ pub const ACTLR_EL3: Self = Self::System(0b11_110_0001_0000_001);
+ /// Secure Configuration Register
+ pub const SCR_EL3: Self = Self::System(0b11_110_0001_0001_000);
+ /// AArch32 Secure Debug Enable Register
+ pub const SDER32_EL3: Self = Self::System(0b11_110_0001_0001_001);
+ /// Architectural Feature Trap Register (EL3)
+ pub const CPTR_EL3: Self = Self::System(0b11_110_0001_0001_010);
+ /// SVE Control Register (EL3)
+ pub const ZCR_EL3: Self = Self::System(0b11_110_0001_0010_000);
+ /// SME Control Register (EL3)
+ pub const SMCR_EL3: Self = Self::System(0b11_110_0001_0010_110);
+ /// Monitor Debug Configuration Register (EL3)
+ pub const MDCR_EL3: Self = Self::System(0b11_110_0001_0011_001);
+ /// Translation Table Base Register 0 (EL3)
+ pub const TTBR0_EL3: Self = Self::System(0b11_110_0010_0000_000);
+ /// Translation Control Register (EL3)
+ pub const TCR_EL3: Self = Self::System(0b11_110_0010_0000_010);
+ /// Granule Protection Table Base Register
+ pub const GPTBR_EL3: Self = Self::System(0b11_110_0010_0001_100);
+ /// Granule Protection Check Control Register (EL3)
+ pub const GPCCR_EL3: Self = Self::System(0b11_110_0010_0001_110);
+ /// Saved Program Status Register (EL3)
+ pub const SPSR_EL3: Self = Self::System(0b11_110_0100_0000_000);
+ /// Exception Link Register (EL3)
+ pub const ELR_EL3: Self = Self::System(0b11_110_0100_0000_001);
+ /// Stack Pointer (EL2)
+ pub const SP_EL2: Self = Self::System(0b11_110_0100_0001_000);
+ /// Auxiliary Fault Status Register 0 (EL3)
+ pub const AFSR0_EL3: Self = Self::System(0b11_110_0101_0001_000);
+ /// Auxiliary Fault Status Register 1 (EL3)
+ pub const AFSR1_EL3: Self = Self::System(0b11_110_0101_0001_001);
+ /// Exception Syndrome Register (EL3)
+ pub const ESR_EL3: Self = Self::System(0b11_110_0101_0010_000);
+ /// Tag Fault Status Register (EL3)
+ pub const TFSR_EL3: Self = Self::System(0b11_110_0101_0110_000);
+ /// Fault Address Register (EL3)
+ pub const FAR_EL3: Self = Self::System(0b11_110_0110_0000_000);
+ /// PA Fault Address Register
+ pub const MFAR_EL3: Self = Self::System(0b11_110_0110_0000_101);
+ /// Memory Attribute Indirection Register (EL3)
+ pub const MAIR_EL3: Self = Self::System(0b11_110_1010_0010_000);
+ /// Auxiliary Memory Attribute Indirection Register (EL3)
+ pub const AMAIR_EL3: Self = Self::System(0b11_110_1010_0011_000);
+ /// MPAM3 Register (EL3)
+ pub const MPAM3_EL3: Self = Self::System(0b11_110_1010_0101_000);
+ /// Vector Base Address Register (EL3)
+ pub const VBAR_EL3: Self = Self::System(0b11_110_1100_0000_000);
+ /// Reset Vector Base Address Register (if EL3 Implemented)
+ pub const RVBAR_EL3: Self = Self::System(0b11_110_1100_0000_001);
+ /// Reset Management Register (EL3)
+ pub const RMR_EL3: Self = Self::System(0b11_110_1100_0000_010);
+ /// Interrupt Controller Control Register (EL3)
+ pub const ICC_CTLR_EL3: Self = Self::System(0b11_110_1100_1100_100);
+ /// Interrupt Controller System Register Enable Register (EL3)
+ pub const ICC_SRE_EL3: Self = Self::System(0b11_110_1100_1100_101);
+ /// Interrupt Controller Interrupt Group 1 Enable Register (EL3)
+ pub const ICC_IGRPEN1_EL3: Self = Self::System(0b11_110_1100_1100_111);
+ /// EL3 Software Thread ID Register
+ pub const TPIDR_EL3: Self = Self::System(0b11_110_1101_0000_010);
+ /// EL3 Read/Write Software Context Number
+ pub const SCXTNUM_EL3: Self = Self::System(0b11_110_1101_0000_111);
+ /// Counter-timer Physical Secure Timer TimerValue Register
+ pub const CNTPS_TVAL_EL1: Self = Self::System(0b11_111_1110_0010_000);
+ /// Counter-timer Physical Secure Timer Control Register
+ pub const CNTPS_CTL_EL1: Self = Self::System(0b11_111_1110_0010_001);
+ /// Counter-timer Physical Secure Timer CompareValue Register
+ pub const CNTPS_CVAL_EL1: Self = Self::System(0b11_111_1110_0010_010);
+
+ /// OS Lock Data Transfer Register, Receive
+ pub const OSDTRRX_EL1: Self = Self::System(0b10_000_0000_0000_010);
+ /// Debug Breakpoint Value Registers - 0
+ pub const DBGBVR0_EL1: Self = Self::System(0b10_000_0000_0000_100);
+ /// Debug Breakpoint Control Registers - 0
+ pub const DBGBCR0_EL1: Self = Self::System(0b10_000_0000_0000_101);
+ /// Debug Watchpoint Value Registers - 0
+ pub const DBGWVR0_EL1: Self = Self::System(0b10_000_0000_0000_110);
+ /// Debug Watchpoint Control Registers - 0
+ pub const DBGWCR0_EL1: Self = Self::System(0b10_000_0000_0000_111);
+ /// Debug Breakpoint Value Registers - 1
+ pub const DBGBVR1_EL1: Self = Self::System(0b10_000_0000_0001_100);
+ /// Debug Breakpoint Control Registers - 1
+ pub const DBGBCR1_EL1: Self = Self::System(0b10_000_0000_0001_101);
+ /// Debug Watchpoint Value Registers - 1
+ pub const DBGWVR1_EL1: Self = Self::System(0b10_000_0000_0001_110);
+ /// Debug Watchpoint Control Registers - 1
+ pub const DBGWCR1_EL1: Self = Self::System(0b10_000_0000_0001_111);
+ /// Monitor DCC Interrupt Enable Register
+ pub const MDCCINT_EL1: Self = Self::System(0b10_000_0000_0010_000);
+ /// Monitor Debug System Control Register
+ pub const MDSCR_EL1: Self = Self::System(0b10_000_0000_0010_010);
+ /// Debug Breakpoint Value Registers - 2
+ pub const DBGBVR2_EL1: Self = Self::System(0b10_000_0000_0010_100);
+ /// Debug Breakpoint Control Registers - 2
+ pub const DBGBCR2_EL1: Self = Self::System(0b10_000_0000_0010_101);
+ /// Debug Watchpoint Value Registers - 2
+ pub const DBGWVR2_EL1: Self = Self::System(0b10_000_0000_0010_110);
+ /// Debug Watchpoint Control Registers - 2
+ pub const DBGWCR2_EL1: Self = Self::System(0b10_000_0000_0010_111);
+ /// OS Lock Data Transfer Register, Transmit
+ pub const OSDTRTX_EL1: Self = Self::System(0b10_000_0000_0011_010);
+ /// Debug Breakpoint Value Registers - 3
+ pub const DBGBVR3_EL1: Self = Self::System(0b10_000_0000_0011_100);
+ /// Debug Breakpoint Control Registers - 3
+ pub const DBGBCR3_EL1: Self = Self::System(0b10_000_0000_0011_101);
+ /// Debug Watchpoint Value Registers - 3
+ pub const DBGWVR3_EL1: Self = Self::System(0b10_000_0000_0011_110);
+ /// Debug Watchpoint Control Registers - 3
+ pub const DBGWCR3_EL1: Self = Self::System(0b10_000_0000_0011_111);
+ /// Debug Breakpoint Value Registers - 4
+ pub const DBGBVR4_EL1: Self = Self::System(0b10_000_0000_0100_100);
+ /// Debug Breakpoint Control Registers - 4
+ pub const DBGBCR4_EL1: Self = Self::System(0b10_000_0000_0100_101);
+ /// Debug Watchpoint Value Registers - 4
+ pub const DBGWVR4_EL1: Self = Self::System(0b10_000_0000_0100_110);
+ /// Debug Watchpoint Control Registers - 4
+ pub const DBGWCR4_EL1: Self = Self::System(0b10_000_0000_0100_111);
+ /// Debug Breakpoint Value Registers - 5
+ pub const DBGBVR5_EL1: Self = Self::System(0b10_000_0000_0101_100);
+ /// Debug Breakpoint Control Registers - 5
+ pub const DBGBCR5_EL1: Self = Self::System(0b10_000_0000_0101_101);
+ /// Debug Watchpoint Value Registers - 5
+ pub const DBGWVR5_EL1: Self = Self::System(0b10_000_0000_0101_110);
+ /// Debug Watchpoint Control Registers - 5
+ pub const DBGWCR5_EL1: Self = Self::System(0b10_000_0000_0101_111);
+ /// OS Lock Exception Catch Control Register
+ pub const OSECCR_EL1: Self = Self::System(0b10_000_0000_0110_010);
+ /// Debug Breakpoint Value Registers - 6
+ pub const DBGBVR6_EL1: Self = Self::System(0b10_000_0000_0110_100);
+ /// Debug Breakpoint Control Registers - 6
+ pub const DBGBCR6_EL1: Self = Self::System(0b10_000_0000_0110_101);
+ /// Debug Watchpoint Value Registers - 6
+ pub const DBGWVR6_EL1: Self = Self::System(0b10_000_0000_0110_110);
+ /// Debug Watchpoint Control Registers - 6
+ pub const DBGWCR6_EL1: Self = Self::System(0b10_000_0000_0110_111);
+ /// Debug Breakpoint Value Registers - 7
+ pub const DBGBVR7_EL1: Self = Self::System(0b10_000_0000_0111_100);
+ /// Debug Breakpoint Control Registers - 7
+ pub const DBGBCR7_EL1: Self = Self::System(0b10_000_0000_0111_101);
+ /// Debug Watchpoint Value Registers - 7
+ pub const DBGWVR7_EL1: Self = Self::System(0b10_000_0000_0111_110);
+ /// Debug Watchpoint Control Registers - 7
+ pub const DBGWCR7_EL1: Self = Self::System(0b10_000_0000_0111_111);
+ /// Debug Breakpoint Value Registers - 8
+ pub const DBGBVR8_EL1: Self = Self::System(0b10_000_0000_1000_100);
+ /// Debug Breakpoint Control Registers - 8
+ pub const DBGBCR8_EL1: Self = Self::System(0b10_000_0000_1000_101);
+ /// Debug Watchpoint Value Registers - 8
+ pub const DBGWVR8_EL1: Self = Self::System(0b10_000_0000_1000_110);
+ /// Debug Watchpoint Control Registers - 8
+ pub const DBGWCR8_EL1: Self = Self::System(0b10_000_0000_1000_111);
+ /// Debug Breakpoint Value Registers - 9
+ pub const DBGBVR9_EL1: Self = Self::System(0b10_000_0000_1001_100);
+ /// Debug Breakpoint Control Registers - 9
+ pub const DBGBCR9_EL1: Self = Self::System(0b10_000_0000_1001_101);
+ /// Debug Watchpoint Value Registers - 9
+ pub const DBGWVR9_EL1: Self = Self::System(0b10_000_0000_1001_110);
+ /// Debug Watchpoint Control Registers - 9
+ pub const DBGWCR9_EL1: Self = Self::System(0b10_000_0000_1001_111);
+ /// Debug Breakpoint Value Registers - 10
+ pub const DBGBVR10_EL1: Self = Self::System(0b10_000_0000_1010_100);
+ /// Debug Breakpoint Control Registers - 10
+ pub const DBGBCR10_EL1: Self = Self::System(0b10_000_0000_1010_101);
+ /// Debug Watchpoint Value Registers - 10
+ pub const DBGWVR10_EL1: Self = Self::System(0b10_000_0000_1010_110);
+ /// Debug Watchpoint Control Registers - 10
+ pub const DBGWCR10_EL1: Self = Self::System(0b10_000_0000_1010_111);
+ /// Debug Breakpoint Value Registers - 11
+ pub const DBGBVR11_EL1: Self = Self::System(0b10_000_0000_1011_100);
+ /// Debug Breakpoint Control Registers - 11
+ pub const DBGBCR11_EL1: Self = Self::System(0b10_000_0000_1011_101);
+ /// Debug Watchpoint Value Registers - 11
+ pub const DBGWVR11_EL1: Self = Self::System(0b10_000_0000_1011_110);
+ /// Debug Watchpoint Control Registers - 11
+ pub const DBGWCR11_EL1: Self = Self::System(0b10_000_0000_1011_111);
+ /// Debug Breakpoint Value Registers - 12
+ pub const DBGBVR12_EL1: Self = Self::System(0b10_000_0000_1100_100);
+ /// Debug Breakpoint Control Registers - 12
+ pub const DBGBCR12_EL1: Self = Self::System(0b10_000_0000_1100_101);
+ /// Debug Watchpoint Value Registers - 12
+ pub const DBGWVR12_EL1: Self = Self::System(0b10_000_0000_1100_110);
+ /// Debug Watchpoint Control Registers - 12
+ pub const DBGWCR12_EL1: Self = Self::System(0b10_000_0000_1100_111);
+ /// Debug Breakpoint Value Registers - 13
+ pub const DBGBVR13_EL1: Self = Self::System(0b10_000_0000_1101_100);
+ /// Debug Breakpoint Control Registers - 13
+ pub const DBGBCR13_EL1: Self = Self::System(0b10_000_0000_1101_101);
+ /// Debug Watchpoint Value Registers - 13
+ pub const DBGWVR13_EL1: Self = Self::System(0b10_000_0000_1101_110);
+ /// Debug Watchpoint Control Registers - 13
+ pub const DBGWCR13_EL1: Self = Self::System(0b10_000_0000_1101_111);
+ /// Debug Breakpoint Value Registers - 14
+ pub const DBGBVR14_EL1: Self = Self::System(0b10_000_0000_1110_100);
+ /// Debug Breakpoint Control Registers - 14
+ pub const DBGBCR14_EL1: Self = Self::System(0b10_000_0000_1110_101);
+ /// Debug Watchpoint Value Registers - 14
+ pub const DBGWVR14_EL1: Self = Self::System(0b10_000_0000_1110_110);
+ /// Debug Watchpoint Control Registers - 14
+ pub const DBGWCR14_EL1: Self = Self::System(0b10_000_0000_1110_111);
+ /// Debug Breakpoint Value Registers - 15
+ pub const DBGBVR15_EL1: Self = Self::System(0b10_000_0000_1111_100);
+ /// Debug Breakpoint Control Registers - 15
+ pub const DBGBCR15_EL1: Self = Self::System(0b10_000_0000_1111_101);
+ /// Debug Watchpoint Value Registers - 15
+ pub const DBGWVR15_EL1: Self = Self::System(0b10_000_0000_1111_110);
+ /// Debug Watchpoint Control Registers - 15
+ pub const DBGWCR15_EL1: Self = Self::System(0b10_000_0000_1111_111);
+ /// Monitor Debug ROM Address Register
+ pub const MDRAR_EL1: Self = Self::System(0b10_000_0001_0000_000);
+ /// OS Lock Access Register
+ pub const OSLAR_EL1: Self = Self::System(0b10_000_0001_0000_100);
+ /// OS Lock Status Register
+ pub const OSLSR_EL1: Self = Self::System(0b10_000_0001_0001_100);
+ /// OS Double Lock Register
+ pub const OSDLR_EL1: Self = Self::System(0b10_000_0001_0011_100);
+ /// Debug Power Control Register
+ pub const DBGPRCR_EL1: Self = Self::System(0b10_000_0001_0100_100);
+ /// Debug CLAIM Tag Set Register
+ pub const DBGCLAIMSET_EL1: Self = Self::System(0b10_000_0111_1000_110);
+ /// Debug CLAIM Tag Clear Register
+ pub const DBGCLAIMCLR_EL1: Self = Self::System(0b10_000_0111_1001_110);
+ /// Debug Authentication Status Register
+ pub const DBGAUTHSTATUS_EL1: Self = Self::System(0b10_000_0111_1110_110);
+ /// Trace ID Register
+ pub const TRCTRACEIDR: Self = Self::System(0b10_001_0000_0000_001);
+ /// ViewInst Main Control Register
+ pub const TRCVICTLR: Self = Self::System(0b10_001_0000_0000_010);
+ /// Sequencer State Transition Control Register 0
+ pub const TRCSEQEVR0: Self = Self::System(0b10_001_0000_0000_100);
+ /// Counter Reload Value Register 0
+ pub const TRCCNTRLDVR0: Self = Self::System(0b10_001_0000_0000_101);
+ /// ID Register 8
+ pub const TRCIDR8: Self = Self::System(0b10_001_0000_0000_110);
+ /// IMP DEF Register 0
+ pub const TRCIMSPEC0: Self = Self::System(0b10_001_0000_0000_111);
+ /// Programming Control Register
+ pub const TRCPRGCTLR: Self = Self::System(0b10_001_0000_0001_000);
+ /// Q Element Control Register
+ pub const TRCQCTLR: Self = Self::System(0b10_001_0000_0001_001);
+ /// ViewInst Include/Exclude Control Register
+ pub const TRCVIIECTLR: Self = Self::System(0b10_001_0000_0001_010);
+ /// Sequencer State Transition Control Register 1
+ pub const TRCSEQEVR1: Self = Self::System(0b10_001_0000_0001_100);
+ /// Counter Reload Value Register 1
+ pub const TRCCNTRLDVR1: Self = Self::System(0b10_001_0000_0001_101);
+ /// ID Register 9
+ pub const TRCIDR9: Self = Self::System(0b10_001_0000_0001_110);
+ /// IMP DEF Register 1
+ pub const TRCIMSPEC1: Self = Self::System(0b10_001_0000_0001_111);
+ /// ViewInst Start/Stop Control Register
+ pub const TRCVISSCTLR: Self = Self::System(0b10_001_0000_0010_010);
+ /// Sequencer State Transition Control Register 2
+ pub const TRCSEQEVR2: Self = Self::System(0b10_001_0000_0010_100);
+ /// Counter Reload Value Register 2
+ pub const TRCCNTRLDVR2: Self = Self::System(0b10_001_0000_0010_101);
+ /// ID Register 10
+ pub const TRCIDR10: Self = Self::System(0b10_001_0000_0010_110);
+ /// IMP DEF Register 2
+ pub const TRCIMSPEC2: Self = Self::System(0b10_001_0000_0010_111);
+ /// Trace Status Register
+ pub const TRCSTATR: Self = Self::System(0b10_001_0000_0011_000);
+ /// ViewInst Start/Stop PE Comparator Control Register
+ pub const TRCVIPCSSCTLR: Self = Self::System(0b10_001_0000_0011_010);
+ /// Counter Reload Value Register 3
+ pub const TRCCNTRLDVR3: Self = Self::System(0b10_001_0000_0011_101);
+ /// ID Register 11
+ pub const TRCIDR11: Self = Self::System(0b10_001_0000_0011_110);
+ /// IMP DEF Register 3
+ pub const TRCIMSPEC3: Self = Self::System(0b10_001_0000_0011_111);
+ /// Trace Configuration Register
+ pub const TRCCONFIGR: Self = Self::System(0b10_001_0000_0100_000);
+ /// Counter Control Register 0
+ pub const TRCCNTCTLR0: Self = Self::System(0b10_001_0000_0100_101);
+ /// ID Register 12
+ pub const TRCIDR12: Self = Self::System(0b10_001_0000_0100_110);
+ /// IMP DEF Register 4
+ pub const TRCIMSPEC4: Self = Self::System(0b10_001_0000_0100_111);
+ /// Counter Control Register 1
+ pub const TRCCNTCTLR1: Self = Self::System(0b10_001_0000_0101_101);
+ /// ID Register 13
+ pub const TRCIDR13: Self = Self::System(0b10_001_0000_0101_110);
+ /// IMP DEF Register 5
+ pub const TRCIMSPEC5: Self = Self::System(0b10_001_0000_0101_111);
+ /// Auxiliary Control Register
+ pub const TRCAUXCTLR: Self = Self::System(0b10_001_0000_0110_000);
+ /// Sequencer Reset Control Register
+ pub const TRCSEQRSTEVR: Self = Self::System(0b10_001_0000_0110_100);
+ /// Counter Control Register 2
+ pub const TRCCNTCTLR2: Self = Self::System(0b10_001_0000_0110_101);
+ /// IMP DEF Register 6
+ pub const TRCIMSPEC6: Self = Self::System(0b10_001_0000_0110_111);
+ /// Sequencer State Register
+ pub const TRCSEQSTR: Self = Self::System(0b10_001_0000_0111_100);
+ /// Counter Control Register 3
+ pub const TRCCNTCTLR3: Self = Self::System(0b10_001_0000_0111_101);
+ /// IMP DEF Register 7
+ pub const TRCIMSPEC7: Self = Self::System(0b10_001_0000_0111_111);
+ /// Event Control 0 Register
+ pub const TRCEVENTCTL0R: Self = Self::System(0b10_001_0000_1000_000);
+ /// External Input Select Register 0
+ pub const TRCEXTINSELR0: Self = Self::System(0b10_001_0000_1000_100);
+ /// Counter Value Register 0
+ pub const TRCCNTVR0: Self = Self::System(0b10_001_0000_1000_101);
+ /// ID Register 0
+ pub const TRCIDR0: Self = Self::System(0b10_001_0000_1000_111);
+ /// Event Control 1 Register
+ pub const TRCEVENTCTL1R: Self = Self::System(0b10_001_0000_1001_000);
+ /// External Input Select Register 1
+ pub const TRCEXTINSELR1: Self = Self::System(0b10_001_0000_1001_100);
+ /// Counter Value Register 1
+ pub const TRCCNTVR1: Self = Self::System(0b10_001_0000_1001_101);
+ /// ID Register 1
+ pub const TRCIDR1: Self = Self::System(0b10_001_0000_1001_111);
+ /// Resources Status Register
+ pub const TRCRSR: Self = Self::System(0b10_001_0000_1010_000);
+ /// External Input Select Register 2
+ pub const TRCEXTINSELR2: Self = Self::System(0b10_001_0000_1010_100);
+ /// Counter Value Register 2
+ pub const TRCCNTVR2: Self = Self::System(0b10_001_0000_1010_101);
+ /// ID Register 2
+ pub const TRCIDR2: Self = Self::System(0b10_001_0000_1010_111);
+ /// Stall Control Register
+ pub const TRCSTALLCTLR: Self = Self::System(0b10_001_0000_1011_000);
+ /// External Input Select Register 3
+ pub const TRCEXTINSELR3: Self = Self::System(0b10_001_0000_1011_100);
+ /// Counter Value Register 3
+ pub const TRCCNTVR3: Self = Self::System(0b10_001_0000_1011_101);
+ /// ID Register 3
+ pub const TRCIDR3: Self = Self::System(0b10_001_0000_1011_111);
+ /// Timestamp Control Register
+ pub const TRCTSCTLR: Self = Self::System(0b10_001_0000_1100_000);
+ /// ID Register 4
+ pub const TRCIDR4: Self = Self::System(0b10_001_0000_1100_111);
+ /// Synchronization Period Register
+ pub const TRCSYNCPR: Self = Self::System(0b10_001_0000_1101_000);
+ /// ID Register 5
+ pub const TRCIDR5: Self = Self::System(0b10_001_0000_1101_111);
+ /// Cycle Count Control Register
+ pub const TRCCCCTLR: Self = Self::System(0b10_001_0000_1110_000);
+ /// ID Register 6
+ pub const TRCIDR6: Self = Self::System(0b10_001_0000_1110_111);
+ /// Branch Broadcast Control Register
+ pub const TRCBBCTLR: Self = Self::System(0b10_001_0000_1111_000);
+ /// ID Register 7
+ pub const TRCIDR7: Self = Self::System(0b10_001_0000_1111_111);
+ /// Resource Selection Control Register 16
+ pub const TRCRSCTLR16: Self = Self::System(0b10_001_0001_0000_001);
+ /// Single-shot Comparator Control Register 0
+ pub const TRCSSCCR0: Self = Self::System(0b10_001_0001_0000_010);
+ /// Single-shot Processing Element Comparator Input Control Register 0
+ pub const TRCSSPCICR0: Self = Self::System(0b10_001_0001_0000_011);
+ /// Resource Selection Control Register 17
+ pub const TRCRSCTLR17: Self = Self::System(0b10_001_0001_0001_001);
+ /// Single-shot Comparator Control Register 1
+ pub const TRCSSCCR1: Self = Self::System(0b10_001_0001_0001_010);
+ /// Single-shot Processing Element Comparator Input Control Register 1
+ pub const TRCSSPCICR1: Self = Self::System(0b10_001_0001_0001_011);
+ /// Trace OS Lock Status Register
+ pub const TRCOSLSR: Self = Self::System(0b10_001_0001_0001_100);
+ /// Resource Selection Control Register 2
+ pub const TRCRSCTLR2: Self = Self::System(0b10_001_0001_0010_000);
+ /// Resource Selection Control Register 18
+ pub const TRCRSCTLR18: Self = Self::System(0b10_001_0001_0010_001);
+ /// Single-shot Comparator Control Register 2
+ pub const TRCSSCCR2: Self = Self::System(0b10_001_0001_0010_010);
+ /// Single-shot Processing Element Comparator Input Control Register 2
+ pub const TRCSSPCICR2: Self = Self::System(0b10_001_0001_0010_011);
+ /// Resource Selection Control Register 3
+ pub const TRCRSCTLR3: Self = Self::System(0b10_001_0001_0011_000);
+ /// Resource Selection Control Register 19
+ pub const TRCRSCTLR19: Self = Self::System(0b10_001_0001_0011_001);
+ /// Single-shot Comparator Control Register 3
+ pub const TRCSSCCR3: Self = Self::System(0b10_001_0001_0011_010);
+ /// Single-shot Processing Element Comparator Input Control Register 3
+ pub const TRCSSPCICR3: Self = Self::System(0b10_001_0001_0011_011);
+ /// Resource Selection Control Register 4
+ pub const TRCRSCTLR4: Self = Self::System(0b10_001_0001_0100_000);
+ /// Resource Selection Control Register 20
+ pub const TRCRSCTLR20: Self = Self::System(0b10_001_0001_0100_001);
+ /// Single-shot Comparator Control Register 4
+ pub const TRCSSCCR4: Self = Self::System(0b10_001_0001_0100_010);
+ /// Single-shot Processing Element Comparator Input Control Register 4
+ pub const TRCSSPCICR4: Self = Self::System(0b10_001_0001_0100_011);
+ /// Resource Selection Control Register 5
+ pub const TRCRSCTLR5: Self = Self::System(0b10_001_0001_0101_000);
+ /// Resource Selection Control Register 21
+ pub const TRCRSCTLR21: Self = Self::System(0b10_001_0001_0101_001);
+ /// Single-shot Comparator Control Register 5
+ pub const TRCSSCCR5: Self = Self::System(0b10_001_0001_0101_010);
+ /// Single-shot Processing Element Comparator Input Control Register 5
+ pub const TRCSSPCICR5: Self = Self::System(0b10_001_0001_0101_011);
+ /// Resource Selection Control Register 6
+ pub const TRCRSCTLR6: Self = Self::System(0b10_001_0001_0110_000);
+ /// Resource Selection Control Register 22
+ pub const TRCRSCTLR22: Self = Self::System(0b10_001_0001_0110_001);
+ /// Single-shot Comparator Control Register 6
+ pub const TRCSSCCR6: Self = Self::System(0b10_001_0001_0110_010);
+ /// Single-shot Processing Element Comparator Input Control Register 6
+ pub const TRCSSPCICR6: Self = Self::System(0b10_001_0001_0110_011);
+ /// Resource Selection Control Register 7
+ pub const TRCRSCTLR7: Self = Self::System(0b10_001_0001_0111_000);
+ /// Resource Selection Control Register 23
+ pub const TRCRSCTLR23: Self = Self::System(0b10_001_0001_0111_001);
+ /// Single-shot Comparator Control Register 7
+ pub const TRCSSCCR7: Self = Self::System(0b10_001_0001_0111_010);
+ /// Single-shot Processing Element Comparator Input Control Register 7
+ pub const TRCSSPCICR7: Self = Self::System(0b10_001_0001_0111_011);
+ /// Resource Selection Control Register 8
+ pub const TRCRSCTLR8: Self = Self::System(0b10_001_0001_1000_000);
+ /// Resource Selection Control Register 24
+ pub const TRCRSCTLR24: Self = Self::System(0b10_001_0001_1000_001);
+ /// Single-shot Comparator Control Status Register 0
+ pub const TRCSSCSR0: Self = Self::System(0b10_001_0001_1000_010);
+ /// Resource Selection Control Register 9
+ pub const TRCRSCTLR9: Self = Self::System(0b10_001_0001_1001_000);
+ /// Resource Selection Control Register 25
+ pub const TRCRSCTLR25: Self = Self::System(0b10_001_0001_1001_001);
+ /// Single-shot Comparator Control Status Register 1
+ pub const TRCSSCSR1: Self = Self::System(0b10_001_0001_1001_010);
+ /// Resource Selection Control Register 10
+ pub const TRCRSCTLR10: Self = Self::System(0b10_001_0001_1010_000);
+ /// Resource Selection Control Register 26
+ pub const TRCRSCTLR26: Self = Self::System(0b10_001_0001_1010_001);
+ /// Single-shot Comparator Control Status Register 2
+ pub const TRCSSCSR2: Self = Self::System(0b10_001_0001_1010_010);
+ /// Resource Selection Control Register 11
+ pub const TRCRSCTLR11: Self = Self::System(0b10_001_0001_1011_000);
+ /// Resource Selection Control Register 27
+ pub const TRCRSCTLR27: Self = Self::System(0b10_001_0001_1011_001);
+ /// Single-shot Comparator Control Status Register 3
+ pub const TRCSSCSR3: Self = Self::System(0b10_001_0001_1011_010);
+ /// Resource Selection Control Register 12
+ pub const TRCRSCTLR12: Self = Self::System(0b10_001_0001_1100_000);
+ /// Resource Selection Control Register 28
+ pub const TRCRSCTLR28: Self = Self::System(0b10_001_0001_1100_001);
+ /// Single-shot Comparator Control Status Register 4
+ pub const TRCSSCSR4: Self = Self::System(0b10_001_0001_1100_010);
+ /// Resource Selection Control Register 13
+ pub const TRCRSCTLR13: Self = Self::System(0b10_001_0001_1101_000);
+ /// Resource Selection Control Register 29
+ pub const TRCRSCTLR29: Self = Self::System(0b10_001_0001_1101_001);
+ /// Single-shot Comparator Control Status Register 5
+ pub const TRCSSCSR5: Self = Self::System(0b10_001_0001_1101_010);
+ /// Resource Selection Control Register 14
+ pub const TRCRSCTLR14: Self = Self::System(0b10_001_0001_1110_000);
+ /// Resource Selection Control Register 30
+ pub const TRCRSCTLR30: Self = Self::System(0b10_001_0001_1110_001);
+ /// Single-shot Comparator Control Status Register 6
+ pub const TRCSSCSR6: Self = Self::System(0b10_001_0001_1110_010);
+ /// Resource Selection Control Register 15
+ pub const TRCRSCTLR15: Self = Self::System(0b10_001_0001_1111_000);
+ /// Resource Selection Control Register 31
+ pub const TRCRSCTLR31: Self = Self::System(0b10_001_0001_1111_001);
+ /// Single-shot Comparator Control Status Register 7
+ pub const TRCSSCSR7: Self = Self::System(0b10_001_0001_1111_010);
+ /// Address Comparator Value Register 0
+ pub const TRCACVR0: Self = Self::System(0b10_001_0010_0000_000);
+ /// Address Comparator Value Register 8
+ pub const TRCACVR8: Self = Self::System(0b10_001_0010_0000_001);
+ /// Address Comparator Access Type Register 0
+ pub const TRCACATR0: Self = Self::System(0b10_001_0010_0000_010);
+ /// Address Comparator Access Type Register 8
+ pub const TRCACATR8: Self = Self::System(0b10_001_0010_0000_011);
+ /// Address Comparator Value Register 1
+ pub const TRCACVR1: Self = Self::System(0b10_001_0010_0010_000);
+ /// Address Comparator Value Register 9
+ pub const TRCACVR9: Self = Self::System(0b10_001_0010_0010_001);
+ /// Address Comparator Access Type Register 1
+ pub const TRCACATR1: Self = Self::System(0b10_001_0010_0010_010);
+ /// Address Comparator Access Type Register 9
+ pub const TRCACATR9: Self = Self::System(0b10_001_0010_0010_011);
+ /// Address Comparator Value Register 2
+ pub const TRCACVR2: Self = Self::System(0b10_001_0010_0100_000);
+ /// Address Comparator Value Register 10
+ pub const TRCACVR10: Self = Self::System(0b10_001_0010_0100_001);
+ /// Address Comparator Access Type Register 2
+ pub const TRCACATR2: Self = Self::System(0b10_001_0010_0100_010);
+ /// Address Comparator Access Type Register 10
+ pub const TRCACATR10: Self = Self::System(0b10_001_0010_0100_011);
+ /// Address Comparator Value Register 3
+ pub const TRCACVR3: Self = Self::System(0b10_001_0010_0110_000);
+ /// Address Comparator Value Register 11
+ pub const TRCACVR11: Self = Self::System(0b10_001_0010_0110_001);
+ /// Address Comparator Access Type Register 3
+ pub const TRCACATR3: Self = Self::System(0b10_001_0010_0110_010);
+ /// Address Comparator Access Type Register 11
+ pub const TRCACATR11: Self = Self::System(0b10_001_0010_0110_011);
+ /// Address Comparator Value Register 4
+ pub const TRCACVR4: Self = Self::System(0b10_001_0010_1000_000);
+ /// Address Comparator Value Register 12
+ pub const TRCACVR12: Self = Self::System(0b10_001_0010_1000_001);
+ /// Address Comparator Access Type Register 4
+ pub const TRCACATR4: Self = Self::System(0b10_001_0010_1000_010);
+ /// Address Comparator Access Type Register 12
+ pub const TRCACATR12: Self = Self::System(0b10_001_0010_1000_011);
+ /// Address Comparator Value Register 5
+ pub const TRCACVR5: Self = Self::System(0b10_001_0010_1010_000);
+ /// Address Comparator Value Register 13
+ pub const TRCACVR13: Self = Self::System(0b10_001_0010_1010_001);
+ /// Address Comparator Access Type Register 5
+ pub const TRCACATR5: Self = Self::System(0b10_001_0010_1010_010);
+ /// Address Comparator Access Type Register 13
+ pub const TRCACATR13: Self = Self::System(0b10_001_0010_1010_011);
+ /// Address Comparator Value Register 6
+ pub const TRCACVR6: Self = Self::System(0b10_001_0010_1100_000);
+ /// Address Comparator Value Register 14
+ pub const TRCACVR14: Self = Self::System(0b10_001_0010_1100_001);
+ /// Address Comparator Access Type Register 6
+ pub const TRCACATR6: Self = Self::System(0b10_001_0010_1100_010);
+ /// Address Comparator Access Type Register 14
+ pub const TRCACATR14: Self = Self::System(0b10_001_0010_1100_011);
+ /// Address Comparator Value Register 7
+ pub const TRCACVR7: Self = Self::System(0b10_001_0010_1110_000);
+ /// Address Comparator Value Register 15
+ pub const TRCACVR15: Self = Self::System(0b10_001_0010_1110_001);
+ /// Address Comparator Access Type Register 7
+ pub const TRCACATR7: Self = Self::System(0b10_001_0010_1110_010);
+ /// Address Comparator Access Type Register 15
+ pub const TRCACATR15: Self = Self::System(0b10_001_0010_1110_011);
+ /// Context Identifier Comparator Value Registers 0
+ pub const TRCCIDCVR0: Self = Self::System(0b10_001_0011_0000_000);
+ /// Virtual Context Identifier Comparator Value Register 0
+ pub const TRCVMIDCVR0: Self = Self::System(0b10_001_0011_0000_001);
+ /// Context Identifier Comparator Control Register 0
+ pub const TRCCIDCCTLR0: Self = Self::System(0b10_001_0011_0000_010);
+ /// Context Identifier Comparator Control Register 1
+ pub const TRCCIDCCTLR1: Self = Self::System(0b10_001_0011_0001_010);
+ /// Context Identifier Comparator Value Registers 1
+ pub const TRCCIDCVR1: Self = Self::System(0b10_001_0011_0010_000);
+ /// Virtual Context Identifier Comparator Value Register 1
+ pub const TRCVMIDCVR1: Self = Self::System(0b10_001_0011_0010_001);
+ /// Virtual Context Identifier Comparator Control Register 0
+ pub const TRCVMIDCCTLR0: Self = Self::System(0b10_001_0011_0010_010);
+ /// Virtual Context Identifier Comparator Control Register 1
+ pub const TRCVMIDCCTLR1: Self = Self::System(0b10_001_0011_0011_010);
+ /// Context Identifier Comparator Value Registers 2
+ pub const TRCCIDCVR2: Self = Self::System(0b10_001_0011_0100_000);
+ /// Virtual Context Identifier Comparator Value Register 2
+ pub const TRCVMIDCVR2: Self = Self::System(0b10_001_0011_0100_001);
+ /// Context Identifier Comparator Value Registers 3
+ pub const TRCCIDCVR3: Self = Self::System(0b10_001_0011_0110_000);
+ /// Virtual Context Identifier Comparator Value Register 3
+ pub const TRCVMIDCVR3: Self = Self::System(0b10_001_0011_0110_001);
+ /// Context Identifier Comparator Value Registers 4
+ pub const TRCCIDCVR4: Self = Self::System(0b10_001_0011_1000_000);
+ /// Virtual Context Identifier Comparator Value Register 4
+ pub const TRCVMIDCVR4: Self = Self::System(0b10_001_0011_1000_001);
+ /// Context Identifier Comparator Value Registers 5
+ pub const TRCCIDCVR5: Self = Self::System(0b10_001_0011_1010_000);
+ /// Virtual Context Identifier Comparator Value Register 5
+ pub const TRCVMIDCVR5: Self = Self::System(0b10_001_0011_1010_001);
+ /// Context Identifier Comparator Value Registers 6
+ pub const TRCCIDCVR6: Self = Self::System(0b10_001_0011_1100_000);
+ /// Virtual Context Identifier Comparator Value Register 6
+ pub const TRCVMIDCVR6: Self = Self::System(0b10_001_0011_1100_001);
+ /// Context Identifier Comparator Value Registers 7
+ pub const TRCCIDCVR7: Self = Self::System(0b10_001_0011_1110_000);
+ /// Virtual Context Identifier Comparator Value Register 7
+ pub const TRCVMIDCVR7: Self = Self::System(0b10_001_0011_1110_001);
+ /// Device Configuration Register
+ pub const TRCDEVID: Self = Self::System(0b10_001_0111_0010_111);
+ /// Claim Tag Set Register
+ pub const TRCCLAIMSET: Self = Self::System(0b10_001_0111_1000_110);
+ /// Claim Tag Clear Register
+ pub const TRCCLAIMCLR: Self = Self::System(0b10_001_0111_1001_110);
+ /// Authentication Status Register
+ pub const TRCAUTHSTATUS: Self = Self::System(0b10_001_0111_1110_110);
+ /// Device Architecture Register
+ pub const TRCDEVARCH: Self = Self::System(0b10_001_0111_1111_110);
+ /// Branch Record Buffer Information Register 0
+ pub const BRBINF0_EL1: Self = Self::System(0b10_001_1000_0000_000);
+ /// Branch Record Buffer Source Address Register 0
+ pub const BRBSRC0_EL1: Self = Self::System(0b10_001_1000_0000_001);
+ /// Branch Record Buffer Target Address Register 0
+ pub const BRBTGT0_EL1: Self = Self::System(0b10_001_1000_0000_010);
+ /// Branch Record Buffer Information Register 16
+ pub const BRBINF16_EL1: Self = Self::System(0b10_001_1000_0000_100);
+ /// Branch Record Buffer Source Address Register 16
+ pub const BRBSRC16_EL1: Self = Self::System(0b10_001_1000_0000_101);
+ /// Branch Record Buffer Target Address Register 16
+ pub const BRBTGT16_EL1: Self = Self::System(0b10_001_1000_0000_110);
+ /// Branch Record Buffer Information Register 1
+ pub const BRBINF1_EL1: Self = Self::System(0b10_001_1000_0001_000);
+ /// Branch Record Buffer Source Address Register 1
+ pub const BRBSRC1_EL1: Self = Self::System(0b10_001_1000_0001_001);
+ /// Branch Record Buffer Target Address Register 1
+ pub const BRBTGT1_EL1: Self = Self::System(0b10_001_1000_0001_010);
+ /// Branch Record Buffer Information Register 17
+ pub const BRBINF17_EL1: Self = Self::System(0b10_001_1000_0001_100);
+ /// Branch Record Buffer Source Address Register 17
+ pub const BRBSRC17_EL1: Self = Self::System(0b10_001_1000_0001_101);
+ /// Branch Record Buffer Target Address Register 17
+ pub const BRBTGT17_EL1: Self = Self::System(0b10_001_1000_0001_110);
+ /// Branch Record Buffer Information Register 2
+ pub const BRBINF2_EL1: Self = Self::System(0b10_001_1000_0010_000);
+ /// Branch Record Buffer Source Address Register 2
+ pub const BRBSRC2_EL1: Self = Self::System(0b10_001_1000_0010_001);
+ /// Branch Record Buffer Target Address Register 2
+ pub const BRBTGT2_EL1: Self = Self::System(0b10_001_1000_0010_010);
+ /// Branch Record Buffer Information Register 18
+ pub const BRBINF18_EL1: Self = Self::System(0b10_001_1000_0010_100);
+ /// Branch Record Buffer Source Address Register 18
+ pub const BRBSRC18_EL1: Self = Self::System(0b10_001_1000_0010_101);
+ /// Branch Record Buffer Target Address Register 18
+ pub const BRBTGT18_EL1: Self = Self::System(0b10_001_1000_0010_110);
+ /// Branch Record Buffer Information Register 3
+ pub const BRBINF3_EL1: Self = Self::System(0b10_001_1000_0011_000);
+ /// Branch Record Buffer Source Address Register 3
+ pub const BRBSRC3_EL1: Self = Self::System(0b10_001_1000_0011_001);
+ /// Branch Record Buffer Target Address Register 3
+ pub const BRBTGT3_EL1: Self = Self::System(0b10_001_1000_0011_010);
+ /// Branch Record Buffer Information Register 19
+ pub const BRBINF19_EL1: Self = Self::System(0b10_001_1000_0011_100);
+ /// Branch Record Buffer Source Address Register 19
+ pub const BRBSRC19_EL1: Self = Self::System(0b10_001_1000_0011_101);
+ /// Branch Record Buffer Target Address Register 19
+ pub const BRBTGT19_EL1: Self = Self::System(0b10_001_1000_0011_110);
+ /// Branch Record Buffer Information Register 4
+ pub const BRBINF4_EL1: Self = Self::System(0b10_001_1000_0100_000);
+ /// Branch Record Buffer Source Address Register 4
+ pub const BRBSRC4_EL1: Self = Self::System(0b10_001_1000_0100_001);
+ /// Branch Record Buffer Target Address Register 4
+ pub const BRBTGT4_EL1: Self = Self::System(0b10_001_1000_0100_010);
+ /// Branch Record Buffer Information Register 20
+ pub const BRBINF20_EL1: Self = Self::System(0b10_001_1000_0100_100);
+ /// Branch Record Buffer Source Address Register 20
+ pub const BRBSRC20_EL1: Self = Self::System(0b10_001_1000_0100_101);
+ /// Branch Record Buffer Target Address Register 20
+ pub const BRBTGT20_EL1: Self = Self::System(0b10_001_1000_0100_110);
+ /// Branch Record Buffer Information Register 5
+ pub const BRBINF5_EL1: Self = Self::System(0b10_001_1000_0101_000);
+ /// Branch Record Buffer Source Address Register 5
+ pub const BRBSRC5_EL1: Self = Self::System(0b10_001_1000_0101_001);
+ /// Branch Record Buffer Target Address Register 5
+ pub const BRBTGT5_EL1: Self = Self::System(0b10_001_1000_0101_010);
+ /// Branch Record Buffer Information Register 21
+ pub const BRBINF21_EL1: Self = Self::System(0b10_001_1000_0101_100);
+ /// Branch Record Buffer Source Address Register 21
+ pub const BRBSRC21_EL1: Self = Self::System(0b10_001_1000_0101_101);
+ /// Branch Record Buffer Target Address Register 21
+ pub const BRBTGT21_EL1: Self = Self::System(0b10_001_1000_0101_110);
+ /// Branch Record Buffer Information Register 6
+ pub const BRBINF6_EL1: Self = Self::System(0b10_001_1000_0110_000);
+ /// Branch Record Buffer Source Address Register 6
+ pub const BRBSRC6_EL1: Self = Self::System(0b10_001_1000_0110_001);
+ /// Branch Record Buffer Target Address Register 6
+ pub const BRBTGT6_EL1: Self = Self::System(0b10_001_1000_0110_010);
+ /// Branch Record Buffer Information Register 22
+ pub const BRBINF22_EL1: Self = Self::System(0b10_001_1000_0110_100);
+ /// Branch Record Buffer Source Address Register 22
+ pub const BRBSRC22_EL1: Self = Self::System(0b10_001_1000_0110_101);
+ /// Branch Record Buffer Target Address Register 22
+ pub const BRBTGT22_EL1: Self = Self::System(0b10_001_1000_0110_110);
+ /// Branch Record Buffer Information Register 7
+ pub const BRBINF7_EL1: Self = Self::System(0b10_001_1000_0111_000);
+ /// Branch Record Buffer Source Address Register 7
+ pub const BRBSRC7_EL1: Self = Self::System(0b10_001_1000_0111_001);
+ /// Branch Record Buffer Target Address Register 7
+ pub const BRBTGT7_EL1: Self = Self::System(0b10_001_1000_0111_010);
+ /// Branch Record Buffer Information Register 23
+ pub const BRBINF23_EL1: Self = Self::System(0b10_001_1000_0111_100);
+ /// Branch Record Buffer Source Address Register 23
+ pub const BRBSRC23_EL1: Self = Self::System(0b10_001_1000_0111_101);
+ /// Branch Record Buffer Target Address Register 23
+ pub const BRBTGT23_EL1: Self = Self::System(0b10_001_1000_0111_110);
+ /// Branch Record Buffer Information Register 8
+ pub const BRBINF8_EL1: Self = Self::System(0b10_001_1000_1000_000);
+ /// Branch Record Buffer Source Address Register 8
+ pub const BRBSRC8_EL1: Self = Self::System(0b10_001_1000_1000_001);
+ /// Branch Record Buffer Target Address Register 8
+ pub const BRBTGT8_EL1: Self = Self::System(0b10_001_1000_1000_010);
+ /// Branch Record Buffer Information Register 24
+ pub const BRBINF24_EL1: Self = Self::System(0b10_001_1000_1000_100);
+ /// Branch Record Buffer Source Address Register 24
+ pub const BRBSRC24_EL1: Self = Self::System(0b10_001_1000_1000_101);
+ /// Branch Record Buffer Target Address Register 24
+ pub const BRBTGT24_EL1: Self = Self::System(0b10_001_1000_1000_110);
+ /// Branch Record Buffer Information Register 9
+ pub const BRBINF9_EL1: Self = Self::System(0b10_001_1000_1001_000);
+ /// Branch Record Buffer Source Address Register 9
+ pub const BRBSRC9_EL1: Self = Self::System(0b10_001_1000_1001_001);
+ /// Branch Record Buffer Target Address Register 9
+ pub const BRBTGT9_EL1: Self = Self::System(0b10_001_1000_1001_010);
+ /// Branch Record Buffer Information Register 25
+ pub const BRBINF25_EL1: Self = Self::System(0b10_001_1000_1001_100);
+ /// Branch Record Buffer Source Address Register 25
+ pub const BRBSRC25_EL1: Self = Self::System(0b10_001_1000_1001_101);
+ /// Branch Record Buffer Target Address Register 25
+ pub const BRBTGT25_EL1: Self = Self::System(0b10_001_1000_1001_110);
+ /// Branch Record Buffer Information Register 10
+ pub const BRBINF10_EL1: Self = Self::System(0b10_001_1000_1010_000);
+ /// Branch Record Buffer Source Address Register 10
+ pub const BRBSRC10_EL1: Self = Self::System(0b10_001_1000_1010_001);
+ /// Branch Record Buffer Target Address Register 10
+ pub const BRBTGT10_EL1: Self = Self::System(0b10_001_1000_1010_010);
+ /// Branch Record Buffer Information Register 26
+ pub const BRBINF26_EL1: Self = Self::System(0b10_001_1000_1010_100);
+ /// Branch Record Buffer Source Address Register 26
+ pub const BRBSRC26_EL1: Self = Self::System(0b10_001_1000_1010_101);
+ /// Branch Record Buffer Target Address Register 26
+ pub const BRBTGT26_EL1: Self = Self::System(0b10_001_1000_1010_110);
+ /// Branch Record Buffer Information Register 11
+ pub const BRBINF11_EL1: Self = Self::System(0b10_001_1000_1011_000);
+ /// Branch Record Buffer Source Address Register 11
+ pub const BRBSRC11_EL1: Self = Self::System(0b10_001_1000_1011_001);
+ /// Branch Record Buffer Target Address Register 11
+ pub const BRBTGT11_EL1: Self = Self::System(0b10_001_1000_1011_010);
+ /// Branch Record Buffer Information Register 27
+ pub const BRBINF27_EL1: Self = Self::System(0b10_001_1000_1011_100);
+ /// Branch Record Buffer Source Address Register 27
+ pub const BRBSRC27_EL1: Self = Self::System(0b10_001_1000_1011_101);
+ /// Branch Record Buffer Target Address Register 27
+ pub const BRBTGT27_EL1: Self = Self::System(0b10_001_1000_1011_110);
+ /// Branch Record Buffer Information Register 12
+ pub const BRBINF12_EL1: Self = Self::System(0b10_001_1000_1100_000);
+ /// Branch Record Buffer Source Address Register 12
+ pub const BRBSRC12_EL1: Self = Self::System(0b10_001_1000_1100_001);
+ /// Branch Record Buffer Target Address Register 12
+ pub const BRBTGT12_EL1: Self = Self::System(0b10_001_1000_1100_010);
+ /// Branch Record Buffer Information Register 28
+ pub const BRBINF28_EL1: Self = Self::System(0b10_001_1000_1100_100);
+ /// Branch Record Buffer Source Address Register 28
+ pub const BRBSRC28_EL1: Self = Self::System(0b10_001_1000_1100_101);
+ /// Branch Record Buffer Target Address Register 28
+ pub const BRBTGT28_EL1: Self = Self::System(0b10_001_1000_1100_110);
+ /// Branch Record Buffer Information Register 13
+ pub const BRBINF13_EL1: Self = Self::System(0b10_001_1000_1101_000);
+ /// Branch Record Buffer Source Address Register 13
+ pub const BRBSRC13_EL1: Self = Self::System(0b10_001_1000_1101_001);
+ /// Branch Record Buffer Target Address Register 13
+ pub const BRBTGT13_EL1: Self = Self::System(0b10_001_1000_1101_010);
+ /// Branch Record Buffer Information Register 29
+ pub const BRBINF29_EL1: Self = Self::System(0b10_001_1000_1101_100);
+ /// Branch Record Buffer Source Address Register 29
+ pub const BRBSRC29_EL1: Self = Self::System(0b10_001_1000_1101_101);
+ /// Branch Record Buffer Target Address Register 29
+ pub const BRBTGT29_EL1: Self = Self::System(0b10_001_1000_1101_110);
+ /// Branch Record Buffer Information Register 14
+ pub const BRBINF14_EL1: Self = Self::System(0b10_001_1000_1110_000);
+ /// Branch Record Buffer Source Address Register 14
+ pub const BRBSRC14_EL1: Self = Self::System(0b10_001_1000_1110_001);
+ /// Branch Record Buffer Target Address Register 14
+ pub const BRBTGT14_EL1: Self = Self::System(0b10_001_1000_1110_010);
+ /// Branch Record Buffer Information Register 30
+ pub const BRBINF30_EL1: Self = Self::System(0b10_001_1000_1110_100);
+ /// Branch Record Buffer Source Address Register 30
+ pub const BRBSRC30_EL1: Self = Self::System(0b10_001_1000_1110_101);
+ /// Branch Record Buffer Target Address Register 30
+ pub const BRBTGT30_EL1: Self = Self::System(0b10_001_1000_1110_110);
+ /// Branch Record Buffer Information Register 15
+ pub const BRBINF15_EL1: Self = Self::System(0b10_001_1000_1111_000);
+ /// Branch Record Buffer Source Address Register 15
+ pub const BRBSRC15_EL1: Self = Self::System(0b10_001_1000_1111_001);
+ /// Branch Record Buffer Target Address Register 15
+ pub const BRBTGT15_EL1: Self = Self::System(0b10_001_1000_1111_010);
+ /// Branch Record Buffer Information Register 31
+ pub const BRBINF31_EL1: Self = Self::System(0b10_001_1000_1111_100);
+ /// Branch Record Buffer Source Address Register 31
+ pub const BRBSRC31_EL1: Self = Self::System(0b10_001_1000_1111_101);
+ /// Branch Record Buffer Target Address Register 31
+ pub const BRBTGT31_EL1: Self = Self::System(0b10_001_1000_1111_110);
+ /// Branch Record Buffer Control Register (EL1)
+ pub const BRBCR_EL1: Self = Self::System(0b10_001_1001_0000_000);
+ /// Branch Record Buffer Control Register (EL2)
+ pub const BRBCR_EL2: Self = Self::System(0b10_001_1001_0000_000);
+ /// Branch Record Buffer Function Control Register
+ pub const BRBFCR_EL1: Self = Self::System(0b10_001_1001_0000_001);
+ /// Branch Record Buffer Timestamp Register
+ pub const BRBTS_EL1: Self = Self::System(0b10_001_1001_0000_010);
+ /// Branch Record Buffer Information Injection Register
+ pub const BRBINFINJ_EL1: Self = Self::System(0b10_001_1001_0001_000);
+ /// Branch Record Buffer Source Address Injection Register
+ pub const BRBSRCINJ_EL1: Self = Self::System(0b10_001_1001_0001_001);
+ /// Branch Record Buffer Target Address Injection Register
+ pub const BRBTGTINJ_EL1: Self = Self::System(0b10_001_1001_0001_010);
+ /// Branch Record Buffer ID0 Register
+ pub const BRBIDR0_EL1: Self = Self::System(0b10_001_1001_0010_000);
+ /// Monitor DCC Status Register
+ pub const MDCCSR_EL0: Self = Self::System(0b10_011_0000_0001_000);
+ /// Debug Data Transfer Register, Half-duplex
+ pub const DBGDTR_EL0: Self = Self::System(0b10_011_0000_0100_000);
+ /// Debug Data Transfer Register, Receive
+ pub const DBGDTRRX_EL0: Self = Self::System(0b10_011_0000_0101_000);
+ /// Debug Data Transfer Register, Transmit
+ pub const DBGDTRTX_EL0: Self = Self::System(0b10_011_0000_0101_000);
+ /// Debug Vector Catch Register
+ pub const DBGVCR32_EL2: Self = Self::System(0b10_100_0000_0111_000);
+}
diff --git a/src/aarch64/reg/mod.rs b/src/aarch64/reg/mod.rs
new file mode 100644
index 0000000..8fe3600
--- /dev/null
+++ b/src/aarch64/reg/mod.rs
@@ -0,0 +1,8 @@
+//! `Register` structs for the AArch64 ARM architecture.
+
+/// `RegId` definitions for the ARM AArch64 Architecture.
+pub mod id;
+
+mod aarch64_core;
+
+pub use aarch64_core::AArch64CoreRegs;
diff --git a/src/aarch64/sysregs.xml b/src/aarch64/sysregs.xml
new file mode 100644
index 0000000..bd643ee
--- /dev/null
+++ b/src/aarch64/sysregs.xml
@@ -0,0 +1,878 @@
+<feature name="org.rust.gdb.arm.sys.regs">
+
+ <!-- Generated from the XML description of ARMv8-A system registers, provided
+ by ARM at https://developer.arm.com/downloads/-/exploration-tools -->
+
+ <reg name="OSDTRRX_EL1" bitsize="64" regnum="32770" group="system"/>
+ <reg name="DBGBVR0_EL1" bitsize="64" regnum="32772" group="system"/>
+ <reg name="DBGBCR0_EL1" bitsize="64" regnum="32773" group="system"/>
+ <reg name="DBGWVR0_EL1" bitsize="64" regnum="32774" group="system"/>
+ <reg name="DBGWCR0_EL1" bitsize="64" regnum="32775" group="system"/>
+ <reg name="DBGBVR1_EL1" bitsize="64" regnum="32780" group="system"/>
+ <reg name="DBGBCR1_EL1" bitsize="64" regnum="32781" group="system"/>
+ <reg name="DBGWVR1_EL1" bitsize="64" regnum="32782" group="system"/>
+ <reg name="DBGWCR1_EL1" bitsize="64" regnum="32783" group="system"/>
+ <reg name="MDCCINT_EL1" bitsize="64" regnum="32784" group="system"/>
+ <reg name="MDSCR_EL1" bitsize="64" regnum="32786" group="system"/>
+ <reg name="DBGBVR2_EL1" bitsize="64" regnum="32788" group="system"/>
+ <reg name="DBGBCR2_EL1" bitsize="64" regnum="32789" group="system"/>
+ <reg name="DBGWVR2_EL1" bitsize="64" regnum="32790" group="system"/>
+ <reg name="DBGWCR2_EL1" bitsize="64" regnum="32791" group="system"/>
+ <reg name="OSDTRTX_EL1" bitsize="64" regnum="32794" group="system"/>
+ <reg name="DBGBVR3_EL1" bitsize="64" regnum="32796" group="system"/>
+ <reg name="DBGBCR3_EL1" bitsize="64" regnum="32797" group="system"/>
+ <reg name="DBGWVR3_EL1" bitsize="64" regnum="32798" group="system"/>
+ <reg name="DBGWCR3_EL1" bitsize="64" regnum="32799" group="system"/>
+ <reg name="DBGBVR4_EL1" bitsize="64" regnum="32804" group="system"/>
+ <reg name="DBGBCR4_EL1" bitsize="64" regnum="32805" group="system"/>
+ <reg name="DBGWVR4_EL1" bitsize="64" regnum="32806" group="system"/>
+ <reg name="DBGWCR4_EL1" bitsize="64" regnum="32807" group="system"/>
+ <reg name="DBGBVR5_EL1" bitsize="64" regnum="32812" group="system"/>
+ <reg name="DBGBCR5_EL1" bitsize="64" regnum="32813" group="system"/>
+ <reg name="DBGWVR5_EL1" bitsize="64" regnum="32814" group="system"/>
+ <reg name="DBGWCR5_EL1" bitsize="64" regnum="32815" group="system"/>
+ <reg name="OSECCR_EL1" bitsize="64" regnum="32818" group="system"/>
+ <reg name="DBGBVR6_EL1" bitsize="64" regnum="32820" group="system"/>
+ <reg name="DBGBCR6_EL1" bitsize="64" regnum="32821" group="system"/>
+ <reg name="DBGWVR6_EL1" bitsize="64" regnum="32822" group="system"/>
+ <reg name="DBGWCR6_EL1" bitsize="64" regnum="32823" group="system"/>
+ <reg name="DBGBVR7_EL1" bitsize="64" regnum="32828" group="system"/>
+ <reg name="DBGBCR7_EL1" bitsize="64" regnum="32829" group="system"/>
+ <reg name="DBGWVR7_EL1" bitsize="64" regnum="32830" group="system"/>
+ <reg name="DBGWCR7_EL1" bitsize="64" regnum="32831" group="system"/>
+ <reg name="DBGBVR8_EL1" bitsize="64" regnum="32836" group="system"/>
+ <reg name="DBGBCR8_EL1" bitsize="64" regnum="32837" group="system"/>
+ <reg name="DBGWVR8_EL1" bitsize="64" regnum="32838" group="system"/>
+ <reg name="DBGWCR8_EL1" bitsize="64" regnum="32839" group="system"/>
+ <reg name="DBGBVR9_EL1" bitsize="64" regnum="32844" group="system"/>
+ <reg name="DBGBCR9_EL1" bitsize="64" regnum="32845" group="system"/>
+ <reg name="DBGWVR9_EL1" bitsize="64" regnum="32846" group="system"/>
+ <reg name="DBGWCR9_EL1" bitsize="64" regnum="32847" group="system"/>
+ <reg name="DBGBVR10_EL1" bitsize="64" regnum="32852" group="system"/>
+ <reg name="DBGBCR10_EL1" bitsize="64" regnum="32853" group="system"/>
+ <reg name="DBGWVR10_EL1" bitsize="64" regnum="32854" group="system"/>
+ <reg name="DBGWCR10_EL1" bitsize="64" regnum="32855" group="system"/>
+ <reg name="DBGBVR11_EL1" bitsize="64" regnum="32860" group="system"/>
+ <reg name="DBGBCR11_EL1" bitsize="64" regnum="32861" group="system"/>
+ <reg name="DBGWVR11_EL1" bitsize="64" regnum="32862" group="system"/>
+ <reg name="DBGWCR11_EL1" bitsize="64" regnum="32863" group="system"/>
+ <reg name="DBGBVR12_EL1" bitsize="64" regnum="32868" group="system"/>
+ <reg name="DBGBCR12_EL1" bitsize="64" regnum="32869" group="system"/>
+ <reg name="DBGWVR12_EL1" bitsize="64" regnum="32870" group="system"/>
+ <reg name="DBGWCR12_EL1" bitsize="64" regnum="32871" group="system"/>
+ <reg name="DBGBVR13_EL1" bitsize="64" regnum="32876" group="system"/>
+ <reg name="DBGBCR13_EL1" bitsize="64" regnum="32877" group="system"/>
+ <reg name="DBGWVR13_EL1" bitsize="64" regnum="32878" group="system"/>
+ <reg name="DBGWCR13_EL1" bitsize="64" regnum="32879" group="system"/>
+ <reg name="DBGBVR14_EL1" bitsize="64" regnum="32884" group="system"/>
+ <reg name="DBGBCR14_EL1" bitsize="64" regnum="32885" group="system"/>
+ <reg name="DBGWVR14_EL1" bitsize="64" regnum="32886" group="system"/>
+ <reg name="DBGWCR14_EL1" bitsize="64" regnum="32887" group="system"/>
+ <reg name="DBGBVR15_EL1" bitsize="64" regnum="32892" group="system"/>
+ <reg name="DBGBCR15_EL1" bitsize="64" regnum="32893" group="system"/>
+ <reg name="DBGWVR15_EL1" bitsize="64" regnum="32894" group="system"/>
+ <reg name="DBGWCR15_EL1" bitsize="64" regnum="32895" group="system"/>
+ <reg name="MDRAR_EL1" bitsize="64" regnum="32896" group="system"/>
+ <reg name="OSLAR_EL1" bitsize="64" regnum="32900" group="system"/>
+ <reg name="OSLSR_EL1" bitsize="64" regnum="32908" group="system"/>
+ <reg name="OSDLR_EL1" bitsize="64" regnum="32924" group="system"/>
+ <reg name="DBGPRCR_EL1" bitsize="64" regnum="32932" group="system"/>
+ <reg name="DBGCLAIMSET_EL1" bitsize="64" regnum="33734" group="system"/>
+ <reg name="DBGCLAIMCLR_EL1" bitsize="64" regnum="33742" group="system"/>
+ <reg name="DBGAUTHSTATUS_EL1" bitsize="64" regnum="33782" group="system"/>
+ <reg name="TRCTRACEIDR" bitsize="64" regnum="34817" group="system"/>
+ <reg name="TRCVICTLR" bitsize="64" regnum="34818" group="system"/>
+ <reg name="TRCSEQEVR0" bitsize="64" regnum="34820" group="system"/>
+ <reg name="TRCCNTRLDVR0" bitsize="64" regnum="34821" group="system"/>
+ <reg name="TRCIDR8" bitsize="64" regnum="34822" group="system"/>
+ <reg name="TRCIMSPEC0" bitsize="64" regnum="34823" group="system"/>
+ <reg name="TRCPRGCTLR" bitsize="64" regnum="34824" group="system"/>
+ <reg name="TRCQCTLR" bitsize="64" regnum="34825" group="system"/>
+ <reg name="TRCVIIECTLR" bitsize="64" regnum="34826" group="system"/>
+ <reg name="TRCSEQEVR1" bitsize="64" regnum="34828" group="system"/>
+ <reg name="TRCCNTRLDVR1" bitsize="64" regnum="34829" group="system"/>
+ <reg name="TRCIDR9" bitsize="64" regnum="34830" group="system"/>
+ <reg name="TRCIMSPEC1" bitsize="64" regnum="34831" group="system"/>
+ <reg name="TRCVISSCTLR" bitsize="64" regnum="34834" group="system"/>
+ <reg name="TRCSEQEVR2" bitsize="64" regnum="34836" group="system"/>
+ <reg name="TRCCNTRLDVR2" bitsize="64" regnum="34837" group="system"/>
+ <reg name="TRCIDR10" bitsize="64" regnum="34838" group="system"/>
+ <reg name="TRCIMSPEC2" bitsize="64" regnum="34839" group="system"/>
+ <reg name="TRCSTATR" bitsize="64" regnum="34840" group="system"/>
+ <reg name="TRCVIPCSSCTLR" bitsize="64" regnum="34842" group="system"/>
+ <reg name="TRCCNTRLDVR3" bitsize="64" regnum="34845" group="system"/>
+ <reg name="TRCIDR11" bitsize="64" regnum="34846" group="system"/>
+ <reg name="TRCIMSPEC3" bitsize="64" regnum="34847" group="system"/>
+ <reg name="TRCCONFIGR" bitsize="64" regnum="34848" group="system"/>
+ <reg name="TRCCNTCTLR0" bitsize="64" regnum="34853" group="system"/>
+ <reg name="TRCIDR12" bitsize="64" regnum="34854" group="system"/>
+ <reg name="TRCIMSPEC4" bitsize="64" regnum="34855" group="system"/>
+ <reg name="TRCCNTCTLR1" bitsize="64" regnum="34861" group="system"/>
+ <reg name="TRCIDR13" bitsize="64" regnum="34862" group="system"/>
+ <reg name="TRCIMSPEC5" bitsize="64" regnum="34863" group="system"/>
+ <reg name="TRCAUXCTLR" bitsize="64" regnum="34864" group="system"/>
+ <reg name="TRCSEQRSTEVR" bitsize="64" regnum="34868" group="system"/>
+ <reg name="TRCCNTCTLR2" bitsize="64" regnum="34869" group="system"/>
+ <reg name="TRCIMSPEC6" bitsize="64" regnum="34871" group="system"/>
+ <reg name="TRCSEQSTR" bitsize="64" regnum="34876" group="system"/>
+ <reg name="TRCCNTCTLR3" bitsize="64" regnum="34877" group="system"/>
+ <reg name="TRCIMSPEC7" bitsize="64" regnum="34879" group="system"/>
+ <reg name="TRCEVENTCTL0R" bitsize="64" regnum="34880" group="system"/>
+ <reg name="TRCEXTINSELR0" bitsize="64" regnum="34884" group="system"/>
+ <reg name="TRCCNTVR0" bitsize="64" regnum="34885" group="system"/>
+ <reg name="TRCIDR0" bitsize="64" regnum="34887" group="system"/>
+ <reg name="TRCEVENTCTL1R" bitsize="64" regnum="34888" group="system"/>
+ <reg name="TRCEXTINSELR1" bitsize="64" regnum="34892" group="system"/>
+ <reg name="TRCCNTVR1" bitsize="64" regnum="34893" group="system"/>
+ <reg name="TRCIDR1" bitsize="64" regnum="34895" group="system"/>
+ <reg name="TRCRSR" bitsize="64" regnum="34896" group="system"/>
+ <reg name="TRCEXTINSELR2" bitsize="64" regnum="34900" group="system"/>
+ <reg name="TRCCNTVR2" bitsize="64" regnum="34901" group="system"/>
+ <reg name="TRCIDR2" bitsize="64" regnum="34903" group="system"/>
+ <reg name="TRCSTALLCTLR" bitsize="64" regnum="34904" group="system"/>
+ <reg name="TRCEXTINSELR3" bitsize="64" regnum="34908" group="system"/>
+ <reg name="TRCCNTVR3" bitsize="64" regnum="34909" group="system"/>
+ <reg name="TRCIDR3" bitsize="64" regnum="34911" group="system"/>
+ <reg name="TRCTSCTLR" bitsize="64" regnum="34912" group="system"/>
+ <reg name="TRCIDR4" bitsize="64" regnum="34919" group="system"/>
+ <reg name="TRCSYNCPR" bitsize="64" regnum="34920" group="system"/>
+ <reg name="TRCIDR5" bitsize="64" regnum="34927" group="system"/>
+ <reg name="TRCCCCTLR" bitsize="64" regnum="34928" group="system"/>
+ <reg name="TRCIDR6" bitsize="64" regnum="34935" group="system"/>
+ <reg name="TRCBBCTLR" bitsize="64" regnum="34936" group="system"/>
+ <reg name="TRCIDR7" bitsize="64" regnum="34943" group="system"/>
+ <reg name="TRCRSCTLR16" bitsize="64" regnum="34945" group="system"/>
+ <reg name="TRCSSCCR0" bitsize="64" regnum="34946" group="system"/>
+ <reg name="TRCSSPCICR0" bitsize="64" regnum="34947" group="system"/>
+ <reg name="TRCRSCTLR17" bitsize="64" regnum="34953" group="system"/>
+ <reg name="TRCSSCCR1" bitsize="64" regnum="34954" group="system"/>
+ <reg name="TRCSSPCICR1" bitsize="64" regnum="34955" group="system"/>
+ <reg name="TRCOSLSR" bitsize="64" regnum="34956" group="system"/>
+ <reg name="TRCRSCTLR2" bitsize="64" regnum="34960" group="system"/>
+ <reg name="TRCRSCTLR18" bitsize="64" regnum="34961" group="system"/>
+ <reg name="TRCSSCCR2" bitsize="64" regnum="34962" group="system"/>
+ <reg name="TRCSSPCICR2" bitsize="64" regnum="34963" group="system"/>
+ <reg name="TRCRSCTLR3" bitsize="64" regnum="34968" group="system"/>
+ <reg name="TRCRSCTLR19" bitsize="64" regnum="34969" group="system"/>
+ <reg name="TRCSSCCR3" bitsize="64" regnum="34970" group="system"/>
+ <reg name="TRCSSPCICR3" bitsize="64" regnum="34971" group="system"/>
+ <reg name="TRCRSCTLR4" bitsize="64" regnum="34976" group="system"/>
+ <reg name="TRCRSCTLR20" bitsize="64" regnum="34977" group="system"/>
+ <reg name="TRCSSCCR4" bitsize="64" regnum="34978" group="system"/>
+ <reg name="TRCSSPCICR4" bitsize="64" regnum="34979" group="system"/>
+ <reg name="TRCRSCTLR5" bitsize="64" regnum="34984" group="system"/>
+ <reg name="TRCRSCTLR21" bitsize="64" regnum="34985" group="system"/>
+ <reg name="TRCSSCCR5" bitsize="64" regnum="34986" group="system"/>
+ <reg name="TRCSSPCICR5" bitsize="64" regnum="34987" group="system"/>
+ <reg name="TRCRSCTLR6" bitsize="64" regnum="34992" group="system"/>
+ <reg name="TRCRSCTLR22" bitsize="64" regnum="34993" group="system"/>
+ <reg name="TRCSSCCR6" bitsize="64" regnum="34994" group="system"/>
+ <reg name="TRCSSPCICR6" bitsize="64" regnum="34995" group="system"/>
+ <reg name="TRCRSCTLR7" bitsize="64" regnum="35000" group="system"/>
+ <reg name="TRCRSCTLR23" bitsize="64" regnum="35001" group="system"/>
+ <reg name="TRCSSCCR7" bitsize="64" regnum="35002" group="system"/>
+ <reg name="TRCSSPCICR7" bitsize="64" regnum="35003" group="system"/>
+ <reg name="TRCRSCTLR8" bitsize="64" regnum="35008" group="system"/>
+ <reg name="TRCRSCTLR24" bitsize="64" regnum="35009" group="system"/>
+ <reg name="TRCSSCSR0" bitsize="64" regnum="35010" group="system"/>
+ <reg name="TRCRSCTLR9" bitsize="64" regnum="35016" group="system"/>
+ <reg name="TRCRSCTLR25" bitsize="64" regnum="35017" group="system"/>
+ <reg name="TRCSSCSR1" bitsize="64" regnum="35018" group="system"/>
+ <reg name="TRCRSCTLR10" bitsize="64" regnum="35024" group="system"/>
+ <reg name="TRCRSCTLR26" bitsize="64" regnum="35025" group="system"/>
+ <reg name="TRCSSCSR2" bitsize="64" regnum="35026" group="system"/>
+ <reg name="TRCRSCTLR11" bitsize="64" regnum="35032" group="system"/>
+ <reg name="TRCRSCTLR27" bitsize="64" regnum="35033" group="system"/>
+ <reg name="TRCSSCSR3" bitsize="64" regnum="35034" group="system"/>
+ <reg name="TRCRSCTLR12" bitsize="64" regnum="35040" group="system"/>
+ <reg name="TRCRSCTLR28" bitsize="64" regnum="35041" group="system"/>
+ <reg name="TRCSSCSR4" bitsize="64" regnum="35042" group="system"/>
+ <reg name="TRCRSCTLR13" bitsize="64" regnum="35048" group="system"/>
+ <reg name="TRCRSCTLR29" bitsize="64" regnum="35049" group="system"/>
+ <reg name="TRCSSCSR5" bitsize="64" regnum="35050" group="system"/>
+ <reg name="TRCRSCTLR14" bitsize="64" regnum="35056" group="system"/>
+ <reg name="TRCRSCTLR30" bitsize="64" regnum="35057" group="system"/>
+ <reg name="TRCSSCSR6" bitsize="64" regnum="35058" group="system"/>
+ <reg name="TRCRSCTLR15" bitsize="64" regnum="35064" group="system"/>
+ <reg name="TRCRSCTLR31" bitsize="64" regnum="35065" group="system"/>
+ <reg name="TRCSSCSR7" bitsize="64" regnum="35066" group="system"/>
+ <reg name="TRCACVR0" bitsize="64" regnum="35072" group="system"/>
+ <reg name="TRCACVR8" bitsize="64" regnum="35073" group="system"/>
+ <reg name="TRCACATR0" bitsize="64" regnum="35074" group="system"/>
+ <reg name="TRCACATR8" bitsize="64" regnum="35075" group="system"/>
+ <reg name="TRCACVR1" bitsize="64" regnum="35088" group="system"/>
+ <reg name="TRCACVR9" bitsize="64" regnum="35089" group="system"/>
+ <reg name="TRCACATR1" bitsize="64" regnum="35090" group="system"/>
+ <reg name="TRCACATR9" bitsize="64" regnum="35091" group="system"/>
+ <reg name="TRCACVR2" bitsize="64" regnum="35104" group="system"/>
+ <reg name="TRCACVR10" bitsize="64" regnum="35105" group="system"/>
+ <reg name="TRCACATR2" bitsize="64" regnum="35106" group="system"/>
+ <reg name="TRCACATR10" bitsize="64" regnum="35107" group="system"/>
+ <reg name="TRCACVR3" bitsize="64" regnum="35120" group="system"/>
+ <reg name="TRCACVR11" bitsize="64" regnum="35121" group="system"/>
+ <reg name="TRCACATR3" bitsize="64" regnum="35122" group="system"/>
+ <reg name="TRCACATR11" bitsize="64" regnum="35123" group="system"/>
+ <reg name="TRCACVR4" bitsize="64" regnum="35136" group="system"/>
+ <reg name="TRCACVR12" bitsize="64" regnum="35137" group="system"/>
+ <reg name="TRCACATR4" bitsize="64" regnum="35138" group="system"/>
+ <reg name="TRCACATR12" bitsize="64" regnum="35139" group="system"/>
+ <reg name="TRCACVR5" bitsize="64" regnum="35152" group="system"/>
+ <reg name="TRCACVR13" bitsize="64" regnum="35153" group="system"/>
+ <reg name="TRCACATR5" bitsize="64" regnum="35154" group="system"/>
+ <reg name="TRCACATR13" bitsize="64" regnum="35155" group="system"/>
+ <reg name="TRCACVR6" bitsize="64" regnum="35168" group="system"/>
+ <reg name="TRCACVR14" bitsize="64" regnum="35169" group="system"/>
+ <reg name="TRCACATR6" bitsize="64" regnum="35170" group="system"/>
+ <reg name="TRCACATR14" bitsize="64" regnum="35171" group="system"/>
+ <reg name="TRCACVR7" bitsize="64" regnum="35184" group="system"/>
+ <reg name="TRCACVR15" bitsize="64" regnum="35185" group="system"/>
+ <reg name="TRCACATR7" bitsize="64" regnum="35186" group="system"/>
+ <reg name="TRCACATR15" bitsize="64" regnum="35187" group="system"/>
+ <reg name="TRCCIDCVR0" bitsize="64" regnum="35200" group="system"/>
+ <reg name="TRCVMIDCVR0" bitsize="64" regnum="35201" group="system"/>
+ <reg name="TRCCIDCCTLR0" bitsize="64" regnum="35202" group="system"/>
+ <reg name="TRCCIDCCTLR1" bitsize="64" regnum="35210" group="system"/>
+ <reg name="TRCCIDCVR1" bitsize="64" regnum="35216" group="system"/>
+ <reg name="TRCVMIDCVR1" bitsize="64" regnum="35217" group="system"/>
+ <reg name="TRCVMIDCCTLR0" bitsize="64" regnum="35218" group="system"/>
+ <reg name="TRCVMIDCCTLR1" bitsize="64" regnum="35226" group="system"/>
+ <reg name="TRCCIDCVR2" bitsize="64" regnum="35232" group="system"/>
+ <reg name="TRCVMIDCVR2" bitsize="64" regnum="35233" group="system"/>
+ <reg name="TRCCIDCVR3" bitsize="64" regnum="35248" group="system"/>
+ <reg name="TRCVMIDCVR3" bitsize="64" regnum="35249" group="system"/>
+ <reg name="TRCCIDCVR4" bitsize="64" regnum="35264" group="system"/>
+ <reg name="TRCVMIDCVR4" bitsize="64" regnum="35265" group="system"/>
+ <reg name="TRCCIDCVR5" bitsize="64" regnum="35280" group="system"/>
+ <reg name="TRCVMIDCVR5" bitsize="64" regnum="35281" group="system"/>
+ <reg name="TRCCIDCVR6" bitsize="64" regnum="35296" group="system"/>
+ <reg name="TRCVMIDCVR6" bitsize="64" regnum="35297" group="system"/>
+ <reg name="TRCCIDCVR7" bitsize="64" regnum="35312" group="system"/>
+ <reg name="TRCVMIDCVR7" bitsize="64" regnum="35313" group="system"/>
+ <reg name="TRCDEVID" bitsize="64" regnum="35735" group="system"/>
+ <reg name="TRCCLAIMSET" bitsize="64" regnum="35782" group="system"/>
+ <reg name="TRCCLAIMCLR" bitsize="64" regnum="35790" group="system"/>
+ <reg name="TRCAUTHSTATUS" bitsize="64" regnum="35830" group="system"/>
+ <reg name="TRCDEVARCH" bitsize="64" regnum="35838" group="system"/>
+ <reg name="BRBINF0_EL1" bitsize="64" regnum="35840" group="system"/>
+ <reg name="BRBSRC0_EL1" bitsize="64" regnum="35841" group="system"/>
+ <reg name="BRBTGT0_EL1" bitsize="64" regnum="35842" group="system"/>
+ <reg name="BRBINF16_EL1" bitsize="64" regnum="35844" group="system"/>
+ <reg name="BRBSRC16_EL1" bitsize="64" regnum="35845" group="system"/>
+ <reg name="BRBTGT16_EL1" bitsize="64" regnum="35846" group="system"/>
+ <reg name="BRBINF1_EL1" bitsize="64" regnum="35848" group="system"/>
+ <reg name="BRBSRC1_EL1" bitsize="64" regnum="35849" group="system"/>
+ <reg name="BRBTGT1_EL1" bitsize="64" regnum="35850" group="system"/>
+ <reg name="BRBINF17_EL1" bitsize="64" regnum="35852" group="system"/>
+ <reg name="BRBSRC17_EL1" bitsize="64" regnum="35853" group="system"/>
+ <reg name="BRBTGT17_EL1" bitsize="64" regnum="35854" group="system"/>
+ <reg name="BRBINF2_EL1" bitsize="64" regnum="35856" group="system"/>
+ <reg name="BRBSRC2_EL1" bitsize="64" regnum="35857" group="system"/>
+ <reg name="BRBTGT2_EL1" bitsize="64" regnum="35858" group="system"/>
+ <reg name="BRBINF18_EL1" bitsize="64" regnum="35860" group="system"/>
+ <reg name="BRBSRC18_EL1" bitsize="64" regnum="35861" group="system"/>
+ <reg name="BRBTGT18_EL1" bitsize="64" regnum="35862" group="system"/>
+ <reg name="BRBINF3_EL1" bitsize="64" regnum="35864" group="system"/>
+ <reg name="BRBSRC3_EL1" bitsize="64" regnum="35865" group="system"/>
+ <reg name="BRBTGT3_EL1" bitsize="64" regnum="35866" group="system"/>
+ <reg name="BRBINF19_EL1" bitsize="64" regnum="35868" group="system"/>
+ <reg name="BRBSRC19_EL1" bitsize="64" regnum="35869" group="system"/>
+ <reg name="BRBTGT19_EL1" bitsize="64" regnum="35870" group="system"/>
+ <reg name="BRBINF4_EL1" bitsize="64" regnum="35872" group="system"/>
+ <reg name="BRBSRC4_EL1" bitsize="64" regnum="35873" group="system"/>
+ <reg name="BRBTGT4_EL1" bitsize="64" regnum="35874" group="system"/>
+ <reg name="BRBINF20_EL1" bitsize="64" regnum="35876" group="system"/>
+ <reg name="BRBSRC20_EL1" bitsize="64" regnum="35877" group="system"/>
+ <reg name="BRBTGT20_EL1" bitsize="64" regnum="35878" group="system"/>
+ <reg name="BRBINF5_EL1" bitsize="64" regnum="35880" group="system"/>
+ <reg name="BRBSRC5_EL1" bitsize="64" regnum="35881" group="system"/>
+ <reg name="BRBTGT5_EL1" bitsize="64" regnum="35882" group="system"/>
+ <reg name="BRBINF21_EL1" bitsize="64" regnum="35884" group="system"/>
+ <reg name="BRBSRC21_EL1" bitsize="64" regnum="35885" group="system"/>
+ <reg name="BRBTGT21_EL1" bitsize="64" regnum="35886" group="system"/>
+ <reg name="BRBINF6_EL1" bitsize="64" regnum="35888" group="system"/>
+ <reg name="BRBSRC6_EL1" bitsize="64" regnum="35889" group="system"/>
+ <reg name="BRBTGT6_EL1" bitsize="64" regnum="35890" group="system"/>
+ <reg name="BRBINF22_EL1" bitsize="64" regnum="35892" group="system"/>
+ <reg name="BRBSRC22_EL1" bitsize="64" regnum="35893" group="system"/>
+ <reg name="BRBTGT22_EL1" bitsize="64" regnum="35894" group="system"/>
+ <reg name="BRBINF7_EL1" bitsize="64" regnum="35896" group="system"/>
+ <reg name="BRBSRC7_EL1" bitsize="64" regnum="35897" group="system"/>
+ <reg name="BRBTGT7_EL1" bitsize="64" regnum="35898" group="system"/>
+ <reg name="BRBINF23_EL1" bitsize="64" regnum="35900" group="system"/>
+ <reg name="BRBSRC23_EL1" bitsize="64" regnum="35901" group="system"/>
+ <reg name="BRBTGT23_EL1" bitsize="64" regnum="35902" group="system"/>
+ <reg name="BRBINF8_EL1" bitsize="64" regnum="35904" group="system"/>
+ <reg name="BRBSRC8_EL1" bitsize="64" regnum="35905" group="system"/>
+ <reg name="BRBTGT8_EL1" bitsize="64" regnum="35906" group="system"/>
+ <reg name="BRBINF24_EL1" bitsize="64" regnum="35908" group="system"/>
+ <reg name="BRBSRC24_EL1" bitsize="64" regnum="35909" group="system"/>
+ <reg name="BRBTGT24_EL1" bitsize="64" regnum="35910" group="system"/>
+ <reg name="BRBINF9_EL1" bitsize="64" regnum="35912" group="system"/>
+ <reg name="BRBSRC9_EL1" bitsize="64" regnum="35913" group="system"/>
+ <reg name="BRBTGT9_EL1" bitsize="64" regnum="35914" group="system"/>
+ <reg name="BRBINF25_EL1" bitsize="64" regnum="35916" group="system"/>
+ <reg name="BRBSRC25_EL1" bitsize="64" regnum="35917" group="system"/>
+ <reg name="BRBTGT25_EL1" bitsize="64" regnum="35918" group="system"/>
+ <reg name="BRBINF10_EL1" bitsize="64" regnum="35920" group="system"/>
+ <reg name="BRBSRC10_EL1" bitsize="64" regnum="35921" group="system"/>
+ <reg name="BRBTGT10_EL1" bitsize="64" regnum="35922" group="system"/>
+ <reg name="BRBINF26_EL1" bitsize="64" regnum="35924" group="system"/>
+ <reg name="BRBSRC26_EL1" bitsize="64" regnum="35925" group="system"/>
+ <reg name="BRBTGT26_EL1" bitsize="64" regnum="35926" group="system"/>
+ <reg name="BRBINF11_EL1" bitsize="64" regnum="35928" group="system"/>
+ <reg name="BRBSRC11_EL1" bitsize="64" regnum="35929" group="system"/>
+ <reg name="BRBTGT11_EL1" bitsize="64" regnum="35930" group="system"/>
+ <reg name="BRBINF27_EL1" bitsize="64" regnum="35932" group="system"/>
+ <reg name="BRBSRC27_EL1" bitsize="64" regnum="35933" group="system"/>
+ <reg name="BRBTGT27_EL1" bitsize="64" regnum="35934" group="system"/>
+ <reg name="BRBINF12_EL1" bitsize="64" regnum="35936" group="system"/>
+ <reg name="BRBSRC12_EL1" bitsize="64" regnum="35937" group="system"/>
+ <reg name="BRBTGT12_EL1" bitsize="64" regnum="35938" group="system"/>
+ <reg name="BRBINF28_EL1" bitsize="64" regnum="35940" group="system"/>
+ <reg name="BRBSRC28_EL1" bitsize="64" regnum="35941" group="system"/>
+ <reg name="BRBTGT28_EL1" bitsize="64" regnum="35942" group="system"/>
+ <reg name="BRBINF13_EL1" bitsize="64" regnum="35944" group="system"/>
+ <reg name="BRBSRC13_EL1" bitsize="64" regnum="35945" group="system"/>
+ <reg name="BRBTGT13_EL1" bitsize="64" regnum="35946" group="system"/>
+ <reg name="BRBINF29_EL1" bitsize="64" regnum="35948" group="system"/>
+ <reg name="BRBSRC29_EL1" bitsize="64" regnum="35949" group="system"/>
+ <reg name="BRBTGT29_EL1" bitsize="64" regnum="35950" group="system"/>
+ <reg name="BRBINF14_EL1" bitsize="64" regnum="35952" group="system"/>
+ <reg name="BRBSRC14_EL1" bitsize="64" regnum="35953" group="system"/>
+ <reg name="BRBTGT14_EL1" bitsize="64" regnum="35954" group="system"/>
+ <reg name="BRBINF30_EL1" bitsize="64" regnum="35956" group="system"/>
+ <reg name="BRBSRC30_EL1" bitsize="64" regnum="35957" group="system"/>
+ <reg name="BRBTGT30_EL1" bitsize="64" regnum="35958" group="system"/>
+ <reg name="BRBINF15_EL1" bitsize="64" regnum="35960" group="system"/>
+ <reg name="BRBSRC15_EL1" bitsize="64" regnum="35961" group="system"/>
+ <reg name="BRBTGT15_EL1" bitsize="64" regnum="35962" group="system"/>
+ <reg name="BRBINF31_EL1" bitsize="64" regnum="35964" group="system"/>
+ <reg name="BRBSRC31_EL1" bitsize="64" regnum="35965" group="system"/>
+ <reg name="BRBTGT31_EL1" bitsize="64" regnum="35966" group="system"/>
+ <reg name="BRBCR_EL1" bitsize="64" regnum="35968" group="system"/>
+ <reg name="BRBCR_EL2" bitsize="64" regnum="35968" group="system"/>
+ <reg name="BRBFCR_EL1" bitsize="64" regnum="35969" group="system"/>
+ <reg name="BRBTS_EL1" bitsize="64" regnum="35970" group="system"/>
+ <reg name="BRBINFINJ_EL1" bitsize="64" regnum="35976" group="system"/>
+ <reg name="BRBSRCINJ_EL1" bitsize="64" regnum="35977" group="system"/>
+ <reg name="BRBTGTINJ_EL1" bitsize="64" regnum="35978" group="system"/>
+ <reg name="BRBIDR0_EL1" bitsize="64" regnum="35984" group="system"/>
+ <reg name="MDCCSR_EL0" bitsize="64" regnum="38920" group="system"/>
+ <reg name="DBGDTR_EL0" bitsize="64" regnum="38944" group="system"/>
+ <reg name="DBGDTRRX_EL0" bitsize="64" regnum="38952" group="system"/>
+ <reg name="DBGDTRTX_EL0" bitsize="64" regnum="38952" group="system"/>
+ <reg name="DBGVCR32_EL2" bitsize="64" regnum="41016" group="system"/>
+ <reg name="MIDR_EL1" bitsize="64" regnum="49152" group="system"/>
+ <reg name="MPIDR_EL1" bitsize="64" regnum="49157" group="system"/>
+ <reg name="REVIDR_EL1" bitsize="64" regnum="49158" group="system"/>
+ <reg name="ID_PFR0_EL1" bitsize="64" regnum="49160" group="system"/>
+ <reg name="ID_PFR1_EL1" bitsize="64" regnum="49161" group="system"/>
+ <reg name="ID_DFR0_EL1" bitsize="64" regnum="49162" group="system"/>
+ <reg name="ID_AFR0_EL1" bitsize="64" regnum="49163" group="system"/>
+ <reg name="ID_MMFR0_EL1" bitsize="64" regnum="49164" group="system"/>
+ <reg name="ID_MMFR1_EL1" bitsize="64" regnum="49165" group="system"/>
+ <reg name="ID_MMFR2_EL1" bitsize="64" regnum="49166" group="system"/>
+ <reg name="ID_MMFR3_EL1" bitsize="64" regnum="49167" group="system"/>
+ <reg name="ID_ISAR0_EL1" bitsize="64" regnum="49168" group="system"/>
+ <reg name="ID_ISAR1_EL1" bitsize="64" regnum="49169" group="system"/>
+ <reg name="ID_ISAR2_EL1" bitsize="64" regnum="49170" group="system"/>
+ <reg name="ID_ISAR3_EL1" bitsize="64" regnum="49171" group="system"/>
+ <reg name="ID_ISAR4_EL1" bitsize="64" regnum="49172" group="system"/>
+ <reg name="ID_ISAR5_EL1" bitsize="64" regnum="49173" group="system"/>
+ <reg name="ID_MMFR4_EL1" bitsize="64" regnum="49174" group="system"/>
+ <reg name="ID_ISAR6_EL1" bitsize="64" regnum="49175" group="system"/>
+ <reg name="MVFR0_EL1" bitsize="64" regnum="49176" group="system"/>
+ <reg name="MVFR1_EL1" bitsize="64" regnum="49177" group="system"/>
+ <reg name="MVFR2_EL1" bitsize="64" regnum="49178" group="system"/>
+ <reg name="ID_PFR2_EL1" bitsize="64" regnum="49180" group="system"/>
+ <reg name="ID_DFR1_EL1" bitsize="64" regnum="49181" group="system"/>
+ <reg name="ID_MMFR5_EL1" bitsize="64" regnum="49182" group="system"/>
+ <reg name="ID_AA64PFR0_EL1" bitsize="64" regnum="49184" group="system"/>
+ <reg name="ID_AA64PFR1_EL1" bitsize="64" regnum="49185" group="system"/>
+ <reg name="ID_AA64ZFR0_EL1" bitsize="64" regnum="49188" group="system"/>
+ <reg name="ID_AA64SMFR0_EL1" bitsize="64" regnum="49189" group="system"/>
+ <reg name="ID_AA64DFR0_EL1" bitsize="64" regnum="49192" group="system"/>
+ <reg name="ID_AA64DFR1_EL1" bitsize="64" regnum="49193" group="system"/>
+ <reg name="ID_AA64AFR0_EL1" bitsize="64" regnum="49196" group="system"/>
+ <reg name="ID_AA64AFR1_EL1" bitsize="64" regnum="49197" group="system"/>
+ <reg name="ID_AA64ISAR0_EL1" bitsize="64" regnum="49200" group="system"/>
+ <reg name="ID_AA64ISAR1_EL1" bitsize="64" regnum="49201" group="system"/>
+ <reg name="ID_AA64ISAR2_EL1" bitsize="64" regnum="49202" group="system"/>
+ <reg name="ID_AA64MMFR0_EL1" bitsize="64" regnum="49208" group="system"/>
+ <reg name="ID_AA64MMFR1_EL1" bitsize="64" regnum="49209" group="system"/>
+ <reg name="ID_AA64MMFR2_EL1" bitsize="64" regnum="49210" group="system"/>
+ <reg name="SCTLR_EL1" bitsize="64" regnum="49280" group="system"/>
+ <reg name="ACTLR_EL1" bitsize="64" regnum="49281" group="system"/>
+ <reg name="CPACR_EL1" bitsize="64" regnum="49282" group="system"/>
+ <reg name="RGSR_EL1" bitsize="64" regnum="49285" group="system"/>
+ <reg name="GCR_EL1" bitsize="64" regnum="49286" group="system"/>
+ <reg name="ZCR_EL1" bitsize="64" regnum="49296" group="system"/>
+ <reg name="TRFCR_EL1" bitsize="64" regnum="49297" group="system"/>
+ <reg name="SMPRI_EL1" bitsize="64" regnum="49300" group="system"/>
+ <reg name="SMCR_EL1" bitsize="64" regnum="49302" group="system"/>
+ <reg name="TTBR0_EL1" bitsize="64" regnum="49408" group="system"/>
+ <reg name="TTBR1_EL1" bitsize="64" regnum="49409" group="system"/>
+ <reg name="TCR_EL1" bitsize="64" regnum="49410" group="system"/>
+ <reg name="APIAKeyLo_EL1" bitsize="64" regnum="49416" group="system"/>
+ <reg name="APIAKeyHi_EL1" bitsize="64" regnum="49417" group="system"/>
+ <reg name="APIBKeyLo_EL1" bitsize="64" regnum="49418" group="system"/>
+ <reg name="APIBKeyHi_EL1" bitsize="64" regnum="49419" group="system"/>
+ <reg name="APDAKeyLo_EL1" bitsize="64" regnum="49424" group="system"/>
+ <reg name="APDAKeyHi_EL1" bitsize="64" regnum="49425" group="system"/>
+ <reg name="APDBKeyLo_EL1" bitsize="64" regnum="49426" group="system"/>
+ <reg name="APDBKeyHi_EL1" bitsize="64" regnum="49427" group="system"/>
+ <reg name="APGAKeyLo_EL1" bitsize="64" regnum="49432" group="system"/>
+ <reg name="APGAKeyHi_EL1" bitsize="64" regnum="49433" group="system"/>
+ <reg name="SPSR_EL1" bitsize="64" regnum="49664" group="system"/>
+ <reg name="ELR_EL1" bitsize="64" regnum="49665" group="system"/>
+ <reg name="SP_EL0" bitsize="64" regnum="49672" group="system"/>
+ <reg name="ICC_PMR_EL1" bitsize="64" regnum="49712" group="system"/>
+ <reg name="ICV_PMR_EL1" bitsize="64" regnum="49712" group="system"/>
+ <reg name="AFSR0_EL1" bitsize="64" regnum="49800" group="system"/>
+ <reg name="AFSR1_EL1" bitsize="64" regnum="49801" group="system"/>
+ <reg name="ESR_EL1" bitsize="64" regnum="49808" group="system"/>
+ <reg name="ERRIDR_EL1" bitsize="64" regnum="49816" group="system"/>
+ <reg name="ERRSELR_EL1" bitsize="64" regnum="49817" group="system"/>
+ <reg name="ERXFR_EL1" bitsize="64" regnum="49824" group="system"/>
+ <reg name="ERXCTLR_EL1" bitsize="64" regnum="49825" group="system"/>
+ <reg name="ERXSTATUS_EL1" bitsize="64" regnum="49826" group="system"/>
+ <reg name="ERXADDR_EL1" bitsize="64" regnum="49827" group="system"/>
+ <reg name="ERXPFGF_EL1" bitsize="64" regnum="49828" group="system"/>
+ <reg name="ERXPFGCTL_EL1" bitsize="64" regnum="49829" group="system"/>
+ <reg name="ERXPFGCDN_EL1" bitsize="64" regnum="49830" group="system"/>
+ <reg name="ERXMISC0_EL1" bitsize="64" regnum="49832" group="system"/>
+ <reg name="ERXMISC1_EL1" bitsize="64" regnum="49833" group="system"/>
+ <reg name="ERXMISC2_EL1" bitsize="64" regnum="49834" group="system"/>
+ <reg name="ERXMISC3_EL1" bitsize="64" regnum="49835" group="system"/>
+ <reg name="TFSR_EL1" bitsize="64" regnum="49840" group="system"/>
+ <reg name="TFSRE0_EL1" bitsize="64" regnum="49841" group="system"/>
+ <reg name="FAR_EL1" bitsize="64" regnum="49920" group="system"/>
+ <reg name="PAR_EL1" bitsize="64" regnum="50080" group="system"/>
+ <reg name="PMSCR_EL1" bitsize="64" regnum="50376" group="system"/>
+ <reg name="PMSNEVFR_EL1" bitsize="64" regnum="50377" group="system"/>
+ <reg name="PMSICR_EL1" bitsize="64" regnum="50378" group="system"/>
+ <reg name="PMSIRR_EL1" bitsize="64" regnum="50379" group="system"/>
+ <reg name="PMSFCR_EL1" bitsize="64" regnum="50380" group="system"/>
+ <reg name="PMSEVFR_EL1" bitsize="64" regnum="50381" group="system"/>
+ <reg name="PMSLATFR_EL1" bitsize="64" regnum="50382" group="system"/>
+ <reg name="PMSIDR_EL1" bitsize="64" regnum="50383" group="system"/>
+ <reg name="PMBLIMITR_EL1" bitsize="64" regnum="50384" group="system"/>
+ <reg name="PMBPTR_EL1" bitsize="64" regnum="50385" group="system"/>
+ <reg name="PMBSR_EL1" bitsize="64" regnum="50387" group="system"/>
+ <reg name="PMBIDR_EL1" bitsize="64" regnum="50391" group="system"/>
+ <reg name="TRBLIMITR_EL1" bitsize="64" regnum="50392" group="system"/>
+ <reg name="TRBPTR_EL1" bitsize="64" regnum="50393" group="system"/>
+ <reg name="TRBBASER_EL1" bitsize="64" regnum="50394" group="system"/>
+ <reg name="TRBSR_EL1" bitsize="64" regnum="50395" group="system"/>
+ <reg name="TRBMAR_EL1" bitsize="64" regnum="50396" group="system"/>
+ <reg name="TRBTRG_EL1" bitsize="64" regnum="50398" group="system"/>
+ <reg name="TRBIDR_EL1" bitsize="64" regnum="50399" group="system"/>
+ <reg name="PMINTENSET_EL1" bitsize="64" regnum="50417" group="system"/>
+ <reg name="PMINTENCLR_EL1" bitsize="64" regnum="50418" group="system"/>
+ <reg name="PMMIR_EL1" bitsize="64" regnum="50422" group="system"/>
+ <reg name="MAIR_EL1" bitsize="64" regnum="50448" group="system"/>
+ <reg name="AMAIR_EL1" bitsize="64" regnum="50456" group="system"/>
+ <reg name="LORSA_EL1" bitsize="64" regnum="50464" group="system"/>
+ <reg name="LOREA_EL1" bitsize="64" regnum="50465" group="system"/>
+ <reg name="LORN_EL1" bitsize="64" regnum="50466" group="system"/>
+ <reg name="LORC_EL1" bitsize="64" regnum="50467" group="system"/>
+ <reg name="MPAMIDR_EL1" bitsize="64" regnum="50468" group="system"/>
+ <reg name="LORID_EL1" bitsize="64" regnum="50471" group="system"/>
+ <reg name="MPAM1_EL1" bitsize="64" regnum="50472" group="system"/>
+ <reg name="MPAM0_EL1" bitsize="64" regnum="50473" group="system"/>
+ <reg name="MPAMSM_EL1" bitsize="64" regnum="50475" group="system"/>
+ <reg name="VBAR_EL1" bitsize="64" regnum="50688" group="system"/>
+ <reg name="RVBAR_EL1" bitsize="64" regnum="50689" group="system"/>
+ <reg name="RMR_EL1" bitsize="64" regnum="50690" group="system"/>
+ <reg name="ISR_EL1" bitsize="64" regnum="50696" group="system"/>
+ <reg name="DISR_EL1" bitsize="64" regnum="50697" group="system"/>
+ <reg name="ICC_IAR0_EL1" bitsize="64" regnum="50752" group="system"/>
+ <reg name="ICV_IAR0_EL1" bitsize="64" regnum="50752" group="system"/>
+ <reg name="ICC_EOIR0_EL1" bitsize="64" regnum="50753" group="system"/>
+ <reg name="ICV_EOIR0_EL1" bitsize="64" regnum="50753" group="system"/>
+ <reg name="ICC_HPPIR0_EL1" bitsize="64" regnum="50754" group="system"/>
+ <reg name="ICV_HPPIR0_EL1" bitsize="64" regnum="50754" group="system"/>
+ <reg name="ICC_BPR0_EL1" bitsize="64" regnum="50755" group="system"/>
+ <reg name="ICV_BPR0_EL1" bitsize="64" regnum="50755" group="system"/>
+ <reg name="ICC_AP0R0_EL1" bitsize="64" regnum="50756" group="system"/>
+ <reg name="ICV_AP0R0_EL1" bitsize="64" regnum="50756" group="system"/>
+ <reg name="ICC_AP0R1_EL1" bitsize="64" regnum="50757" group="system"/>
+ <reg name="ICV_AP0R1_EL1" bitsize="64" regnum="50757" group="system"/>
+ <reg name="ICC_AP0R2_EL1" bitsize="64" regnum="50758" group="system"/>
+ <reg name="ICV_AP0R2_EL1" bitsize="64" regnum="50758" group="system"/>
+ <reg name="ICC_AP0R3_EL1" bitsize="64" regnum="50759" group="system"/>
+ <reg name="ICV_AP0R3_EL1" bitsize="64" regnum="50759" group="system"/>
+ <reg name="ICC_AP1R0_EL1" bitsize="64" regnum="50760" group="system"/>
+ <reg name="ICV_AP1R0_EL1" bitsize="64" regnum="50760" group="system"/>
+ <reg name="ICC_AP1R1_EL1" bitsize="64" regnum="50761" group="system"/>
+ <reg name="ICV_AP1R1_EL1" bitsize="64" regnum="50761" group="system"/>
+ <reg name="ICC_AP1R2_EL1" bitsize="64" regnum="50762" group="system"/>
+ <reg name="ICV_AP1R2_EL1" bitsize="64" regnum="50762" group="system"/>
+ <reg name="ICC_AP1R3_EL1" bitsize="64" regnum="50763" group="system"/>
+ <reg name="ICV_AP1R3_EL1" bitsize="64" regnum="50763" group="system"/>
+ <reg name="ICC_NMIAR1_EL1" bitsize="64" regnum="50765" group="system"/>
+ <reg name="ICV_NMIAR1_EL1" bitsize="64" regnum="50765" group="system"/>
+ <reg name="ICC_DIR_EL1" bitsize="64" regnum="50777" group="system"/>
+ <reg name="ICV_DIR_EL1" bitsize="64" regnum="50777" group="system"/>
+ <reg name="ICC_RPR_EL1" bitsize="64" regnum="50779" group="system"/>
+ <reg name="ICV_RPR_EL1" bitsize="64" regnum="50779" group="system"/>
+ <reg name="ICC_SGI1R_EL1" bitsize="64" regnum="50781" group="system"/>
+ <reg name="ICC_ASGI1R_EL1" bitsize="64" regnum="50782" group="system"/>
+ <reg name="ICC_SGI0R_EL1" bitsize="64" regnum="50783" group="system"/>
+ <reg name="ICC_IAR1_EL1" bitsize="64" regnum="50784" group="system"/>
+ <reg name="ICV_IAR1_EL1" bitsize="64" regnum="50784" group="system"/>
+ <reg name="ICC_EOIR1_EL1" bitsize="64" regnum="50785" group="system"/>
+ <reg name="ICV_EOIR1_EL1" bitsize="64" regnum="50785" group="system"/>
+ <reg name="ICC_HPPIR1_EL1" bitsize="64" regnum="50786" group="system"/>
+ <reg name="ICV_HPPIR1_EL1" bitsize="64" regnum="50786" group="system"/>
+ <reg name="ICC_BPR1_EL1" bitsize="64" regnum="50787" group="system"/>
+ <reg name="ICV_BPR1_EL1" bitsize="64" regnum="50787" group="system"/>
+ <reg name="ICC_CTLR_EL1" bitsize="64" regnum="50788" group="system"/>
+ <reg name="ICV_CTLR_EL1" bitsize="64" regnum="50788" group="system"/>
+ <reg name="ICC_SRE_EL1" bitsize="64" regnum="50789" group="system"/>
+ <reg name="ICC_IGRPEN0_EL1" bitsize="64" regnum="50790" group="system"/>
+ <reg name="ICV_IGRPEN0_EL1" bitsize="64" regnum="50790" group="system"/>
+ <reg name="ICC_IGRPEN1_EL1" bitsize="64" regnum="50791" group="system"/>
+ <reg name="ICV_IGRPEN1_EL1" bitsize="64" regnum="50791" group="system"/>
+ <reg name="CONTEXTIDR_EL1" bitsize="64" regnum="50817" group="system"/>
+ <reg name="TPIDR_EL1" bitsize="64" regnum="50820" group="system"/>
+ <reg name="ACCDATA_EL1" bitsize="64" regnum="50821" group="system"/>
+ <reg name="SCXTNUM_EL1" bitsize="64" regnum="50823" group="system"/>
+ <reg name="CNTKCTL_EL1" bitsize="64" regnum="50952" group="system"/>
+ <reg name="CCSIDR_EL1" bitsize="64" regnum="51200" group="system"/>
+ <reg name="CLIDR_EL1" bitsize="64" regnum="51201" group="system"/>
+ <reg name="CCSIDR2_EL1" bitsize="64" regnum="51202" group="system"/>
+ <reg name="GMID_EL1" bitsize="64" regnum="51204" group="system"/>
+ <reg name="SMIDR_EL1" bitsize="64" regnum="51206" group="system"/>
+ <reg name="AIDR_EL1" bitsize="64" regnum="51207" group="system"/>
+ <reg name="CSSELR_EL1" bitsize="64" regnum="53248" group="system"/>
+ <reg name="CTR_EL0" bitsize="64" regnum="55297" group="system"/>
+ <reg name="DCZID_EL0" bitsize="64" regnum="55303" group="system"/>
+ <reg name="RNDR" bitsize="64" regnum="55584" group="system"/>
+ <reg name="RNDRRS" bitsize="64" regnum="55585" group="system"/>
+ <reg name="SVCR" bitsize="64" regnum="55826" group="system"/>
+ <reg name="FPCR" bitsize="64" regnum="55840" group="system"/>
+ <reg name="FPSR" bitsize="64" regnum="55841" group="system"/>
+ <reg name="DSPSR_EL0" bitsize="64" regnum="55848" group="system"/>
+ <reg name="DLR_EL0" bitsize="64" regnum="55849" group="system"/>
+ <reg name="PMCR_EL0" bitsize="64" regnum="56544" group="system"/>
+ <reg name="PMCNTENSET_EL0" bitsize="64" regnum="56545" group="system"/>
+ <reg name="PMCNTENCLR_EL0" bitsize="64" regnum="56546" group="system"/>
+ <reg name="PMOVSCLR_EL0" bitsize="64" regnum="56547" group="system"/>
+ <reg name="PMSWINC_EL0" bitsize="64" regnum="56548" group="system"/>
+ <reg name="PMSELR_EL0" bitsize="64" regnum="56549" group="system"/>
+ <reg name="PMCEID0_EL0" bitsize="64" regnum="56550" group="system"/>
+ <reg name="PMCEID1_EL0" bitsize="64" regnum="56551" group="system"/>
+ <reg name="PMCCNTR_EL0" bitsize="64" regnum="56552" group="system"/>
+ <reg name="PMXEVTYPER_EL0" bitsize="64" regnum="56553" group="system"/>
+ <reg name="PMXEVCNTR_EL0" bitsize="64" regnum="56554" group="system"/>
+ <reg name="PMUSERENR_EL0" bitsize="64" regnum="56560" group="system"/>
+ <reg name="PMOVSSET_EL0" bitsize="64" regnum="56563" group="system"/>
+ <reg name="TPIDR_EL0" bitsize="64" regnum="56962" group="system"/>
+ <reg name="TPIDRRO_EL0" bitsize="64" regnum="56963" group="system"/>
+ <reg name="TPIDR2_EL0" bitsize="64" regnum="56965" group="system"/>
+ <reg name="SCXTNUM_EL0" bitsize="64" regnum="56967" group="system"/>
+ <reg name="AMCR_EL0" bitsize="64" regnum="56976" group="system"/>
+ <reg name="AMCFGR_EL0" bitsize="64" regnum="56977" group="system"/>
+ <reg name="AMCGCR_EL0" bitsize="64" regnum="56978" group="system"/>
+ <reg name="AMUSERENR_EL0" bitsize="64" regnum="56979" group="system"/>
+ <reg name="AMCNTENCLR0_EL0" bitsize="64" regnum="56980" group="system"/>
+ <reg name="AMCNTENSET0_EL0" bitsize="64" regnum="56981" group="system"/>
+ <reg name="AMCG1IDR_EL0" bitsize="64" regnum="56982" group="system"/>
+ <reg name="AMCNTENCLR1_EL0" bitsize="64" regnum="56984" group="system"/>
+ <reg name="AMCNTENSET1_EL0" bitsize="64" regnum="56985" group="system"/>
+ <reg name="AMEVCNTR00_EL0" bitsize="64" regnum="56992" group="system"/>
+ <reg name="AMEVCNTR01_EL0" bitsize="64" regnum="56993" group="system"/>
+ <reg name="AMEVCNTR02_EL0" bitsize="64" regnum="56994" group="system"/>
+ <reg name="AMEVCNTR03_EL0" bitsize="64" regnum="56995" group="system"/>
+ <reg name="AMEVTYPER00_EL0" bitsize="64" regnum="57008" group="system"/>
+ <reg name="AMEVTYPER01_EL0" bitsize="64" regnum="57009" group="system"/>
+ <reg name="AMEVTYPER02_EL0" bitsize="64" regnum="57010" group="system"/>
+ <reg name="AMEVTYPER03_EL0" bitsize="64" regnum="57011" group="system"/>
+ <reg name="AMEVCNTR10_EL0" bitsize="64" regnum="57056" group="system"/>
+ <reg name="AMEVCNTR11_EL0" bitsize="64" regnum="57057" group="system"/>
+ <reg name="AMEVCNTR12_EL0" bitsize="64" regnum="57058" group="system"/>
+ <reg name="AMEVCNTR13_EL0" bitsize="64" regnum="57059" group="system"/>
+ <reg name="AMEVCNTR14_EL0" bitsize="64" regnum="57060" group="system"/>
+ <reg name="AMEVCNTR15_EL0" bitsize="64" regnum="57061" group="system"/>
+ <reg name="AMEVCNTR16_EL0" bitsize="64" regnum="57062" group="system"/>
+ <reg name="AMEVCNTR17_EL0" bitsize="64" regnum="57063" group="system"/>
+ <reg name="AMEVCNTR18_EL0" bitsize="64" regnum="57064" group="system"/>
+ <reg name="AMEVCNTR19_EL0" bitsize="64" regnum="57065" group="system"/>
+ <reg name="AMEVCNTR110_EL0" bitsize="64" regnum="57066" group="system"/>
+ <reg name="AMEVCNTR111_EL0" bitsize="64" regnum="57067" group="system"/>
+ <reg name="AMEVCNTR112_EL0" bitsize="64" regnum="57068" group="system"/>
+ <reg name="AMEVCNTR113_EL0" bitsize="64" regnum="57069" group="system"/>
+ <reg name="AMEVCNTR114_EL0" bitsize="64" regnum="57070" group="system"/>
+ <reg name="AMEVCNTR115_EL0" bitsize="64" regnum="57071" group="system"/>
+ <reg name="AMEVTYPER10_EL0" bitsize="64" regnum="57072" group="system"/>
+ <reg name="AMEVTYPER11_EL0" bitsize="64" regnum="57073" group="system"/>
+ <reg name="AMEVTYPER12_EL0" bitsize="64" regnum="57074" group="system"/>
+ <reg name="AMEVTYPER13_EL0" bitsize="64" regnum="57075" group="system"/>
+ <reg name="AMEVTYPER14_EL0" bitsize="64" regnum="57076" group="system"/>
+ <reg name="AMEVTYPER15_EL0" bitsize="64" regnum="57077" group="system"/>
+ <reg name="AMEVTYPER16_EL0" bitsize="64" regnum="57078" group="system"/>
+ <reg name="AMEVTYPER17_EL0" bitsize="64" regnum="57079" group="system"/>
+ <reg name="AMEVTYPER18_EL0" bitsize="64" regnum="57080" group="system"/>
+ <reg name="AMEVTYPER19_EL0" bitsize="64" regnum="57081" group="system"/>
+ <reg name="AMEVTYPER110_EL0" bitsize="64" regnum="57082" group="system"/>
+ <reg name="AMEVTYPER111_EL0" bitsize="64" regnum="57083" group="system"/>
+ <reg name="AMEVTYPER112_EL0" bitsize="64" regnum="57084" group="system"/>
+ <reg name="AMEVTYPER113_EL0" bitsize="64" regnum="57085" group="system"/>
+ <reg name="AMEVTYPER114_EL0" bitsize="64" regnum="57086" group="system"/>
+ <reg name="AMEVTYPER115_EL0" bitsize="64" regnum="57087" group="system"/>
+ <reg name="CNTFRQ_EL0" bitsize="64" regnum="57088" group="system"/>
+ <reg name="CNTPCT_EL0" bitsize="64" regnum="57089" group="system"/>
+ <reg name="CNTVCT_EL0" bitsize="64" regnum="57090" group="system"/>
+ <reg name="CNTPCTSS_EL0" bitsize="64" regnum="57093" group="system"/>
+ <reg name="CNTVCTSS_EL0" bitsize="64" regnum="57094" group="system"/>
+ <reg name="CNTP_TVAL_EL0" bitsize="64" regnum="57104" group="system"/>
+ <reg name="CNTP_CTL_EL0" bitsize="64" regnum="57105" group="system"/>
+ <reg name="CNTP_CVAL_EL0" bitsize="64" regnum="57106" group="system"/>
+ <reg name="CNTV_TVAL_EL0" bitsize="64" regnum="57112" group="system"/>
+ <reg name="CNTV_CTL_EL0" bitsize="64" regnum="57113" group="system"/>
+ <reg name="CNTV_CVAL_EL0" bitsize="64" regnum="57114" group="system"/>
+ <reg name="PMEVCNTR0_EL0" bitsize="64" regnum="57152" group="system"/>
+ <reg name="PMEVCNTR1_EL0" bitsize="64" regnum="57153" group="system"/>
+ <reg name="PMEVCNTR2_EL0" bitsize="64" regnum="57154" group="system"/>
+ <reg name="PMEVCNTR3_EL0" bitsize="64" regnum="57155" group="system"/>
+ <reg name="PMEVCNTR4_EL0" bitsize="64" regnum="57156" group="system"/>
+ <reg name="PMEVCNTR5_EL0" bitsize="64" regnum="57157" group="system"/>
+ <reg name="PMEVCNTR6_EL0" bitsize="64" regnum="57158" group="system"/>
+ <reg name="PMEVCNTR7_EL0" bitsize="64" regnum="57159" group="system"/>
+ <reg name="PMEVCNTR8_EL0" bitsize="64" regnum="57160" group="system"/>
+ <reg name="PMEVCNTR9_EL0" bitsize="64" regnum="57161" group="system"/>
+ <reg name="PMEVCNTR10_EL0" bitsize="64" regnum="57162" group="system"/>
+ <reg name="PMEVCNTR11_EL0" bitsize="64" regnum="57163" group="system"/>
+ <reg name="PMEVCNTR12_EL0" bitsize="64" regnum="57164" group="system"/>
+ <reg name="PMEVCNTR13_EL0" bitsize="64" regnum="57165" group="system"/>
+ <reg name="PMEVCNTR14_EL0" bitsize="64" regnum="57166" group="system"/>
+ <reg name="PMEVCNTR15_EL0" bitsize="64" regnum="57167" group="system"/>
+ <reg name="PMEVCNTR16_EL0" bitsize="64" regnum="57168" group="system"/>
+ <reg name="PMEVCNTR17_EL0" bitsize="64" regnum="57169" group="system"/>
+ <reg name="PMEVCNTR18_EL0" bitsize="64" regnum="57170" group="system"/>
+ <reg name="PMEVCNTR19_EL0" bitsize="64" regnum="57171" group="system"/>
+ <reg name="PMEVCNTR20_EL0" bitsize="64" regnum="57172" group="system"/>
+ <reg name="PMEVCNTR21_EL0" bitsize="64" regnum="57173" group="system"/>
+ <reg name="PMEVCNTR22_EL0" bitsize="64" regnum="57174" group="system"/>
+ <reg name="PMEVCNTR23_EL0" bitsize="64" regnum="57175" group="system"/>
+ <reg name="PMEVCNTR24_EL0" bitsize="64" regnum="57176" group="system"/>
+ <reg name="PMEVCNTR25_EL0" bitsize="64" regnum="57177" group="system"/>
+ <reg name="PMEVCNTR26_EL0" bitsize="64" regnum="57178" group="system"/>
+ <reg name="PMEVCNTR27_EL0" bitsize="64" regnum="57179" group="system"/>
+ <reg name="PMEVCNTR28_EL0" bitsize="64" regnum="57180" group="system"/>
+ <reg name="PMEVCNTR29_EL0" bitsize="64" regnum="57181" group="system"/>
+ <reg name="PMEVCNTR30_EL0" bitsize="64" regnum="57182" group="system"/>
+ <reg name="PMEVTYPER0_EL0" bitsize="64" regnum="57184" group="system"/>
+ <reg name="PMEVTYPER1_EL0" bitsize="64" regnum="57185" group="system"/>
+ <reg name="PMEVTYPER2_EL0" bitsize="64" regnum="57186" group="system"/>
+ <reg name="PMEVTYPER3_EL0" bitsize="64" regnum="57187" group="system"/>
+ <reg name="PMEVTYPER4_EL0" bitsize="64" regnum="57188" group="system"/>
+ <reg name="PMEVTYPER5_EL0" bitsize="64" regnum="57189" group="system"/>
+ <reg name="PMEVTYPER6_EL0" bitsize="64" regnum="57190" group="system"/>
+ <reg name="PMEVTYPER7_EL0" bitsize="64" regnum="57191" group="system"/>
+ <reg name="PMEVTYPER8_EL0" bitsize="64" regnum="57192" group="system"/>
+ <reg name="PMEVTYPER9_EL0" bitsize="64" regnum="57193" group="system"/>
+ <reg name="PMEVTYPER10_EL0" bitsize="64" regnum="57194" group="system"/>
+ <reg name="PMEVTYPER11_EL0" bitsize="64" regnum="57195" group="system"/>
+ <reg name="PMEVTYPER12_EL0" bitsize="64" regnum="57196" group="system"/>
+ <reg name="PMEVTYPER13_EL0" bitsize="64" regnum="57197" group="system"/>
+ <reg name="PMEVTYPER14_EL0" bitsize="64" regnum="57198" group="system"/>
+ <reg name="PMEVTYPER15_EL0" bitsize="64" regnum="57199" group="system"/>
+ <reg name="PMEVTYPER16_EL0" bitsize="64" regnum="57200" group="system"/>
+ <reg name="PMEVTYPER17_EL0" bitsize="64" regnum="57201" group="system"/>
+ <reg name="PMEVTYPER18_EL0" bitsize="64" regnum="57202" group="system"/>
+ <reg name="PMEVTYPER19_EL0" bitsize="64" regnum="57203" group="system"/>
+ <reg name="PMEVTYPER20_EL0" bitsize="64" regnum="57204" group="system"/>
+ <reg name="PMEVTYPER21_EL0" bitsize="64" regnum="57205" group="system"/>
+ <reg name="PMEVTYPER22_EL0" bitsize="64" regnum="57206" group="system"/>
+ <reg name="PMEVTYPER23_EL0" bitsize="64" regnum="57207" group="system"/>
+ <reg name="PMEVTYPER24_EL0" bitsize="64" regnum="57208" group="system"/>
+ <reg name="PMEVTYPER25_EL0" bitsize="64" regnum="57209" group="system"/>
+ <reg name="PMEVTYPER26_EL0" bitsize="64" regnum="57210" group="system"/>
+ <reg name="PMEVTYPER27_EL0" bitsize="64" regnum="57211" group="system"/>
+ <reg name="PMEVTYPER28_EL0" bitsize="64" regnum="57212" group="system"/>
+ <reg name="PMEVTYPER29_EL0" bitsize="64" regnum="57213" group="system"/>
+ <reg name="PMEVTYPER30_EL0" bitsize="64" regnum="57214" group="system"/>
+ <reg name="PMCCFILTR_EL0" bitsize="64" regnum="57215" group="system"/>
+ <reg name="VPIDR_EL2" bitsize="64" regnum="57344" group="system"/>
+ <reg name="VMPIDR_EL2" bitsize="64" regnum="57349" group="system"/>
+ <reg name="SCTLR_EL2" bitsize="64" regnum="57472" group="system"/>
+ <reg name="ACTLR_EL2" bitsize="64" regnum="57473" group="system"/>
+ <reg name="HCR_EL2" bitsize="64" regnum="57480" group="system"/>
+ <reg name="MDCR_EL2" bitsize="64" regnum="57481" group="system"/>
+ <reg name="CPTR_EL2" bitsize="64" regnum="57482" group="system"/>
+ <reg name="HSTR_EL2" bitsize="64" regnum="57483" group="system"/>
+ <reg name="HFGRTR_EL2" bitsize="64" regnum="57484" group="system"/>
+ <reg name="HFGWTR_EL2" bitsize="64" regnum="57485" group="system"/>
+ <reg name="HFGITR_EL2" bitsize="64" regnum="57486" group="system"/>
+ <reg name="HACR_EL2" bitsize="64" regnum="57487" group="system"/>
+ <reg name="ZCR_EL2" bitsize="64" regnum="57488" group="system"/>
+ <reg name="TRFCR_EL2" bitsize="64" regnum="57489" group="system"/>
+ <reg name="HCRX_EL2" bitsize="64" regnum="57490" group="system"/>
+ <reg name="SMPRIMAP_EL2" bitsize="64" regnum="57493" group="system"/>
+ <reg name="SMCR_EL2" bitsize="64" regnum="57494" group="system"/>
+ <reg name="SDER32_EL2" bitsize="64" regnum="57497" group="system"/>
+ <reg name="TTBR0_EL2" bitsize="64" regnum="57600" group="system"/>
+ <reg name="TTBR1_EL2" bitsize="64" regnum="57601" group="system"/>
+ <reg name="TCR_EL2" bitsize="64" regnum="57602" group="system"/>
+ <reg name="VTTBR_EL2" bitsize="64" regnum="57608" group="system"/>
+ <reg name="VTCR_EL2" bitsize="64" regnum="57610" group="system"/>
+ <reg name="VNCR_EL2" bitsize="64" regnum="57616" group="system"/>
+ <reg name="VSTTBR_EL2" bitsize="64" regnum="57648" group="system"/>
+ <reg name="VSTCR_EL2" bitsize="64" regnum="57650" group="system"/>
+ <reg name="DACR32_EL2" bitsize="64" regnum="57728" group="system"/>
+ <reg name="HDFGRTR_EL2" bitsize="64" regnum="57740" group="system"/>
+ <reg name="HDFGWTR_EL2" bitsize="64" regnum="57741" group="system"/>
+ <reg name="HAFGRTR_EL2" bitsize="64" regnum="57742" group="system"/>
+ <reg name="SPSR_EL2" bitsize="64" regnum="57856" group="system"/>
+ <reg name="ELR_EL2" bitsize="64" regnum="57857" group="system"/>
+ <reg name="SP_EL1" bitsize="64" regnum="57864" group="system"/>
+ <reg name="SPSR_irq" bitsize="64" regnum="57880" group="system"/>
+ <reg name="SPSR_abt" bitsize="64" regnum="57881" group="system"/>
+ <reg name="SPSR_und" bitsize="64" regnum="57882" group="system"/>
+ <reg name="SPSR_fiq" bitsize="64" regnum="57883" group="system"/>
+ <reg name="IFSR32_EL2" bitsize="64" regnum="57985" group="system"/>
+ <reg name="AFSR0_EL2" bitsize="64" regnum="57992" group="system"/>
+ <reg name="AFSR1_EL2" bitsize="64" regnum="57993" group="system"/>
+ <reg name="ESR_EL2" bitsize="64" regnum="58000" group="system"/>
+ <reg name="VSESR_EL2" bitsize="64" regnum="58003" group="system"/>
+ <reg name="FPEXC32_EL2" bitsize="64" regnum="58008" group="system"/>
+ <reg name="TFSR_EL2" bitsize="64" regnum="58032" group="system"/>
+ <reg name="FAR_EL2" bitsize="64" regnum="58112" group="system"/>
+ <reg name="HPFAR_EL2" bitsize="64" regnum="58116" group="system"/>
+ <reg name="PMSCR_EL2" bitsize="64" regnum="58568" group="system"/>
+ <reg name="MAIR_EL2" bitsize="64" regnum="58640" group="system"/>
+ <reg name="AMAIR_EL2" bitsize="64" regnum="58648" group="system"/>
+ <reg name="MPAMHCR_EL2" bitsize="64" regnum="58656" group="system"/>
+ <reg name="MPAMVPMV_EL2" bitsize="64" regnum="58657" group="system"/>
+ <reg name="MPAM2_EL2" bitsize="64" regnum="58664" group="system"/>
+ <reg name="MPAMVPM0_EL2" bitsize="64" regnum="58672" group="system"/>
+ <reg name="MPAMVPM1_EL2" bitsize="64" regnum="58673" group="system"/>
+ <reg name="MPAMVPM2_EL2" bitsize="64" regnum="58674" group="system"/>
+ <reg name="MPAMVPM3_EL2" bitsize="64" regnum="58675" group="system"/>
+ <reg name="MPAMVPM4_EL2" bitsize="64" regnum="58676" group="system"/>
+ <reg name="MPAMVPM5_EL2" bitsize="64" regnum="58677" group="system"/>
+ <reg name="MPAMVPM6_EL2" bitsize="64" regnum="58678" group="system"/>
+ <reg name="MPAMVPM7_EL2" bitsize="64" regnum="58679" group="system"/>
+ <reg name="VBAR_EL2" bitsize="64" regnum="58880" group="system"/>
+ <reg name="RVBAR_EL2" bitsize="64" regnum="58881" group="system"/>
+ <reg name="RMR_EL2" bitsize="64" regnum="58882" group="system"/>
+ <reg name="VDISR_EL2" bitsize="64" regnum="58889" group="system"/>
+ <reg name="ICH_AP0R0_EL2" bitsize="64" regnum="58944" group="system"/>
+ <reg name="ICH_AP0R1_EL2" bitsize="64" regnum="58945" group="system"/>
+ <reg name="ICH_AP0R2_EL2" bitsize="64" regnum="58946" group="system"/>
+ <reg name="ICH_AP0R3_EL2" bitsize="64" regnum="58947" group="system"/>
+ <reg name="ICH_AP1R0_EL2" bitsize="64" regnum="58952" group="system"/>
+ <reg name="ICH_AP1R1_EL2" bitsize="64" regnum="58953" group="system"/>
+ <reg name="ICH_AP1R2_EL2" bitsize="64" regnum="58954" group="system"/>
+ <reg name="ICH_AP1R3_EL2" bitsize="64" regnum="58955" group="system"/>
+ <reg name="ICC_SRE_EL2" bitsize="64" regnum="58957" group="system"/>
+ <reg name="ICH_HCR_EL2" bitsize="64" regnum="58968" group="system"/>
+ <reg name="ICH_VTR_EL2" bitsize="64" regnum="58969" group="system"/>
+ <reg name="ICH_MISR_EL2" bitsize="64" regnum="58970" group="system"/>
+ <reg name="ICH_EISR_EL2" bitsize="64" regnum="58971" group="system"/>
+ <reg name="ICH_ELRSR_EL2" bitsize="64" regnum="58973" group="system"/>
+ <reg name="ICH_VMCR_EL2" bitsize="64" regnum="58975" group="system"/>
+ <reg name="ICH_LR0_EL2" bitsize="64" regnum="58976" group="system"/>
+ <reg name="ICH_LR1_EL2" bitsize="64" regnum="58977" group="system"/>
+ <reg name="ICH_LR2_EL2" bitsize="64" regnum="58978" group="system"/>
+ <reg name="ICH_LR3_EL2" bitsize="64" regnum="58979" group="system"/>
+ <reg name="ICH_LR4_EL2" bitsize="64" regnum="58980" group="system"/>
+ <reg name="ICH_LR5_EL2" bitsize="64" regnum="58981" group="system"/>
+ <reg name="ICH_LR6_EL2" bitsize="64" regnum="58982" group="system"/>
+ <reg name="ICH_LR7_EL2" bitsize="64" regnum="58983" group="system"/>
+ <reg name="ICH_LR8_EL2" bitsize="64" regnum="58984" group="system"/>
+ <reg name="ICH_LR9_EL2" bitsize="64" regnum="58985" group="system"/>
+ <reg name="ICH_LR10_EL2" bitsize="64" regnum="58986" group="system"/>
+ <reg name="ICH_LR11_EL2" bitsize="64" regnum="58987" group="system"/>
+ <reg name="ICH_LR12_EL2" bitsize="64" regnum="58988" group="system"/>
+ <reg name="ICH_LR13_EL2" bitsize="64" regnum="58989" group="system"/>
+ <reg name="ICH_LR14_EL2" bitsize="64" regnum="58990" group="system"/>
+ <reg name="ICH_LR15_EL2" bitsize="64" regnum="58991" group="system"/>
+ <reg name="CONTEXTIDR_EL2" bitsize="64" regnum="59009" group="system"/>
+ <reg name="TPIDR_EL2" bitsize="64" regnum="59010" group="system"/>
+ <reg name="SCXTNUM_EL2" bitsize="64" regnum="59015" group="system"/>
+ <reg name="AMEVCNTVOFF00_EL2" bitsize="64" regnum="59072" group="system"/>
+ <reg name="AMEVCNTVOFF01_EL2" bitsize="64" regnum="59073" group="system"/>
+ <reg name="AMEVCNTVOFF02_EL2" bitsize="64" regnum="59074" group="system"/>
+ <reg name="AMEVCNTVOFF03_EL2" bitsize="64" regnum="59075" group="system"/>
+ <reg name="AMEVCNTVOFF04_EL2" bitsize="64" regnum="59076" group="system"/>
+ <reg name="AMEVCNTVOFF05_EL2" bitsize="64" regnum="59077" group="system"/>
+ <reg name="AMEVCNTVOFF06_EL2" bitsize="64" regnum="59078" group="system"/>
+ <reg name="AMEVCNTVOFF07_EL2" bitsize="64" regnum="59079" group="system"/>
+ <reg name="AMEVCNTVOFF08_EL2" bitsize="64" regnum="59080" group="system"/>
+ <reg name="AMEVCNTVOFF09_EL2" bitsize="64" regnum="59081" group="system"/>
+ <reg name="AMEVCNTVOFF010_EL2" bitsize="64" regnum="59082" group="system"/>
+ <reg name="AMEVCNTVOFF011_EL2" bitsize="64" regnum="59083" group="system"/>
+ <reg name="AMEVCNTVOFF012_EL2" bitsize="64" regnum="59084" group="system"/>
+ <reg name="AMEVCNTVOFF013_EL2" bitsize="64" regnum="59085" group="system"/>
+ <reg name="AMEVCNTVOFF014_EL2" bitsize="64" regnum="59086" group="system"/>
+ <reg name="AMEVCNTVOFF015_EL2" bitsize="64" regnum="59087" group="system"/>
+ <reg name="AMEVCNTVOFF10_EL2" bitsize="64" regnum="59088" group="system"/>
+ <reg name="AMEVCNTVOFF11_EL2" bitsize="64" regnum="59089" group="system"/>
+ <reg name="AMEVCNTVOFF12_EL2" bitsize="64" regnum="59090" group="system"/>
+ <reg name="AMEVCNTVOFF13_EL2" bitsize="64" regnum="59091" group="system"/>
+ <reg name="AMEVCNTVOFF14_EL2" bitsize="64" regnum="59092" group="system"/>
+ <reg name="AMEVCNTVOFF15_EL2" bitsize="64" regnum="59093" group="system"/>
+ <reg name="AMEVCNTVOFF16_EL2" bitsize="64" regnum="59094" group="system"/>
+ <reg name="AMEVCNTVOFF17_EL2" bitsize="64" regnum="59095" group="system"/>
+ <reg name="AMEVCNTVOFF18_EL2" bitsize="64" regnum="59096" group="system"/>
+ <reg name="AMEVCNTVOFF19_EL2" bitsize="64" regnum="59097" group="system"/>
+ <reg name="AMEVCNTVOFF110_EL2" bitsize="64" regnum="59098" group="system"/>
+ <reg name="AMEVCNTVOFF111_EL2" bitsize="64" regnum="59099" group="system"/>
+ <reg name="AMEVCNTVOFF112_EL2" bitsize="64" regnum="59100" group="system"/>
+ <reg name="AMEVCNTVOFF113_EL2" bitsize="64" regnum="59101" group="system"/>
+ <reg name="AMEVCNTVOFF114_EL2" bitsize="64" regnum="59102" group="system"/>
+ <reg name="AMEVCNTVOFF115_EL2" bitsize="64" regnum="59103" group="system"/>
+ <reg name="CNTVOFF_EL2" bitsize="64" regnum="59139" group="system"/>
+ <reg name="CNTPOFF_EL2" bitsize="64" regnum="59142" group="system"/>
+ <reg name="CNTHCTL_EL2" bitsize="64" regnum="59144" group="system"/>
+ <reg name="CNTHP_TVAL_EL2" bitsize="64" regnum="59152" group="system"/>
+ <reg name="CNTHP_CTL_EL2" bitsize="64" regnum="59153" group="system"/>
+ <reg name="CNTHP_CVAL_EL2" bitsize="64" regnum="59154" group="system"/>
+ <reg name="CNTHV_TVAL_EL2" bitsize="64" regnum="59160" group="system"/>
+ <reg name="CNTHV_CTL_EL2" bitsize="64" regnum="59161" group="system"/>
+ <reg name="CNTHV_CVAL_EL2" bitsize="64" regnum="59162" group="system"/>
+ <reg name="CNTHVS_TVAL_EL2" bitsize="64" regnum="59168" group="system"/>
+ <reg name="CNTHVS_CTL_EL2" bitsize="64" regnum="59169" group="system"/>
+ <reg name="CNTHVS_CVAL_EL2" bitsize="64" regnum="59170" group="system"/>
+ <reg name="CNTHPS_TVAL_EL2" bitsize="64" regnum="59176" group="system"/>
+ <reg name="CNTHPS_CTL_EL2" bitsize="64" regnum="59177" group="system"/>
+ <reg name="CNTHPS_CVAL_EL2" bitsize="64" regnum="59178" group="system"/>
+ <reg name="SCTLR_EL3" bitsize="64" regnum="61568" group="system"/>
+ <reg name="ACTLR_EL3" bitsize="64" regnum="61569" group="system"/>
+ <reg name="SCR_EL3" bitsize="64" regnum="61576" group="system"/>
+ <reg name="SDER32_EL3" bitsize="64" regnum="61577" group="system"/>
+ <reg name="CPTR_EL3" bitsize="64" regnum="61578" group="system"/>
+ <reg name="ZCR_EL3" bitsize="64" regnum="61584" group="system"/>
+ <reg name="SMCR_EL3" bitsize="64" regnum="61590" group="system"/>
+ <reg name="MDCR_EL3" bitsize="64" regnum="61593" group="system"/>
+ <reg name="TTBR0_EL3" bitsize="64" regnum="61696" group="system"/>
+ <reg name="TCR_EL3" bitsize="64" regnum="61698" group="system"/>
+ <reg name="GPTBR_EL3" bitsize="64" regnum="61708" group="system"/>
+ <reg name="GPCCR_EL3" bitsize="64" regnum="61710" group="system"/>
+ <reg name="SPSR_EL3" bitsize="64" regnum="61952" group="system"/>
+ <reg name="ELR_EL3" bitsize="64" regnum="61953" group="system"/>
+ <reg name="SP_EL2" bitsize="64" regnum="61960" group="system"/>
+ <reg name="AFSR0_EL3" bitsize="64" regnum="62088" group="system"/>
+ <reg name="AFSR1_EL3" bitsize="64" regnum="62089" group="system"/>
+ <reg name="ESR_EL3" bitsize="64" regnum="62096" group="system"/>
+ <reg name="TFSR_EL3" bitsize="64" regnum="62128" group="system"/>
+ <reg name="FAR_EL3" bitsize="64" regnum="62208" group="system"/>
+ <reg name="MFAR_EL3" bitsize="64" regnum="62213" group="system"/>
+ <reg name="MAIR_EL3" bitsize="64" regnum="62736" group="system"/>
+ <reg name="AMAIR_EL3" bitsize="64" regnum="62744" group="system"/>
+ <reg name="MPAM3_EL3" bitsize="64" regnum="62760" group="system"/>
+ <reg name="VBAR_EL3" bitsize="64" regnum="62976" group="system"/>
+ <reg name="RVBAR_EL3" bitsize="64" regnum="62977" group="system"/>
+ <reg name="RMR_EL3" bitsize="64" regnum="62978" group="system"/>
+ <reg name="ICC_CTLR_EL3" bitsize="64" regnum="63076" group="system"/>
+ <reg name="ICC_SRE_EL3" bitsize="64" regnum="63077" group="system"/>
+ <reg name="ICC_IGRPEN1_EL3" bitsize="64" regnum="63079" group="system"/>
+ <reg name="TPIDR_EL3" bitsize="64" regnum="63106" group="system"/>
+ <reg name="SCXTNUM_EL3" bitsize="64" regnum="63111" group="system"/>
+ <reg name="CNTPS_TVAL_EL1" bitsize="64" regnum="65296" group="system"/>
+ <reg name="CNTPS_CTL_EL1" bitsize="64" regnum="65297" group="system"/>
+ <reg name="CNTPS_CVAL_EL1" bitsize="64" regnum="65298" group="system"/>
+</feature>
diff --git a/src/arm/mod.rs b/src/arm/mod.rs
index 96fc404..dbc915a 100644
--- a/src/arm/mod.rs
+++ b/src/arm/mod.rs
@@ -1,6 +1,6 @@
//! Implementations for various ARM architectures.
-use gdbstub::arch::Arch;
+use gdbstub::arch::{Arch, SingleStepGdbBehavior};
pub mod reg;
@@ -30,7 +30,7 @@
}
}
-/// Implements `Arch` for ARMv4T
+/// Implements `Arch` for the ARMv4T architecture
pub enum Armv4t {}
impl Arch for Armv4t {
@@ -42,4 +42,9 @@
fn target_description_xml() -> Option<&'static str> {
Some(r#"<target version="1.0"><architecture>armv4t</architecture></target>"#)
}
+
+ #[inline(always)]
+ fn single_step_gdb_behavior() -> SingleStepGdbBehavior {
+ SingleStepGdbBehavior::Optional
+ }
}
diff --git a/src/arm/reg/arm_core.rs b/src/arm/reg/arm_core.rs
index 179d590..e7ffd80 100644
--- a/src/arm/reg/arm_core.rs
+++ b/src/arm/reg/arm_core.rs
@@ -2,7 +2,7 @@
/// 32-bit ARM core registers.
///
-/// Source: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/arm/arm-core.xml
+/// Source: <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/arm/arm-core.xml>
#[derive(Debug, Default, Clone, Eq, PartialEq)]
pub struct ArmCoreRegs {
/// General purpose registers (R0-R12)
@@ -48,32 +48,38 @@
write_bytes!(&self.cpsr.to_le_bytes());
}
- fn gdb_deserialize(&mut self, bytes: &[u8]) -> Result<(), ()> {
- // ensure bytes.chunks_exact(4) won't panic
- if bytes.len() % 4 != 0 {
+ fn gdb_deserialize(&mut self, mut bytes: &[u8]) -> Result<(), ()> {
+ if bytes.len() != (17 + 25) * 4 {
return Err(());
}
- use core::convert::TryInto;
- let mut regs = bytes
- .chunks_exact(4)
- .map(|c| u32::from_le_bytes(c.try_into().unwrap()));
+ let mut next_reg = || {
+ if bytes.len() < 4 {
+ Err(())
+ } else {
+ use core::convert::TryInto;
+
+ let (next, rest) = bytes.split_at(4);
+ bytes = rest;
+ Ok(u32::from_le_bytes(next.try_into().unwrap()))
+ }
+ };
for reg in self.r.iter_mut() {
- *reg = regs.next().ok_or(())?
+ *reg = next_reg()?
}
- self.sp = regs.next().ok_or(())?;
- self.lr = regs.next().ok_or(())?;
- self.pc = regs.next().ok_or(())?;
+ self.sp = next_reg()?;
+ self.lr = next_reg()?;
+ self.pc = next_reg()?;
// Floating point registers (unused)
for _ in 0..25 {
- regs.next().ok_or(())?;
+ next_reg()?;
}
- self.cpsr = regs.next().ok_or(())?;
+ self.cpsr = next_reg()?;
- if regs.next().is_some() {
+ if next_reg().is_ok() {
return Err(());
}
diff --git a/src/arm/reg/id.rs b/src/arm/reg/id.rs
index c7e11a2..3b91321 100644
--- a/src/arm/reg/id.rs
+++ b/src/arm/reg/id.rs
@@ -1,3 +1,5 @@
+use core::num::NonZeroUsize;
+
use gdbstub::arch::RegId;
/// 32-bit ARM core register identifier.
@@ -21,16 +23,17 @@
}
impl RegId for ArmCoreRegId {
- fn from_raw_id(id: usize) -> Option<(Self, usize)> {
+ fn from_raw_id(id: usize) -> Option<(Self, Option<NonZeroUsize>)> {
let reg = match id {
0..=12 => Self::Gpr(id as u8),
13 => Self::Sp,
14 => Self::Lr,
15 => Self::Pc,
16..=23 => Self::Fpr((id as u8) - 16),
+ 24 => Self::Fps,
25 => Self::Cpsr,
_ => return None,
};
- Some((reg, 4))
+ Some((reg, Some(NonZeroUsize::new(4)?)))
}
}
diff --git a/src/lib.rs b/src/lib.rs
index ccf9b2d..9b3a607 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -53,6 +53,7 @@
#![cfg_attr(not(test), no_std)]
#![deny(missing_docs)]
+pub mod aarch64;
pub mod arm;
pub mod mips;
pub mod msp430;
diff --git a/src/mips/mod.rs b/src/mips/mod.rs
index 7784fe8..7e39cc5 100644
--- a/src/mips/mod.rs
+++ b/src/mips/mod.rs
@@ -1,7 +1,6 @@
//! Implementations for the MIPS architecture.
-use gdbstub::arch::Arch;
-use gdbstub::arch::RegId;
+use gdbstub::arch::{Arch, SingleStepGdbBehavior};
pub mod reg;
@@ -38,48 +37,46 @@
}
/// Implements `Arch` for 32-bit MIPS.
-///
-/// Check out the [module level docs](gdbstub::arch#whats-with-regidimpl) for
-/// more info about the `RegIdImpl` type parameter.
-pub enum Mips<RegIdImpl: RegId = reg::id::MipsRegId<u32>> {
- #[doc(hidden)]
- _Marker(core::marker::PhantomData<RegIdImpl>),
-}
+pub enum Mips {}
+
+/// Implements `Arch` for 32-bit MIPS, with the DSP feature enabled.
+pub enum MipsWithDsp {}
/// Implements `Arch` for 64-bit MIPS.
///
-/// Check out the [module level docs](gdbstub::arch#whats-with-regidimpl) for
-/// more info about the `RegIdImpl` type parameter.
-pub enum Mips64<RegIdImpl: RegId = reg::id::MipsRegId<u64>> {
- #[doc(hidden)]
- _Marker(core::marker::PhantomData<RegIdImpl>),
-}
+/// **NOTE:** Due to GDB client behavior, this arch does _not_ include a
+/// built-in `target.xml` implementation. Consider manually implementing
+/// [`TargetDescriptionXmlOverride`].
+///
+/// See [daniel5151/gdbstub#97](https://github.com/daniel5151/gdbstub/issues/97).
+///
+/// [`TargetDescriptionXmlOverride`]: gdbstub::target::ext::target_description_xml_override::TargetDescriptionXmlOverride
+pub enum Mips64 {}
-/// Implements `Arch` for 32-bit MIPS with the DSP feature enabled.
-pub enum MipsWithDsp {}
-
-/// Implements `Arch` for 64-bit MIPS with the DSP feature enabled.
+/// Implements `Arch` for 64-bit MIPS, with the DSP feature enabled.
+///
+/// **NOTE:** Due to GDB client behavior, this arch does _not_ include a
+/// built-in `target.xml` implementation. Consider manually implementing
+/// [`TargetDescriptionXmlOverride`].
+///
+/// See [daniel5151/gdbstub#97](https://github.com/daniel5151/gdbstub/issues/97).
+///
+/// [`TargetDescriptionXmlOverride`]: gdbstub::target::ext::target_description_xml_override::TargetDescriptionXmlOverride
pub enum Mips64WithDsp {}
-impl<RegIdImpl: RegId> Arch for Mips<RegIdImpl> {
+impl Arch for Mips {
type Usize = u32;
type Registers = reg::MipsCoreRegs<u32>;
- type RegId = RegIdImpl;
+ type RegId = reg::id::MipsRegId<u32>;
type BreakpointKind = MipsBreakpointKind;
fn target_description_xml() -> Option<&'static str> {
Some(r#"<target version="1.0"><architecture>mips</architecture></target>"#)
}
-}
-impl<RegIdImpl: RegId> Arch for Mips64<RegIdImpl> {
- type Usize = u64;
- type Registers = reg::MipsCoreRegs<u64>;
- type RegId = RegIdImpl;
- type BreakpointKind = MipsBreakpointKind;
-
- fn target_description_xml() -> Option<&'static str> {
- Some(r#"<target version="1.0"><architecture>mips64</architecture></target>"#)
+ #[inline(always)]
+ fn single_step_gdb_behavior() -> SingleStepGdbBehavior {
+ SingleStepGdbBehavior::Ignored
}
}
@@ -94,8 +91,31 @@
r#"<target version="1.0"><architecture>mips</architecture><feature name="org.gnu.gdb.mips.dsp"></feature></target>"#,
)
}
+
+ #[inline(always)]
+ fn single_step_gdb_behavior() -> SingleStepGdbBehavior {
+ SingleStepGdbBehavior::Ignored
+ }
}
+#[allow(deprecated)]
+impl Arch for Mips64 {
+ type Usize = u64;
+ type Registers = reg::MipsCoreRegs<u64>;
+ type RegId = reg::id::MipsRegId<u64>;
+ type BreakpointKind = MipsBreakpointKind;
+
+ fn target_description_xml() -> Option<&'static str> {
+ None
+ }
+
+ #[inline(always)]
+ fn single_step_gdb_behavior() -> SingleStepGdbBehavior {
+ SingleStepGdbBehavior::Ignored
+ }
+}
+
+#[allow(deprecated)]
impl Arch for Mips64WithDsp {
type Usize = u64;
type Registers = reg::MipsCoreRegsWithDsp<u64>;
@@ -103,8 +123,11 @@
type BreakpointKind = MipsBreakpointKind;
fn target_description_xml() -> Option<&'static str> {
- Some(
- r#"<target version="1.0"><architecture>mips64</architecture><feature name="org.gnu.gdb.mips.dsp"></feature></target>"#,
- )
+ None
+ }
+
+ #[inline(always)]
+ fn single_step_gdb_behavior() -> SingleStepGdbBehavior {
+ SingleStepGdbBehavior::Ignored
}
}
diff --git a/src/mips/reg/id.rs b/src/mips/reg/id.rs
index 57665c6..99afb3f 100644
--- a/src/mips/reg/id.rs
+++ b/src/mips/reg/id.rs
@@ -1,3 +1,5 @@
+use core::num::NonZeroUsize;
+
use gdbstub::arch::RegId;
/// MIPS register identifier.
@@ -41,10 +43,10 @@
/// Restart register
Restart,
#[doc(hidden)]
- _Size(U),
+ _Size(core::marker::PhantomData<U>),
}
-fn from_raw_id<U>(id: usize) -> Option<(MipsRegId<U>, usize)> {
+fn from_raw_id<U>(id: usize) -> Option<(MipsRegId<U>, Option<NonZeroUsize>)> {
let reg = match id {
0..=31 => MipsRegId::Gpr(id as u8),
32 => MipsRegId::Status,
@@ -63,23 +65,23 @@
76 => MipsRegId::Hi3,
77 => MipsRegId::Lo3,
// `MipsRegId::Dspctl` is the only register that will always be 4 bytes wide
- 78 => return Some((MipsRegId::Dspctl, 4)),
+ 78 => return Some((MipsRegId::Dspctl, Some(NonZeroUsize::new(4)?))),
79 => MipsRegId::Restart,
_ => return None,
};
let ptrsize = core::mem::size_of::<U>();
- Some((reg, ptrsize))
+ Some((reg, Some(NonZeroUsize::new(ptrsize)?)))
}
impl RegId for MipsRegId<u32> {
- fn from_raw_id(id: usize) -> Option<(Self, usize)> {
+ fn from_raw_id(id: usize) -> Option<(Self, Option<NonZeroUsize>)> {
from_raw_id::<u32>(id)
}
}
impl RegId for MipsRegId<u64> {
- fn from_raw_id(id: usize) -> Option<(Self, usize)> {
+ fn from_raw_id(id: usize) -> Option<(Self, Option<NonZeroUsize>)> {
from_raw_id::<u64>(id)
}
}
@@ -104,7 +106,7 @@
let mut i = 0;
let mut sum_reg_sizes = 0;
while let Some((_, size)) = RId::from_raw_id(i) {
- sum_reg_sizes += size;
+ sum_reg_sizes += size.unwrap().get();
i += 1;
}
diff --git a/src/mips/reg/mips.rs b/src/mips/reg/mips.rs
index be14e33..3e2023c 100644
--- a/src/mips/reg/mips.rs
+++ b/src/mips/reg/mips.rs
@@ -9,7 +9,7 @@
///
/// The register width is set to `u32` or `u64` based on the `<U>` type.
///
-/// Source: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/mips-cpu.xml
+/// Source: <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/mips-cpu.xml>
#[derive(Debug, Default, Clone, Eq, PartialEq)]
pub struct MipsCoreRegs<U> {
/// General purpose registers (R0-R31)
@@ -28,7 +28,7 @@
/// MIPS CP0 (coprocessor 0) registers.
///
-/// Source: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/mips-cp0.xml
+/// Source: <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/mips-cp0.xml>
#[derive(Debug, Default, Clone, Eq, PartialEq)]
pub struct MipsCp0Regs<U> {
/// Status register (regnum 32)
@@ -41,7 +41,7 @@
/// MIPS FPU registers.
///
-/// Source: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/mips-fpu.xml
+/// Source: <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/mips-fpu.xml>
#[derive(Debug, Default, Clone, Eq, PartialEq)]
pub struct MipsFpuRegs<U> {
/// FP registers (F0-F31) starting at regnum 38
@@ -54,7 +54,7 @@
/// MIPS DSP registers.
///
-/// Source: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/mips-dsp.xml
+/// Source: <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/mips-dsp.xml>
#[derive(Debug, Default, Clone, Eq, PartialEq)]
pub struct MipsDspRegs<U> {
/// High 1 register (regnum 72)
@@ -71,7 +71,7 @@
pub lo3: U,
/// DSP Control register (regnum 78)
/// Note: This register will always be 32-bit regardless of the target
- /// https://sourceware.org/gdb/current/onlinedocs/gdb/MIPS-Features.html#MIPS-Features
+ /// <https://sourceware.org/gdb/current/onlinedocs/gdb/MIPS-Features.html#MIPS-Features>
pub dspctl: u32,
/// Restart register (regnum 79)
pub restart: U,
@@ -79,7 +79,7 @@
/// MIPS core and DSP registers.
///
-/// Source: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/mips-dsp-linux.xml
+/// Source: <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/mips-dsp-linux.xml>
#[derive(Debug, Default, Clone, Eq, PartialEq)]
pub struct MipsCoreRegsWithDsp<U> {
/// Core registers
@@ -132,7 +132,7 @@
// Write FPRs
for reg in self.fpu.r.iter() {
- write_le_bytes!(®);
+ write_le_bytes!(reg);
}
// Write FCSR and FIR registers
diff --git a/src/msp430/mod.rs b/src/msp430/mod.rs
index 456ce18..dd90c6a 100644
--- a/src/msp430/mod.rs
+++ b/src/msp430/mod.rs
@@ -1,26 +1,43 @@
//! Implementations for the TI-MSP430 family of MCUs.
-use gdbstub::arch::Arch;
-use gdbstub::arch::RegId;
+use gdbstub::arch::{Arch, SingleStepGdbBehavior};
pub mod reg;
/// Implements `Arch` for standard 16-bit TI-MSP430 MCUs.
-///
-/// Check out the [module level docs](gdbstub::arch#whats-with-regidimpl) for
-/// more info about the `RegIdImpl` type parameter.
-pub enum Msp430<RegIdImpl: RegId = reg::id::Msp430RegId> {
- #[doc(hidden)]
- _Marker(core::marker::PhantomData<RegIdImpl>),
-}
+pub struct Msp430 {}
-impl<RegIdImpl: RegId> Arch for Msp430<RegIdImpl> {
+impl Arch for Msp430 {
type Usize = u16;
- type Registers = reg::Msp430Regs;
- type RegId = RegIdImpl;
+ type Registers = reg::Msp430Regs<u16>;
+ type RegId = reg::id::Msp430RegId<u16>;
type BreakpointKind = usize;
fn target_description_xml() -> Option<&'static str> {
Some(r#"<target version="1.0"><architecture>msp430</architecture></target>"#)
}
+
+ #[inline(always)]
+ fn single_step_gdb_behavior() -> SingleStepGdbBehavior {
+ SingleStepGdbBehavior::Required
+ }
+}
+
+/// Implements `Arch` for 20-bit TI-MSP430 MCUs (CPUX).
+pub struct Msp430X {}
+
+impl Arch for Msp430X {
+ type Usize = u32;
+ type Registers = reg::Msp430Regs<u32>;
+ type RegId = reg::id::Msp430RegId<u32>;
+ type BreakpointKind = usize;
+
+ fn target_description_xml() -> Option<&'static str> {
+ Some(r#"<target version="1.0"><architecture>msp430x</architecture></target>"#)
+ }
+
+ #[inline(always)]
+ fn single_step_gdb_behavior() -> SingleStepGdbBehavior {
+ SingleStepGdbBehavior::Required
+ }
}
diff --git a/src/msp430/reg/id.rs b/src/msp430/reg/id.rs
index 1c38763..679c1cc 100644
--- a/src/msp430/reg/id.rs
+++ b/src/msp430/reg/id.rs
@@ -1,3 +1,5 @@
+use core::num::NonZeroUsize;
+
use gdbstub::arch::RegId;
/// TI-MSP430 register identifier.
@@ -6,7 +8,7 @@
/// The best file to reference is [msp430-tdep.c](https://github.com/bminor/binutils-gdb/blob/master/gdb/msp430-tdep.c).
#[derive(Debug, Clone, Copy)]
#[non_exhaustive]
-pub enum Msp430RegId {
+pub enum Msp430RegId<U> {
/// Program Counter (R0)
Pc,
/// Stack Pointer (R1)
@@ -17,19 +19,33 @@
Cg,
/// General Purpose Registers (R4-R15)
Gpr(u8),
+ #[doc(hidden)]
+ _Size(core::marker::PhantomData<U>),
}
-impl RegId for Msp430RegId {
- fn from_raw_id(id: usize) -> Option<(Self, usize)> {
- let reg = match id {
- 0 => Self::Pc,
- 1 => Self::Sp,
- 2 => Self::Sr,
- 3 => Self::Cg,
- 4..=15 => Self::Gpr((id as u8) - 4),
- _ => return None,
- };
- Some((reg, 2))
+fn from_raw_id<U>(id: usize) -> Option<(Msp430RegId<U>, Option<NonZeroUsize>)> {
+ let reg = match id {
+ 0 => Msp430RegId::Pc,
+ 1 => Msp430RegId::Sp,
+ 2 => Msp430RegId::Sr,
+ 3 => Msp430RegId::Cg,
+ 4..=15 => Msp430RegId::Gpr((id as u8) - 4),
+ _ => return None,
+ };
+
+ let ptrsize = core::mem::size_of::<U>();
+ Some((reg, Some(NonZeroUsize::new(ptrsize)?)))
+}
+
+impl RegId for Msp430RegId<u16> {
+ fn from_raw_id(id: usize) -> Option<(Self, Option<NonZeroUsize>)> {
+ from_raw_id::<u16>(id)
+ }
+}
+
+impl RegId for Msp430RegId<u32> {
+ fn from_raw_id(id: usize) -> Option<(Self, Option<NonZeroUsize>)> {
+ from_raw_id::<u32>(id)
}
}
@@ -51,13 +67,13 @@
// The `Msp430Regs` implementation does not increment the size for
// the CG register since it will always be the constant zero.
- serialized_data_len += 4;
+ serialized_data_len += RId::from_raw_id(3).unwrap().1.unwrap().get();
// Accumulate register sizes returned by `from_raw_id`.
let mut i = 0;
let mut sum_reg_sizes = 0;
while let Some((_, size)) = RId::from_raw_id(i) {
- sum_reg_sizes += size;
+ sum_reg_sizes += size.unwrap().get();
i += 1;
}
@@ -66,6 +82,11 @@
#[test]
fn test_msp430() {
- test::<crate::msp430::reg::Msp430Regs, crate::msp430::reg::id::Msp430RegId>()
+ test::<crate::msp430::reg::Msp430Regs<u16>, crate::msp430::reg::id::Msp430RegId<u16>>()
+ }
+
+ #[test]
+ fn test_msp430x() {
+ test::<crate::msp430::reg::Msp430Regs<u32>, crate::msp430::reg::id::Msp430RegId<u32>>()
}
}
diff --git a/src/msp430/reg/msp430.rs b/src/msp430/reg/msp430.rs
index 652fc1b..89f04e1 100644
--- a/src/msp430/reg/msp430.rs
+++ b/src/msp430/reg/msp430.rs
@@ -1,60 +1,74 @@
-use gdbstub::arch::Registers;
+use num_traits::PrimInt;
-/// 16-bit TI-MSP430 registers.
+use gdbstub::arch::Registers;
+use gdbstub::internal::LeBytes;
+
+/// TI-MSP430 registers.
+///
+/// The register width is set based on the `<U>` type. For 16-bit MSP430 CPUs
+/// this should be `u16` and for 20-bit MSP430 CPUs (CPUX) this should be `u32`.
#[derive(Debug, Default, Clone, Eq, PartialEq)]
-pub struct Msp430Regs {
+pub struct Msp430Regs<U> {
/// Program Counter (R0)
- pub pc: u16,
+ pub pc: U,
/// Stack Pointer (R1)
- pub sp: u16,
+ pub sp: U,
/// Status Register (R2)
- pub sr: u16,
+ pub sr: U,
/// General Purpose Registers (R4-R15)
- pub r: [u16; 11],
+ pub r: [U; 12],
}
-impl Registers for Msp430Regs {
- type ProgramCounter = u16;
+impl<U> Registers for Msp430Regs<U>
+where
+ U: PrimInt + LeBytes + Default + core::fmt::Debug,
+{
+ type ProgramCounter = U;
fn pc(&self) -> Self::ProgramCounter {
self.pc
}
fn gdb_serialize(&self, mut write_byte: impl FnMut(Option<u8>)) {
- macro_rules! write_bytes {
- ($bytes:expr) => {
- for b in $bytes {
- write_byte(Some(*b))
+ macro_rules! write_le_bytes {
+ ($value:expr) => {
+ let mut buf = [0; 4];
+ // infallible (register size a maximum of 32-bits)
+ let len = $value.to_le_bytes(&mut buf).unwrap();
+ let buf = &buf[..len];
+ for b in buf {
+ write_byte(Some(*b));
}
};
}
- write_bytes!(&self.pc.to_le_bytes());
- write_bytes!(&self.sp.to_le_bytes());
- write_bytes!(&self.sr.to_le_bytes());
- (0..4).for_each(|_| write_byte(None)); // Constant Generator (CG/R3)
+ write_le_bytes!(&self.pc);
+ write_le_bytes!(&self.sp);
+ write_le_bytes!(&self.sr);
+ (0..core::mem::size_of::<U>()).for_each(|_| write_byte(None)); // Constant Generator (CG/R3)
for reg in self.r.iter() {
- write_bytes!(®.to_le_bytes());
+ write_le_bytes!(reg);
}
}
fn gdb_deserialize(&mut self, bytes: &[u8]) -> Result<(), ()> {
- // ensure bytes.chunks_exact(2) won't panic
- if bytes.len() % 2 != 0 {
+ let ptrsize = core::mem::size_of::<U>();
+
+ // Ensure bytes contains enough data for all 16 registers
+ if bytes.len() < ptrsize * 16 {
return Err(());
}
- use core::convert::TryInto;
let mut regs = bytes
- .chunks_exact(2)
- .map(|c| u16::from_le_bytes(c.try_into().unwrap()));
+ .chunks_exact(ptrsize)
+ .map(|c| U::from_le_bytes(c).unwrap());
self.pc = regs.next().ok_or(())?;
self.sp = regs.next().ok_or(())?;
self.sr = regs.next().ok_or(())?;
// Constant Generator (CG/R3) should always be 0
- if regs.next().ok_or(())? != 0 {
+ if regs.next().ok_or(())? != U::zero() {
return Err(());
}
diff --git a/src/ppc/mod.rs b/src/ppc/mod.rs
index 60beed3..5351ef4 100644
--- a/src/ppc/mod.rs
+++ b/src/ppc/mod.rs
@@ -1,7 +1,6 @@
//! Implementations for various PowerPC architectures.
-use gdbstub::arch::Arch;
-use gdbstub::arch::RegId;
+use gdbstub::arch::{Arch, RegId, SingleStepGdbBehavior};
pub mod reg;
@@ -25,4 +24,9 @@
r#"<target version="1.0"><architecture>powerpc:common</architecture><feature name="org.gnu.gdb.power.core"></feature><feature name="org.gnu.gdb.power.fpu"></feature><feature name="org.gnu.gdb.power.altivec"></feature></target>"#,
)
}
+
+ #[inline(always)]
+ fn single_step_gdb_behavior() -> SingleStepGdbBehavior {
+ SingleStepGdbBehavior::Required
+ }
}
diff --git a/src/ppc/reg/common.rs b/src/ppc/reg/common.rs
index 45bdb1c..c84a87b 100644
--- a/src/ppc/reg/common.rs
+++ b/src/ppc/reg/common.rs
@@ -7,10 +7,10 @@
/// 32-bit PowerPC core registers, FPU registers, and AltiVec SIMD registers.
///
/// Sources:
-/// * https://github.com/bminor/binutils-gdb/blob/master/gdb/features/rs6000/powerpc-altivec32.xml
-/// * https://github.com/bminor/binutils-gdb/blob/master/gdb/features/rs6000/power-core.xml
-/// * https://github.com/bminor/binutils-gdb/blob/master/gdb/features/rs6000/power-fpu.xml
-/// * https://github.com/bminor/binutils-gdb/blob/master/gdb/features/rs6000/power-altivec.xml
+/// * <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/rs6000/powerpc-altivec32.xml>
+/// * <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/rs6000/power-core.xml>
+/// * <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/rs6000/power-fpu.xml>
+/// * <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/rs6000/power-altivec.xml>
#[derive(Debug, Default, Clone, PartialEq)]
pub struct PowerPcCommonRegs {
/// General purpose registers
diff --git a/src/riscv/mod.rs b/src/riscv/mod.rs
index 62ce98e..d5c6c67 100644
--- a/src/riscv/mod.rs
+++ b/src/riscv/mod.rs
@@ -2,7 +2,7 @@
//!
//! *Note*: currently only supports integer versions of the ISA.
-use gdbstub::arch::Arch;
+use gdbstub::arch::{Arch, SingleStepGdbBehavior};
pub mod reg;
@@ -19,7 +19,12 @@
type BreakpointKind = usize;
fn target_description_xml() -> Option<&'static str> {
- Some(r#"<target version="1.0"><architecture>riscv</architecture></target>"#)
+ Some(r#"<target version="1.0"><architecture>riscv:rv32</architecture></target>"#)
+ }
+
+ #[inline(always)]
+ fn single_step_gdb_behavior() -> SingleStepGdbBehavior {
+ SingleStepGdbBehavior::Ignored
}
}
@@ -30,6 +35,11 @@
type BreakpointKind = usize;
fn target_description_xml() -> Option<&'static str> {
- Some(r#"<target version="1.0"><architecture>riscv64</architecture></target>"#)
+ Some(r#"<target version="1.0"><architecture>riscv:rv64</architecture></target>"#)
+ }
+
+ #[inline(always)]
+ fn single_step_gdb_behavior() -> SingleStepGdbBehavior {
+ SingleStepGdbBehavior::Ignored
}
}
diff --git a/src/riscv/reg/id.rs b/src/riscv/reg/id.rs
index b6e589d..621231e 100644
--- a/src/riscv/reg/id.rs
+++ b/src/riscv/reg/id.rs
@@ -1,3 +1,5 @@
+use core::num::NonZeroUsize;
+
use gdbstub::arch::RegId;
/// RISC-V Register identifier.
@@ -22,10 +24,10 @@
macro_rules! impl_riscv_reg_id {
($usize:ty) => {
impl RegId for RiscvRegId<$usize> {
- fn from_raw_id(id: usize) -> Option<(Self, usize)> {
+ fn from_raw_id(id: usize) -> Option<(Self, Option<NonZeroUsize>)> {
const USIZE: usize = core::mem::size_of::<$usize>();
- let reg_size = match id {
+ let (id, size) = match id {
0..=31 => (Self::Gpr(id as u8), USIZE),
32 => (Self::Pc, USIZE),
33..=64 => (Self::Fpr((id - 33) as u8), USIZE),
@@ -33,7 +35,8 @@
4161 => (Self::Priv, 1),
_ => return None,
};
- Some(reg_size)
+
+ Some((id, Some(NonZeroUsize::new(size)?)))
}
}
};
diff --git a/src/riscv/reg/riscv.rs b/src/riscv/reg/riscv.rs
index 9875ad2..15075f2 100644
--- a/src/riscv/reg/riscv.rs
+++ b/src/riscv/reg/riscv.rs
@@ -10,7 +10,7 @@
/// Useful links:
/// * [GNU binutils-gdb XML descriptions](https://github.com/bminor/binutils-gdb/blob/master/gdb/features/riscv)
/// * [riscv-tdep.h](https://github.com/bminor/binutils-gdb/blob/master/gdb/riscv-tdep.h)
-#[derive(Debug, Default, Clone, PartialEq)]
+#[derive(Debug, Default, Clone, PartialEq, Eq)]
pub struct RiscvCoreRegs<U> {
/// General purpose registers (x0-x31)
pub x: [U; 32],
diff --git a/src/x86/mod.rs b/src/x86/mod.rs
index e7fec5c..d1c7a61 100644
--- a/src/x86/mod.rs
+++ b/src/x86/mod.rs
@@ -1,24 +1,17 @@
//! Implementations for various x86 architectures.
-use gdbstub::arch::Arch;
-use gdbstub::arch::RegId;
+use gdbstub::arch::{Arch, SingleStepGdbBehavior};
pub mod reg;
/// Implements `Arch` for 64-bit x86 + SSE Extensions.
-///
-/// Check out the [module level docs](gdbstub::arch#whats-with-regidimpl) for
-/// more info about the `RegIdImpl` type parameter.
#[allow(non_camel_case_types, clippy::upper_case_acronyms)]
-pub enum X86_64_SSE<RegIdImpl: RegId = reg::id::X86_64CoreRegId> {
- #[doc(hidden)]
- _Marker(core::marker::PhantomData<RegIdImpl>),
-}
+pub enum X86_64_SSE {}
-impl<RegIdImpl: RegId> Arch for X86_64_SSE<RegIdImpl> {
+impl Arch for X86_64_SSE {
type Usize = u64;
type Registers = reg::X86_64CoreRegs;
- type RegId = RegIdImpl;
+ type RegId = reg::id::X86_64CoreRegId;
type BreakpointKind = usize;
fn target_description_xml() -> Option<&'static str> {
@@ -26,22 +19,21 @@
r#"<target version="1.0"><architecture>i386:x86-64</architecture><feature name="org.gnu.gdb.i386.sse"></feature></target>"#,
)
}
+
+ #[inline(always)]
+ fn single_step_gdb_behavior() -> SingleStepGdbBehavior {
+ SingleStepGdbBehavior::Required
+ }
}
/// Implements `Arch` for 32-bit x86 + SSE Extensions.
-///
-/// Check out the [module level docs](gdbstub::arch#whats-with-regidimpl) for
-/// more info about the `RegIdImpl` type parameter.
#[allow(non_camel_case_types, clippy::upper_case_acronyms)]
-pub enum X86_SSE<RegIdImpl: RegId = reg::id::X86CoreRegId> {
- #[doc(hidden)]
- _Marker(core::marker::PhantomData<RegIdImpl>),
-}
+pub enum X86_SSE {}
-impl<RegIdImpl: RegId> Arch for X86_SSE<RegIdImpl> {
+impl Arch for X86_SSE {
type Usize = u32;
type Registers = reg::X86CoreRegs;
- type RegId = RegIdImpl;
+ type RegId = reg::id::X86CoreRegId;
type BreakpointKind = usize;
fn target_description_xml() -> Option<&'static str> {
@@ -49,4 +41,9 @@
r#"<target version="1.0"><architecture>i386:intel</architecture><feature name="org.gnu.gdb.i386.sse"></feature></target>"#,
)
}
+
+ #[inline(always)]
+ fn single_step_gdb_behavior() -> SingleStepGdbBehavior {
+ SingleStepGdbBehavior::Required
+ }
}
diff --git a/src/x86/reg/core32.rs b/src/x86/reg/core32.rs
index d91e707..105b380 100644
--- a/src/x86/reg/core32.rs
+++ b/src/x86/reg/core32.rs
@@ -6,9 +6,9 @@
/// 32-bit x86 core registers (+ SSE extensions).
///
-/// Source: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/32bit-core.xml
-/// Additionally: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/32bit-sse.xml
-#[derive(Debug, Default, Clone, PartialEq)]
+/// Source: <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/32bit-core.xml>
+/// Additionally: <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/32bit-sse.xml>
+#[derive(Debug, Default, Clone, PartialEq, Eq)]
pub struct X86CoreRegs {
/// Accumulator
pub eax: u32,
diff --git a/src/x86/reg/core64.rs b/src/x86/reg/core64.rs
index e0fc5af..f61d2d5 100644
--- a/src/x86/reg/core64.rs
+++ b/src/x86/reg/core64.rs
@@ -6,9 +6,9 @@
/// 64-bit x86 core registers (+ SSE extensions).
///
-/// Source: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/64bit-core.xml
-/// Additionally: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/64bit-sse.xml
-#[derive(Debug, Default, Clone, PartialEq)]
+/// Source: <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/64bit-core.xml>
+/// Additionally: <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/64bit-sse.xml>
+#[derive(Debug, Default, Clone, PartialEq, Eq)]
pub struct X86_64CoreRegs {
/// RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, r8-r15
pub regs: [u64; 16],
diff --git a/src/x86/reg/id.rs b/src/x86/reg/id.rs
index 03de64b..d1f5462 100644
--- a/src/x86/reg/id.rs
+++ b/src/x86/reg/id.rs
@@ -1,3 +1,5 @@
+use core::num::NonZeroUsize;
+
use gdbstub::arch::RegId;
/// FPU register identifier.
@@ -77,8 +79,8 @@
/// 32-bit x86 core + SSE register identifier.
///
-/// Source: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/32bit-core.xml
-/// Additionally: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/32bit-sse.xml
+/// Source: <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/32bit-core.xml>
+/// Additionally: <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/32bit-sse.xml>
#[derive(Debug, Clone, Copy)]
#[non_exhaustive]
pub enum X86CoreRegId {
@@ -115,10 +117,10 @@
}
impl RegId for X86CoreRegId {
- fn from_raw_id(id: usize) -> Option<(Self, usize)> {
+ fn from_raw_id(id: usize) -> Option<(Self, Option<NonZeroUsize>)> {
use self::X86CoreRegId::*;
- let r = match id {
+ let (r, sz): (X86CoreRegId, usize) = match id {
0 => (Eax, 4),
1 => (Ecx, 4),
2 => (Edx, 4),
@@ -136,14 +138,15 @@
40 => (Mxcsr, 4),
_ => return None,
};
- Some(r)
+
+ Some((r, Some(NonZeroUsize::new(sz)?)))
}
}
/// 64-bit x86 core + SSE register identifier.
///
-/// Source: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/64bit-core.xml
-/// Additionally: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/64bit-sse.xml
+/// Source: <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/64bit-core.xml>
+/// Additionally: <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/64bit-sse.xml>
#[derive(Debug, Clone, Copy)]
#[non_exhaustive]
pub enum X86_64CoreRegId {
@@ -167,13 +170,13 @@
}
impl RegId for X86_64CoreRegId {
- fn from_raw_id(id: usize) -> Option<(Self, usize)> {
+ fn from_raw_id(id: usize) -> Option<(Self, Option<NonZeroUsize>)> {
use self::X86_64CoreRegId::*;
- let r = match id {
+ let (r, sz): (X86_64CoreRegId, usize) = match id {
0..=15 => (Gpr(id as u8), 8),
- 16 => (Rip, 4),
- 17 => (Eflags, 8),
+ 16 => (Rip, 8),
+ 17 => (Eflags, 4),
18..=23 => (Segment(X86SegmentRegId::from_u8(id as u8 - 18)?), 4),
24..=31 => (St(id as u8 - 24), 10),
32..=39 => (Fpu(X87FpuInternalRegId::from_u8(id as u8 - 32)?), 4),
@@ -181,7 +184,8 @@
56 => (Mxcsr, 4),
_ => return None,
};
- Some(r)
+
+ Some((r, Some(NonZeroUsize::new(sz)?)))
}
}
@@ -208,7 +212,7 @@
let mut i = 0;
let mut sum_reg_sizes = 0;
while let Some((_, size)) = RId::from_raw_id(i) {
- sum_reg_sizes += size;
+ sum_reg_sizes += size.unwrap().get();
i += 1;
}
diff --git a/src/x86/reg/mod.rs b/src/x86/reg/mod.rs
index bac64cd..6397e70 100644
--- a/src/x86/reg/mod.rs
+++ b/src/x86/reg/mod.rs
@@ -17,7 +17,7 @@
pub type F80 = [u8; 10];
/// FPU registers
-#[derive(Debug, Default, Clone, PartialEq)]
+#[derive(Debug, Default, Clone, PartialEq, Eq)]
pub struct X87FpuInternalRegs {
/// Floating-point control register
pub fctrl: u32,
@@ -91,8 +91,8 @@
/// x86 segment registers.
///
-/// Source: https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/64bit-core.xml
-#[derive(Debug, Default, Clone, PartialEq)]
+/// Source: <https://github.com/bminor/binutils-gdb/blob/master/gdb/features/i386/64bit-core.xml>
+#[derive(Debug, Default, Clone, PartialEq, Eq)]
pub struct X86SegmentRegs {
/// Code Segment
pub cs: u32,
