src/llvm-project/llvm/test/CodeGen/X86/GlobalISel/legalize-ptr-add.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64
# RUN: llc -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86

--- |
  define void @test_gep_i8c(ptr %addr) {
    %arrayidx = getelementptr i32, ptr undef, i8 5
    ret void
  }
  define void @test_gep_i8(ptr %addr, i8 %ofs) {
    %arrayidx = getelementptr i32, ptr undef, i8 %ofs
    ret void
  }

  define void @test_gep_i16c(ptr %addr) {
    %arrayidx = getelementptr i32, ptr undef, i16 5
    ret void
  }
  define void @test_gep_i16(ptr %addr, i16 %ofs) {
    %arrayidx = getelementptr i32, ptr undef, i16 %ofs
    ret void
  }

  define void @test_gep_i32c(ptr %addr) {
    %arrayidx = getelementptr i32, ptr undef, i32 5
    ret void
  }
  define void @test_gep_i32(ptr %addr, i32 %ofs) {
    %arrayidx = getelementptr i32, ptr undef, i32 %ofs
    ret void
  }

  define void @test_gep_i64c(ptr %addr) {
    %arrayidx = getelementptr i32, ptr undef, i64 5
    ret void
  }
  define void @test_gep_i64(ptr %addr, i64 %ofs) {
    %arrayidx = getelementptr i32, ptr undef, i64 %ofs
    ret void
  }
...
---
name:            test_gep_i8c
legalized:       false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    ; CHECK-LABEL: name: test_gep_i8c
    ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
    ; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
    ; CHECK-NEXT: RET 0
    %0(p0) = IMPLICIT_DEF
    %1(s8) = G_CONSTANT i8 20
    %2(p0) = G_PTR_ADD %0, %1(s8)
    G_STORE %2, %0 :: (store (p0) into %ir.addr)
    RET 0
...
---
name:            test_gep_i8
legalized:       false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    ; CHECK-LABEL: name: test_gep_i8
    ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s8) = IMPLICIT_DEF
    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[DEF1]](s8)
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[SEXT]](s32)
    ; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
    ; CHECK-NEXT: RET 0
    %0(p0) = IMPLICIT_DEF
    %1(s8) = IMPLICIT_DEF
    %2(p0) = G_PTR_ADD %0, %1(s8)
    G_STORE %2, %0 :: (store (p0) into %ir.addr)
    RET 0
...
---
name:            test_gep_i16c
legalized:       false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    ; CHECK-LABEL: name: test_gep_i16c
    ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
    ; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
    ; CHECK-NEXT: RET 0
    %0(p0) = IMPLICIT_DEF
    %1(s16) = G_CONSTANT i16 20
    %2(p0) = G_PTR_ADD %0, %1(s16)
    G_STORE %2, %0 :: (store (p0) into %ir.addr)
    RET 0
...
---
name:            test_gep_i16
legalized:       false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    ; CHECK-LABEL: name: test_gep_i16
    ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s16) = IMPLICIT_DEF
    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[DEF1]](s16)
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[SEXT]](s32)
    ; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
    ; CHECK-NEXT: RET 0
    %0(p0) = IMPLICIT_DEF
    %1(s16) = IMPLICIT_DEF
    %2(p0) = G_PTR_ADD %0, %1(s16)
    G_STORE %2, %0 :: (store (p0) into %ir.addr)
    RET 0
...
---
name:            test_gep_i32c
legalized:       false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    ; CHECK-LABEL: name: test_gep_i32c
    ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
    ; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
    ; CHECK-NEXT: RET 0
    %0(p0) = IMPLICIT_DEF
    %1(s32) = G_CONSTANT i32 20
    %2(p0) = G_PTR_ADD %0, %1(s32)
    G_STORE %2, %0 :: (store (p0) into %ir.addr)
    RET 0
...
---
name:            test_gep_i32
legalized:       false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    ; CHECK-LABEL: name: test_gep_i32
    ; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[DEF1]](s32)
    ; CHECK-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
    ; CHECK-NEXT: RET 0
    %0(p0) = IMPLICIT_DEF
    %1(s32) = IMPLICIT_DEF
    %2(p0) = G_PTR_ADD %0, %1(s32)
    G_STORE %2, %0 :: (store (p0) into %ir.addr)
    RET 0
...
---
name:            test_gep_i64c
legalized:       false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    ; X64-LABEL: name: test_gep_i64c
    ; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
    ; X64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 20
    ; X64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s64)
    ; X64-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
    ; X64-NEXT: RET 0
    ; X86-LABEL: name: test_gep_i64c
    ; X86: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
    ; X86-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
    ; X86-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
    ; X86-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
    ; X86-NEXT: RET 0
    %0(p0) = IMPLICIT_DEF
    %1(s64) = G_CONSTANT i64 20
    %2(p0) = G_PTR_ADD %0, %1(s64)
    G_STORE %2, %0 :: (store (p0) into %ir.addr)
    RET 0
...
---
name:            test_gep_i64
legalized:       false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    ; X64-LABEL: name: test_gep_i64
    ; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
    ; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
    ; X64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[DEF1]](s64)
    ; X64-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
    ; X64-NEXT: RET 0
    ; X86-LABEL: name: test_gep_i64
    ; X86: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
    ; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
    ; X86-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF1]](s64)
    ; X86-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[TRUNC]](s32)
    ; X86-NEXT: G_STORE [[PTR_ADD]](p0), [[DEF]](p0) :: (store (p0) into %ir.addr)
    ; X86-NEXT: RET 0
    %0(p0) = IMPLICIT_DEF
    %1(s64) = IMPLICIT_DEF
    %2(p0) = G_PTR_ADD %0, %1(s64)
    G_STORE %2, %0 :: (store (p0) into %ir.addr)
    RET 0
...