src/llvm-project/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/join-loopexit-gmir.mir

# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
# CHECK-LABEL: MachineUniformityInfo for function: test

# CHECK-LABEL: BLOCK bb.0
# CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s1) = G_ICMP intpred(eq), %{{[0-9]*}}:_(s32), %{{[0-9]*}}:_

# CHECK-LABEL: BLOCK bb.1
# CHECK-NOT: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32) = G_PHI %{{[0-9]*}}:_(s32), %bb.0, %{{[0-9]*}}:_(s32), %bb.2
# CHECK:  DIVERGENT: G_BRCOND %{{[0-9]*}}:_(s1), %bb.3

# CHECK-LABEL: BLOCK bb.2
# CHECK-NOT: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s32), %{{[0-9]*}}:_(s1) = G_UADDO_
# CHECK-NOT: DIVERGENT: G_BRCOND %{{[0-9]*}}:_(s1), %bb.3

# CHECK-LABEL: BLOCK bb.3
# CHECK: DIVERGENT: %{{[0-9]*}}: %{{[0-9]*}}:_(s1) = G_PHI %{{[0-9]*}}:_(s1), %bb.1, %{{[0-9]*}}:_(s1), %bb.2
# CHECK: DIVERGENT: G_BRCOND %{{[0-9]*}}:_(s1), %bb.4
# CHECK: DIVERGENT: G_BR %bb.5

---
name:            test
tracksRegLiveness: true
body:             |
  bb.0:
    successors: %bb.1

    %2:_(s1) = G_CONSTANT i1 true
    %3:_(s1) = G_CONSTANT i1 false
    %1:_(s32) = G_CONSTANT i32 0
    %20:_(s32) = G_CONSTANT i32 7
    %5:_(s32) = G_CONSTANT i32 -1
    %4:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)
    %6:_(s1) = G_ICMP intpred(eq), %4(s32), %5

  bb.1:
    successors: %bb.2, %bb.3

    %8:_(s32) = G_PHI %20(s32), %bb.0, %21(s32), %bb.2
    G_BRCOND %6(s1), %bb.3   ; Entrance to loop is divergent
  bb.2:
    successors: %bb.3, %bb.1

    %21:_(s32), %22:_(s1) = G_UADDO %8, %5
    %23:_(s1) = G_ICMP intpred(eq), %21(s32), %1
    G_BRCOND %23(s1), %bb.3
    G_BR %bb.1

  bb.3:
    %31:_(s1) = G_PHI %2(s1), %bb.1, %3(s1), %bb.2
    S_ENDPGM 0
    G_BRCOND %31(s1), %bb.4
    G_BR %bb.5
  bb.4:
    G_BR %bb.5
  bb.5:

...