src/llvm-project/llvm/test/CodeGen/X86/peephole-test-after-add.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - %s -mtriple=x86_64-unknown-linux-gnu --run-pass=peephole-opt | FileCheck %s

# Test that TEST64rr is erased in `test_erased`, and kept in `test_not_erased_when_sf_used`
# and `test_not_erased_when_eflags_change`.

--- |
  ; ModuleID = 'tmp.ll'
  source_filename = "tmp.ll"
  target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"

  define i64 @test_erased(ptr %0, i64 %1, i64 %2) {
    %4 = load i64, ptr %0, align 8
    %5 = and i64 %4, 3
    %6 = icmp eq i64 %5, 0
    %7 = select i1 %6, i64 %1, i64 %5
    store i64 %7, ptr %0, align 8
    ret i64 %5
  }

  define i64 @test_not_erased_when_sf_used(ptr %0, i64 %1, i64 %2, i64 %3) {
    %5 = load i64, ptr %0, align 8
    %6 = and i64 %5, 3
    %7 = icmp slt i64 %6, 0
    %8 = select i1 %7, i64 %1, i64 %6
    store i64 %8, ptr %0, align 8
    ret i64 %5
  }

  define void @test_not_erased_when_eflags_change(ptr %0, i64 %1, i64 %2, i64 %3, ptr %4) {
    %6 = load i64, ptr %0, align 8
    %7 = and i64 %6, 3
    %8 = xor i64 %3, 5
    %9 = icmp eq i64 %7, 0
    %10 = select i1 %9, i64 %1, i64 %7
    store i64 %10, ptr %0, align 8
    store i64 %8, ptr %4, align 8
    ret void
  }

  define i16 @erase_test16(i16 %0, i16 %1, ptr nocapture %2) {
  entry:
    %3 = icmp ne i16 %0, 0
    %4 = and i16 %1, 123
    %5 = icmp eq i16 %4, 0
    %6 = select i1 %3, i1 %5, i1 false
    br i1 %6, label %if.then, label %if.end

  if.then:                                          ; preds = %entry
    store i16 %0, ptr %2, align 4
    br label %if.end

  if.end:                                           ; preds = %if.then, %entry
    ret i16 0
  }

  define i16 @erase_test16_bigimm(i16 %0, i32 %1, ptr nocapture %2) {
  entry:
    %3 = icmp ne i16 %0, 0
    %4 = and i32 %1, 123456
    %trunc = trunc i32 %4 to i16
    %5 = icmp eq i16 %trunc, 0
    %6 = select i1 %3, i1 %5, i1 false
    br i1 %6, label %if.then, label %if.end

  if.then:                                          ; preds = %entry
    store i32 %4, ptr %2, align 4
    br label %if.end

  if.end:                                           ; preds = %if.then, %entry
    ret i16 0
  }

  define i16 @erase_test16_sf(i16 %0, i16 %1, ptr nocapture %2) {
  entry:
    %3 = icmp ne i16 %0, 0
    %4 = and i16 %1, 1234
    %5 = icmp slt i16 %4, 0
    %6 = select i1 %3, i1 %5, i1 false
    br i1 %6, label %if.then, label %if.end

  if.then:                                          ; preds = %entry
    store i16 %4, ptr %2, align 4
    br label %if.end

  if.end:                                           ; preds = %if.then, %entry
    ret i16 0
  }
...
---
name:            test_erased
alignment:       16
tracksDebugUserValues: false
registers:
  - { id: 0, class: gr64, preferred-register: '' }
  - { id: 1, class: gr64, preferred-register: '' }
  - { id: 2, class: gr64, preferred-register: '' }
  - { id: 3, class: gr64, preferred-register: '' }
  - { id: 4, class: gr32, preferred-register: '' }
  - { id: 5, class: gr32, preferred-register: '' }
  - { id: 6, class: gr64, preferred-register: '' }
  - { id: 7, class: gr64, preferred-register: '' }
liveins:
  - { reg: '$rdi', virtual-reg: '%0' }
  - { reg: '$rsi', virtual-reg: '%1' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0 (%ir-block.3):
    liveins: $rdi, $rsi

    ; CHECK-LABEL: name: test_erased
    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
    ; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.0)
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[MOV64rm]].sub_32bit
    ; CHECK-NEXT: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[COPY2]], 3, implicit-def $eflags
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[AND32ri8_]], %subreg.sub_32bit
    ; CHECK-NEXT: [[CMOV64rr:%[0-9]+]]:gr64 = CMOV64rr [[SUBREG_TO_REG]], [[COPY]], 4, implicit $eflags
    ; CHECK-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, killed [[CMOV64rr]] :: (store (s64) into %ir.0)
    ; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG]]
    ; CHECK-NEXT: RET 0, $rax
    %1:gr64 = COPY $rsi
    %0:gr64 = COPY $rdi
    %3:gr64 = MOV64rm %0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.0)
    %4:gr32 = COPY %3.sub_32bit
    %5:gr32 = AND32ri8 %4, 3, implicit-def dead $eflags
    %6:gr64 = SUBREG_TO_REG 0, killed %5, %subreg.sub_32bit
    TEST64rr %6, %6, implicit-def $eflags
    %7:gr64 = CMOV64rr %6, %1, 4, implicit $eflags
    MOV64mr %0, 1, $noreg, 0, $noreg, killed %7 :: (store (s64) into %ir.0)
    $rax = COPY %6
    RET 0, $rax

...
---
name:            test_not_erased_when_sf_used
alignment:       16
tracksDebugUserValues: false
registers:
  - { id: 0, class: gr64, preferred-register: '' }
  - { id: 1, class: gr64, preferred-register: '' }
  - { id: 2, class: gr64, preferred-register: '' }
  - { id: 3, class: gr64, preferred-register: '' }
  - { id: 4, class: gr64, preferred-register: '' }
  - { id: 5, class: gr32, preferred-register: '' }
  - { id: 6, class: gr32, preferred-register: '' }
  - { id: 7, class: gr64, preferred-register: '' }
  - { id: 8, class: gr64, preferred-register: '' }
liveins:
  - { reg: '$rdi', virtual-reg: '%0' }
  - { reg: '$rsi', virtual-reg: '%1' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0 (%ir-block.4):
    liveins: $rdi, $rsi

    ; CHECK-LABEL: name: test_not_erased_when_sf_used
    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
    ; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.0)
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[MOV64rm]].sub_32bit
    ; CHECK-NEXT: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[COPY2]], 3, implicit-def dead $eflags
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[AND32ri8_]], %subreg.sub_32bit
    ; CHECK-NEXT: TEST64rr [[SUBREG_TO_REG]], [[SUBREG_TO_REG]], implicit-def $eflags
    ; CHECK-NEXT: [[CMOV64rr:%[0-9]+]]:gr64 = CMOV64rr [[SUBREG_TO_REG]], [[COPY]], 8, implicit $eflags
    ; CHECK-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, killed [[CMOV64rr]] :: (store (s64) into %ir.0)
    ; CHECK-NEXT: $rax = COPY [[MOV64rm]]
    ; CHECK-NEXT: RET 0, $rax
    %1:gr64 = COPY $rsi
    %0:gr64 = COPY $rdi
    %4:gr64 = MOV64rm %0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.0)
    %5:gr32 = COPY %4.sub_32bit
    %6:gr32 = AND32ri8 %5, 3, implicit-def dead $eflags
    %7:gr64 = SUBREG_TO_REG 0, killed %6, %subreg.sub_32bit
    TEST64rr %7, %7, implicit-def $eflags
    %8:gr64 = CMOV64rr %7, %1, 8, implicit $eflags
    MOV64mr %0, 1, $noreg, 0, $noreg, killed %8 :: (store (s64) into %ir.0)
    $rax = COPY %4
    RET 0, $rax

...
---
name:            test_not_erased_when_eflags_change
alignment:       16
tracksDebugUserValues: false
registers:
  - { id: 0, class: gr64, preferred-register: '' }
  - { id: 1, class: gr64, preferred-register: '' }
  - { id: 2, class: gr64, preferred-register: '' }
  - { id: 3, class: gr64, preferred-register: '' }
  - { id: 4, class: gr64, preferred-register: '' }
  - { id: 5, class: gr64, preferred-register: '' }
  - { id: 6, class: gr32, preferred-register: '' }
  - { id: 7, class: gr32, preferred-register: '' }
  - { id: 8, class: gr64, preferred-register: '' }
  - { id: 9, class: gr64, preferred-register: '' }
  - { id: 10, class: gr64, preferred-register: '' }
liveins:
  - { reg: '$rdi', virtual-reg: '%0' }
  - { reg: '$rsi', virtual-reg: '%1' }
  - { reg: '$rcx', virtual-reg: '%3' }
  - { reg: '$r8', virtual-reg: '%4' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0 (%ir-block.5):
    liveins: $rdi, $rsi, $rcx, $r8

    ; CHECK-LABEL: name: test_not_erased_when_eflags_change
    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $r8
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rcx
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rsi
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr64 = COPY $rdi
    ; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY3]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.0)
    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr32 = COPY [[MOV64rm]].sub_32bit
    ; CHECK-NEXT: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[COPY4]], 3, implicit-def dead $eflags
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[AND32ri8_]], %subreg.sub_32bit
    ; CHECK-NEXT: [[XOR64ri8_:%[0-9]+]]:gr64 = XOR64ri8 [[COPY1]], 5, implicit-def dead $eflags
    ; CHECK-NEXT: TEST64rr [[SUBREG_TO_REG]], [[SUBREG_TO_REG]], implicit-def $eflags
    ; CHECK-NEXT: [[CMOV64rr:%[0-9]+]]:gr64 = CMOV64rr [[SUBREG_TO_REG]], [[COPY2]], 4, implicit $eflags
    ; CHECK-NEXT: MOV64mr [[COPY3]], 1, $noreg, 0, $noreg, killed [[CMOV64rr]] :: (store (s64) into %ir.0)
    ; CHECK-NEXT: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, killed [[XOR64ri8_]] :: (store (s64) into %ir.4)
    ; CHECK-NEXT: RET 0
    %4:gr64 = COPY $r8
    %3:gr64 = COPY $rcx
    %1:gr64 = COPY $rsi
    %0:gr64 = COPY $rdi
    %5:gr64 = MOV64rm %0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.0)
    %6:gr32 = COPY %5.sub_32bit
    %7:gr32 = AND32ri8 %6, 3, implicit-def dead $eflags
    %8:gr64 = SUBREG_TO_REG 0, killed %7, %subreg.sub_32bit
    %9:gr64 = XOR64ri8 %3, 5, implicit-def dead $eflags
    TEST64rr %8, %8, implicit-def $eflags
    %10:gr64 = CMOV64rr %8, %1, 4, implicit $eflags
    MOV64mr %0, 1, $noreg, 0, $noreg, killed %10 :: (store (s64) into %ir.0)
    MOV64mr %4, 1, $noreg, 0, $noreg, killed %9 :: (store (s64) into %ir.4)
    RET 0

...
---
name:            erase_test16
alignment:       16
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
callsEHReturn:   false
callsUnwindInit: false
hasEHCatchret:   false
hasEHScopes:     false
hasEHFunclets:   false
isOutlined:      false
debugInstrRef:   true
failsVerification: false
tracksDebugUserValues: false
registers:
  - { id: 0, class: gr32, preferred-register: '' }
  - { id: 1, class: gr32, preferred-register: '' }
  - { id: 2, class: gr64, preferred-register: '' }
  - { id: 3, class: gr16, preferred-register: '' }
  - { id: 4, class: gr16, preferred-register: '' }
  - { id: 5, class: gr32, preferred-register: '' }
  - { id: 6, class: gr32, preferred-register: '' }
  - { id: 7, class: gr16, preferred-register: '' }
liveins:
  - { reg: '$edi', virtual-reg: '%0' }
  - { reg: '$esi', virtual-reg: '%1' }
  - { reg: '$rdx', virtual-reg: '%2' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  functionContext: ''
  maxCallFrameSize: 4294967295
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  hasTailCall:     false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:           []
entry_values:    []
callSites:       []
debugValueSubstitutions: []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: erase_test16
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   successors: %bb.1(0x60000000), %bb.3(0x20000000)
  ; CHECK-NEXT:   liveins: $edi, $esi, $rdx
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr64 = COPY $rdx
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY $esi
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gr32 = COPY $edi
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY2]].sub_16bit
  ; CHECK-NEXT:   TEST16rr [[COPY3]], [[COPY3]], implicit-def $eflags
  ; CHECK-NEXT:   JCC_1 %bb.3, 4, implicit $eflags
  ; CHECK-NEXT:   JMP_1 %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1.entry:
  ; CHECK-NEXT:   successors: %bb.2(0x55555555), %bb.3(0x2aaaaaab)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[COPY1]], 123, implicit-def $eflags
  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gr16 = COPY [[AND32ri]].sub_16bit
  ; CHECK-NEXT:   JCC_1 %bb.3, 5, implicit $eflags
  ; CHECK-NEXT:   JMP_1 %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2.if.then:
  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   MOV16mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY3]] :: (store (s16) into %ir.2, align 4)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3.if.end:
  ; CHECK-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:gr16 = COPY [[MOV32r0_]].sub_16bit
  ; CHECK-NEXT:   $ax = COPY [[COPY5]]
  ; CHECK-NEXT:   RET 0, $ax
  bb.0.entry:
    successors: %bb.3(0x60000000), %bb.2(0x20000000)
    liveins: $edi, $esi, $rdx

    %2:gr64 = COPY $rdx
    %1:gr32 = COPY $esi
    %0:gr32 = COPY $edi
    %3:gr16 = COPY %0.sub_16bit
    TEST16rr %3, %3, implicit-def $eflags
    JCC_1 %bb.2, 4, implicit $eflags
    JMP_1 %bb.3

  bb.3.entry:
    successors: %bb.1(0x55555555), %bb.2(0x2aaaaaab)

    %5:gr32 = AND32ri %1, 123, implicit-def dead $eflags
    %4:gr16 = COPY %5.sub_16bit
    TEST16rr %4, %4, implicit-def $eflags
    JCC_1 %bb.2, 5, implicit $eflags
    JMP_1 %bb.1

  bb.1.if.then:
    successors: %bb.2(0x80000000)

    MOV16mr %2, 1, $noreg, 0, $noreg, %3 :: (store (s16) into %ir.2, align 4)

  bb.2.if.end:
    %6:gr32 = MOV32r0 implicit-def dead $eflags
    %7:gr16 = COPY %6.sub_16bit
    $ax = COPY %7
    RET 0, $ax

...
---
name:            erase_test16_bigimm
alignment:       16
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
callsEHReturn:   false
callsUnwindInit: false
hasEHCatchret:   false
hasEHScopes:     false
hasEHFunclets:   false
isOutlined:      false
debugInstrRef:   true
failsVerification: false
tracksDebugUserValues: false
registers:
  - { id: 0, class: gr32, preferred-register: '' }
  - { id: 1, class: gr32, preferred-register: '' }
  - { id: 2, class: gr32, preferred-register: '' }
  - { id: 3, class: gr64, preferred-register: '' }
  - { id: 4, class: gr16, preferred-register: '' }
  - { id: 5, class: gr16, preferred-register: '' }
  - { id: 6, class: gr32, preferred-register: '' }
  - { id: 7, class: gr16, preferred-register: '' }
liveins:
  - { reg: '$edi', virtual-reg: '%1' }
  - { reg: '$esi', virtual-reg: '%2' }
  - { reg: '$rdx', virtual-reg: '%3' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  functionContext: ''
  maxCallFrameSize: 4294967295
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  hasTailCall:     false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:           []
entry_values:    []
callSites:       []
debugValueSubstitutions: []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: erase_test16_bigimm
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   successors: %bb.1(0x60000000), %bb.3(0x20000000)
  ; CHECK-NEXT:   liveins: $edi, $esi, $rdx
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr64 = COPY $rdx
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY $esi
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gr32 = COPY $edi
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY2]].sub_16bit
  ; CHECK-NEXT:   TEST16rr [[COPY3]], [[COPY3]], implicit-def $eflags
  ; CHECK-NEXT:   JCC_1 %bb.3, 4, implicit $eflags
  ; CHECK-NEXT:   JMP_1 %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1.entry:
  ; CHECK-NEXT:   successors: %bb.2(0x55555555), %bb.3(0x2aaaaaab)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[COPY1]], 123456, implicit-def dead $eflags
  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gr16 = COPY [[AND32ri]].sub_16bit
  ; CHECK-NEXT:   TEST16rr [[COPY4]], [[COPY4]], implicit-def $eflags
  ; CHECK-NEXT:   JCC_1 %bb.3, 5, implicit $eflags
  ; CHECK-NEXT:   JMP_1 %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2.if.then:
  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   MOV32mr [[COPY]], 1, $noreg, 0, $noreg, [[AND32ri]] :: (store (s32) into %ir.2)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3.if.end:
  ; CHECK-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:gr16 = COPY [[MOV32r0_]].sub_16bit
  ; CHECK-NEXT:   $ax = COPY [[COPY5]]
  ; CHECK-NEXT:   RET 0, $ax
  bb.0.entry:
    successors: %bb.3(0x60000000), %bb.2(0x20000000)
    liveins: $edi, $esi, $rdx

    %3:gr64 = COPY $rdx
    %2:gr32 = COPY $esi
    %1:gr32 = COPY $edi
    %5:gr16 = COPY %1.sub_16bit
    TEST16rr %5, %5, implicit-def $eflags
    JCC_1 %bb.2, 4, implicit $eflags
    JMP_1 %bb.3

  bb.3.entry:
    successors: %bb.1(0x55555555), %bb.2(0x2aaaaaab)

    %0:gr32 = AND32ri %2, 123456, implicit-def dead $eflags
    %4:gr16 = COPY %0.sub_16bit
    TEST16rr %4, %4, implicit-def $eflags
    JCC_1 %bb.2, 5, implicit $eflags
    JMP_1 %bb.1

  bb.1.if.then:
    successors: %bb.2(0x80000000)

    MOV32mr %3, 1, $noreg, 0, $noreg, %0 :: (store (s32) into %ir.2)

  bb.2.if.end:
    %6:gr32 = MOV32r0 implicit-def dead $eflags
    %7:gr16 = COPY %6.sub_16bit
    $ax = COPY %7
    RET 0, $ax

...
---
name:            erase_test16_sf
alignment:       16
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
callsEHReturn:   false
callsUnwindInit: false
hasEHCatchret:   false
hasEHScopes:     false
hasEHFunclets:   false
isOutlined:      false
debugInstrRef:   true
failsVerification: false
tracksDebugUserValues: false
registers:
  - { id: 0, class: gr16, preferred-register: '' }
  - { id: 1, class: gr32, preferred-register: '' }
  - { id: 2, class: gr32, preferred-register: '' }
  - { id: 3, class: gr64, preferred-register: '' }
  - { id: 4, class: gr16, preferred-register: '' }
  - { id: 5, class: gr32, preferred-register: '' }
  - { id: 6, class: gr32, preferred-register: '' }
  - { id: 7, class: gr16, preferred-register: '' }
liveins:
  - { reg: '$edi', virtual-reg: '%1' }
  - { reg: '$esi', virtual-reg: '%2' }
  - { reg: '$rdx', virtual-reg: '%3' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  functionContext: ''
  maxCallFrameSize: 4294967295
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  hasTailCall:     false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:           []
entry_values:    []
callSites:       []
debugValueSubstitutions: []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: erase_test16_sf
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   successors: %bb.1(0x60000000), %bb.3(0x20000000)
  ; CHECK-NEXT:   liveins: $edi, $esi, $rdx
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr64 = COPY $rdx
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY $esi
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gr32 = COPY $edi
  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY2]].sub_16bit
  ; CHECK-NEXT:   TEST16rr [[COPY3]], [[COPY3]], implicit-def $eflags
  ; CHECK-NEXT:   JCC_1 %bb.3, 4, implicit $eflags
  ; CHECK-NEXT:   JMP_1 %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1.entry:
  ; CHECK-NEXT:   successors: %bb.2(0x55555555), %bb.3(0x2aaaaaab)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[COPY1]], 1234, implicit-def dead $eflags
  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gr16 = COPY [[AND32ri]].sub_16bit
  ; CHECK-NEXT:   TEST16rr [[COPY4]], [[COPY4]], implicit-def $eflags
  ; CHECK-NEXT:   JCC_1 %bb.3, 9, implicit $eflags
  ; CHECK-NEXT:   JMP_1 %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2.if.then:
  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   MOV16mr [[COPY]], 1, $noreg, 0, $noreg, [[COPY4]] :: (store (s16) into %ir.2, align 4)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3.if.end:
  ; CHECK-NEXT:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:gr16 = COPY [[MOV32r0_]].sub_16bit
  ; CHECK-NEXT:   $ax = COPY [[COPY5]]
  ; CHECK-NEXT:   RET 0, $ax
  bb.0.entry:
    successors: %bb.3(0x60000000), %bb.2(0x20000000)
    liveins: $edi, $esi, $rdx

    %3:gr64 = COPY $rdx
    %2:gr32 = COPY $esi
    %1:gr32 = COPY $edi
    %4:gr16 = COPY %1.sub_16bit
    TEST16rr %4, %4, implicit-def $eflags
    JCC_1 %bb.2, 4, implicit $eflags
    JMP_1 %bb.3

  bb.3.entry:
    successors: %bb.1(0x55555555), %bb.2(0x2aaaaaab)

    %5:gr32 = AND32ri %2, 1234, implicit-def dead $eflags
    %0:gr16 = COPY %5.sub_16bit
    TEST16rr %0, %0, implicit-def $eflags
    JCC_1 %bb.2, 9, implicit $eflags
    JMP_1 %bb.1

  bb.1.if.then:
    successors: %bb.2(0x80000000)

    MOV16mr %3, 1, $noreg, 0, $noreg, %0 :: (store (s16) into %ir.2, align 4)

  bb.2.if.end:
    %6:gr32 = MOV32r0 implicit-def dead $eflags
    %7:gr16 = COPY %6.sub_16bit
    $ax = COPY %7
    RET 0, $ax

...