src/llvm-project/llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64
# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86

--- |

  define void @test_add_i1() { ret void}
  define void @test_add_i8() { ret void }
  define void @test_add_i16() { ret void }
  define void @test_add_i27() { ret void }
  define void @test_add_i32() { ret void }
  define void @test_add_i42() { ret void }
  define void @test_add_i64() { ret void }
  define void @test_add_i128() { ret void }

...
---
name:            test_add_i1
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _, preferred-register: '' }
  - { id: 1, class: _, preferred-register: '' }
  - { id: 2, class: _, preferred-register: '' }
body:             |
  bb.1 (%ir-block.0):
    ; CHECK-LABEL: name: test_add_i1
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s8)
    ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
    ; CHECK-NEXT: RET 0
    %0(s32) = COPY $edx
    %1(s1) = G_TRUNC %0(s32)
    %2(s1) = G_ADD %1, %1
    %3:_(s32) = G_ANYEXT %2
    $eax = COPY %3
    RET 0
...
---
name:            test_add_i8
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _, preferred-register: '' }
  - { id: 1, class: _, preferred-register: '' }
  - { id: 2, class: _, preferred-register: '' }
body:             |
  bb.1 (%ir-block.0):
    ; CHECK-LABEL: name: test_add_i8
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s8)
    ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
    ; CHECK-NEXT: RET 0
    %0(s32) = COPY $edx
    %1(s8) = G_TRUNC %0(s32)
    %2(s8) = G_ADD %1, %1
    %3:_(s32) = G_ANYEXT %2
    $eax = COPY %3
    RET 0
...
---
name:            test_add_i16
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    ; CHECK-LABEL: name: test_add_i16
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC]]
    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16)
    ; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
    ; CHECK-NEXT: RET 0
    %0(s32) = COPY $edx
    %1(s16) = G_TRUNC %0(s32)
    %2(s16) = G_ADD %1, %1
    %3:_(s32) = G_ANYEXT %2
    $eax = COPY %3
    RET 0
...
---
name:            test_add_i27
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    ; CHECK-LABEL: name: test_add_i27
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
    ; CHECK-NEXT: $eax = COPY [[ADD]](s32)
    ; CHECK-NEXT: RET 0
    %0(s32) = COPY $edx
    %1(s27) = G_TRUNC %0(s32)
    %2(s27) = G_ADD %1, %1
    %3:_(s32) = G_ANYEXT %2
    $eax = COPY %3
    RET 0
...
---
name:            test_add_i32
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    ; CHECK-LABEL: name: test_add_i32
    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[DEF]], [[DEF1]]
    ; CHECK-NEXT: $eax = COPY [[ADD]](s32)
    ; CHECK-NEXT: RET 0
    %0(s32) = IMPLICIT_DEF
    %1(s32) = IMPLICIT_DEF
    %2(s32) = G_ADD %0, %1
    $eax = COPY %2
    RET 0
...
---
name:            test_add_i42
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    ; X64-LABEL: name: test_add_i42
    ; X64: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
    ; X64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY]]
    ; X64-NEXT: $rax = COPY [[ADD]](s64)
    ; X64-NEXT: RET 0
    ;
    ; X86-LABEL: name: test_add_i42
    ; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
    ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
    ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
    ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
    ; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
    ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
    ; X86-NEXT: $rax = COPY [[MV]](s64)
    ; X86-NEXT: RET 0
    %0(s64) = COPY $rdx
    %1(s42) = G_TRUNC %0(s64)
    %2(s42) = G_ADD %1, %1
    %3:_(s64) = G_ANYEXT %2
    $rax = COPY %3
    RET 0
...
---
name:            test_add_i64
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    ; X64-LABEL: name: test_add_i64
    ; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
    ; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
    ; X64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[DEF]], [[DEF1]]
    ; X64-NEXT: $rax = COPY [[ADD]](s64)
    ; X64-NEXT: RET 0
    ;
    ; X86-LABEL: name: test_add_i64
    ; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
    ; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
    ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
    ; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
    ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
    ; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
    ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
    ; X86-NEXT: $rax = COPY [[MV]](s64)
    ; X86-NEXT: RET 0
    %0(s64) = IMPLICIT_DEF
    %1(s64) = IMPLICIT_DEF
    %2(s64) = G_ADD %0, %1
    $rax = COPY %2
    RET 0
...
---
name:            test_add_i128
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    ; X64-LABEL: name: test_add_i128
    ; X64: [[DEF:%[0-9]+]]:_(s128) = IMPLICIT_DEF
    ; X64-NEXT: [[DEF1:%[0-9]+]]:_(s128) = IMPLICIT_DEF
    ; X64-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](s128)
    ; X64-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF1]](s128)
    ; X64-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
    ; X64-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
    ; X64-NEXT: $rax = COPY [[UADDO]](s64)
    ; X64-NEXT: $rdx = COPY [[UADDE]](s64)
    ; X64-NEXT: RET 0
    ;
    ; X86-LABEL: name: test_add_i128
    ; X86: [[DEF:%[0-9]+]]:_(s128) = IMPLICIT_DEF
    ; X86-NEXT: [[DEF1:%[0-9]+]]:_(s128) = IMPLICIT_DEF
    ; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s128)
    ; X86-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s128)
    ; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV4]]
    ; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV5]], [[UADDO1]]
    ; X86-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV2]], [[UV6]], [[UADDE1]]
    ; X86-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UV3]], [[UV7]], [[UADDE3]]
    ; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
    ; X86-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDE2]](s32), [[UADDE4]](s32)
    ; X86-NEXT: $rax = COPY [[MV]](s64)
    ; X86-NEXT: $rdx = COPY [[MV1]](s64)
    ; X86-NEXT: RET 0
    %0(s128) = IMPLICIT_DEF
    %1(s128) = IMPLICIT_DEF
    %2(s128) = G_ADD %0, %1
    %3:_(s64), %4:_(s64) = G_UNMERGE_VALUES %2(s128)
    $rax = COPY %3
    $rdx = COPY %4
    RET 0
...