src/llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-and.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s
---
name:            and_i8
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: and_i8
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[AND]]
    ; CHECK-NEXT: $x10 = COPY [[AND]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s8) = G_TRUNC %0(s32)
    %3:_(s8) = G_TRUNC %1(s32)
    %4:_(s8) = G_AND %3, %4
    %5:_(s32) = G_ANYEXT %4(s8)
    $x10 = COPY %5(s32)
    PseudoRET implicit $x10

...
---
name:            and_i16
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: and_i16
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[AND]]
    ; CHECK-NEXT: $x10 = COPY [[AND]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s16) = G_TRUNC %0(s32)
    %3:_(s16) = G_TRUNC %1(s32)
    %4:_(s16) = G_AND %3, %4
    %5:_(s32) = G_ANYEXT %4(s16)
    $x10 = COPY %5(s32)
    PseudoRET implicit $x10

...
---
name:            and_i32
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: and_i32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
    ; CHECK-NEXT: $x10 = COPY [[AND]](s32)
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:_(s32) = COPY $x10
    %1:_(s32) = COPY $x11
    %2:_(s32) = G_AND %0, %1
    $x10 = COPY %2(s32)
    PseudoRET implicit $x10

...