commit 9b512f460f6c050e00227e68d5e58b6a9134050c
author Maciej Żenczykowski <maze@google.com> Wed May 01 04:51:56 2024 +0000
committer Maciej Żenczykowski <maze@google.com> Wed May 01 05:08:47 2024 +0000
tree c787e5cd27857d485baca640cee6de002896a24f
parent 4fcc23591f8ffda5b3e5f83e53be40687361875b

ApfGenerator: fix (and rename) APFv6+ addArithR1

Test: TreeHugger
Signed-off-by: Maciej Żenczykowski <maze@google.com
Change-Id: I46a046b6fbf9160f051569a9ceca0fa46625dbe8

src/android/net/apf/ApfV4Generator.java

diff --git a/src/android/net/apf/ApfV4Generator.java b/src/android/net/apf/ApfV4Generator.java
index bf9a368..a2f93a1 100644
--- a/src/android/net/apf/ApfV4Generator.java
+++ b/src/android/net/apf/ApfV4Generator.java
@@ -15,6 +15,7 @@
  */
 package android.net.apf;
 
+import static android.net.apf.BaseApfGenerator.Rbit.Rbit1;
 import static android.net.apf.BaseApfGenerator.Register.R0;
 import static android.net.apf.BaseApfGenerator.Register.R1;
 
@@ -73,8 +74,8 @@
     }
 
     @Override
-    void addArithR1(Opcodes opcode) {
-        append(new Instruction(opcode, R1));
+    void addR0ArithR1(Opcodes opcode) {
+        append(new Instruction(opcode, Rbit1));  // APFv2/4: R0 op= R1
     }
 
     /**

src/android/net/apf/ApfV4GeneratorBase.java

diff --git a/src/android/net/apf/ApfV4GeneratorBase.java b/src/android/net/apf/ApfV4GeneratorBase.java
index be3da08..6dcc338 100644
--- a/src/android/net/apf/ApfV4GeneratorBase.java
+++ b/src/android/net/apf/ApfV4GeneratorBase.java
@@ -218,14 +218,14 @@
         return addLeftShift(-val);
     }
 
-    // Argument should be one of Opcodes.{ADD,MUL,DIV,AND,OR,SH}
-    abstract void addArithR1(Opcodes opcode);
+    // R0 op= R1, where op should be one of Opcodes.{ADD,MUL,DIV,AND,OR,SH}
+    abstract void addR0ArithR1(Opcodes opcode);
 
     /**
      * Add an instruction to the end of the program to add register R1 to register R0.
      */
     public final Type addAddR1ToR0() {
-        addArithR1(Opcodes.ADD);
+        addR0ArithR1(Opcodes.ADD);  // R0 += R1
         return self();
     }
 
@@ -233,7 +233,7 @@
      * Add an instruction to the end of the program to multiply register R0 by register R1.
      */
     public final Type addMulR0ByR1() {
-        addArithR1(Opcodes.MUL);
+        addR0ArithR1(Opcodes.MUL);  // R0 *= R1
         return self();
     }
 
@@ -241,7 +241,7 @@
      * Add an instruction to the end of the program to divide register R0 by register R1.
      */
     public final Type addDivR0ByR1() {
-        addArithR1(Opcodes.DIV);
+        addR0ArithR1(Opcodes.DIV);  // R0 /= R1
         return self();
     }
 
@@ -250,7 +250,7 @@
      * and store the result back into register R0.
      */
     public final Type addAndR0WithR1() {
-        addArithR1(Opcodes.AND);
+        addR0ArithR1(Opcodes.AND);  // R0 &= R1
         return self();
     }
 
@@ -259,7 +259,7 @@
      * and store the result back into register R0.
      */
     public final Type addOrR0WithR1() {
-        addArithR1(Opcodes.OR);
+        addR0ArithR1(Opcodes.OR);  // R0 |= R1
         return self();
     }
 
@@ -268,7 +268,7 @@
      * register R1.
      */
     public final Type addLeftShiftR0ByR1() {
-        addArithR1(Opcodes.SH);
+        addR0ArithR1(Opcodes.SH);  // R0 <<= R1
         return self();
     }
 

src/android/net/apf/ApfV6GeneratorBase.java

diff --git a/src/android/net/apf/ApfV6GeneratorBase.java b/src/android/net/apf/ApfV6GeneratorBase.java
index f76dc3d..b8359ec 100644
--- a/src/android/net/apf/ApfV6GeneratorBase.java
+++ b/src/android/net/apf/ApfV6GeneratorBase.java
@@ -17,6 +17,7 @@
 
 import static android.net.apf.BaseApfGenerator.Rbit.Rbit0;
 import static android.net.apf.BaseApfGenerator.Rbit.Rbit1;
+import static android.net.apf.BaseApfGenerator.Register.R0;
 import static android.net.apf.BaseApfGenerator.Register.R1;
 
 import androidx.annotation.NonNull;
@@ -610,8 +611,8 @@
     }
 
     @Override
-    void addArithR1(Opcodes opcode) {
-        append(new Instruction(opcode, R1));
+    void addR0ArithR1(Opcodes opcode) {
+        append(new Instruction(opcode, R0));  // APFv6+: R0 op= R1
     }
 
     /**