Merge AU_LINUX_ANDROID_LW.UM.2.1.R1.11.00.00.200.040
This updates our sources to CodeLinaro release
AU_LINUX_ANDROID_LW.UM.2.1.R1.11.00.00.200.040 (LW.UM.2.1.r1-04000-SW5100.0),
which corresponds to ChipCode LW 2.0 r00078.3a.
Bug: 280095980
Change-Id: Ibea75e0eda39d57425f557d577464d9d4be102ad
Signed-off-by: Daniel Price <danielprice@google.com>
diff --git a/fw/htc.h b/fw/htc.h
index 348c719..8e7f13d 100644
--- a/fw/htc.h
+++ b/fw/htc.h
@@ -165,13 +165,17 @@
/* base message ID header */
typedef PREPACK struct {
- A_UINT32 MessageID : 16,
- reserved : 16;
+ A_UINT32 MessageID: 16,
+ MetaData: 8,
+ reserved: 8;
} POSTPACK HTC_UNKNOWN_MSG;
#define HTC_UNKNOWN_MSG_MESSAGEID_LSB 0
#define HTC_UNKNOWN_MSG_MESSAGEID_MASK 0x0000ffff
#define HTC_UNKNOWN_MSG_MESSAGEID_OFFSET 0x00000000
+#define HTC_UNKNOWN_MSG_METADATA_LSB 16
+#define HTC_UNKNOWN_MSG_METADATA_MASK 0X00ff0000
+#define HTC_UNKNOWN_MSG_METADATA_OFFSET 0x00000000
/* HTC ready message
* direction : target-to-host */
diff --git a/fw/htt.h b/fw/htt.h
index 8912b77..6089d19 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -247,9 +247,11 @@
* 3.119 Add RX_PEER_META_DATA V1A and V1B defs.
* 3.120 Add HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND, _RESP defs.
* 3.121 Add HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND def.
+ * 3.122 Add is_umac_hang flag in H2T UMAC_HANG_RECOVERY_SOC_START_PRE_RESET msg
+ * 3.123 Add HTT_OPTION_TLV_TCL_METADATA_V21 def.
*/
#define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 121
+#define HTT_CURRENT_VERSION_MINOR 123
#define HTT_NUM_TX_FRAG_DESC 1024
@@ -562,10 +564,21 @@
* supported by the host. If the target doesn't provide a
* HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the VERSION_CONF message, it
* is implicitly understood that the V1 TCL metadata shall be used.
+ *
+ * Feb 2023: Added version HTT_OPTION_TLV_TCL_METADATA_V21 = 21
+ * read as version 2.1. We added support for Dynamic AST Index Allocation
+ * for Alder+Pine in version 2.1. For HTT_OPTION_TLV_TCL_METADATA_V2 = 2
+ * we will retain older behavior of making sure the AST Index for SAWF
+ * in Pine is allocated using wifitool ath2 setUnitTestCmd 0x48 2 536 1
+ * and the FW will crash in wal_tx_de_fast.c. For version 2.1 and
+ * above we will use htt_tx_tcl_svc_class_id_metadata.ast_index
+ * in TCLV2 command and do the dynamic AST allocations.
*/
enum HTT_OPTION_TLV_TCL_METADATA_VER_VALUES {
HTT_OPTION_TLV_TCL_METADATA_V1 = 1,
HTT_OPTION_TLV_TCL_METADATA_V2 = 2,
+ /* values 3-20 reserved */
+ HTT_OPTION_TLV_TCL_METADATA_V21 = 21,
};
PREPACK struct htt_option_tlv_tcl_metadata_ver_t {
@@ -782,6 +795,13 @@
HTT_STATS_TX_PDEV_MLO_ABORT_TAG = 177, /* htt_tx_pdev_stats_mlo_abort_tlv_v */
HTT_STATS_TX_PDEV_MLO_TXOP_ABORT_TAG = 178, /* htt_tx_pdev_stats_mlo_txop_abort_tlv_v */
HTT_STATS_UMAC_SSR_TAG = 179, /* htt_umac_ssr_stats_tlv */
+ HTT_STATS_PEER_BE_OFDMA_STATS_TAG = 180, /* htt_peer_be_ofdma_stats_tlv */
+ HTT_STATS_MLO_UMAC_SSR_TRIGGER_TAG = 181, /* htt_mlo_umac_ssr_trigger_stats_tlv */
+ HTT_STATS_MLO_UMAC_SSR_CMN_TAG = 182, /* htt_mlo_umac_ssr_common_stats_tlv */
+ HTT_STATS_MLO_UMAC_SSR_KPI_TSTMP_TAG = 183, /* htt_mlo_umac_ssr_kpi_tstamp_stats_tlv */
+ HTT_STATS_MLO_UMAC_SSR_DBG_TAG = 184, /* htt_mlo_umac_ssr_dbg_tlv */
+ HTT_STATS_MLO_UMAC_SSR_HANDSHAKE_TAG = 185, /* htt_mlo_umac_htt_handshake_stats_tlv */
+ HTT_STATS_MLO_UMAC_SSR_MLO_TAG = 186, /* htt_mlo_umac_ssr_mlo_stats_tlv */
HTT_STATS_MAX_TAG,
@@ -2569,7 +2589,8 @@
type: 2, /* vdev_id based or peer_id or svc_id or global seq based */
valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */
svc_class_id: 8,
- rsvd: 5,
+ ast_index: 3, /* Indicates to firmware the AST index to be used for Pine for AST Override */
+ rsvd: 2,
padding: 16; /* These 16 bits cannot be used by FW for the tcl command */
} htt_tx_tcl_svc_class_id_metadata;
@@ -7169,7 +7190,7 @@
rsvd4: 10;
A_UINT32 tx_queue_ext_v2_word_mask: 12,
tx_peer_entry_v2_word_mask: 12,
- rsvd5: 10;
+ rsvd5: 8;
A_UINT32 fes_status_end_word_mask: 16,
response_end_status_word_mask: 16;
A_UINT32 fes_status_prot_word_mask: 11,
@@ -10212,12 +10233,13 @@
* and HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP was sent
* beforehand.
*
- * |31 9|8|7 0|
+ * |31 10|9|8|7 0|
* |-----------------------------------------------------------|
- * | reserved |I| msg_type |
+ * | reserved |U|I| msg_type |
* |-----------------------------------------------------------|
* Where:
* I = is_initiator
+ * U = is_umac_hang
*
* The message is interpreted as follows:
* dword0 - b'0:7 - msg_type
@@ -10226,13 +10248,16 @@
* execute the UMAC-recovery in context of the Initiator or
* Non-Initiator.
* The value zero indicates this target is Non-Initiator.
- * b'9:31 - reserved.
+ * b'9 - is_umac_hang: indicates whether MLO UMAC recovery
+ * executed in context of UMAC hang or Target recovery.
+ * b'10:31 - reserved.
*/
PREPACK typedef struct {
A_UINT32 msg_type : 8,
is_initiator : 1,
- reserved : 23;
+ is_umac_hang : 1,
+ reserved : 22;
} POSTPACK htt_h2t_umac_hang_recovery_start_pre_reset_t;
#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_BYTES \
@@ -10251,6 +10276,17 @@
((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S));\
} while (0)
+#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_M 0x00000200
+#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S 9
+#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_GET(word0) \
+ (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_M) >> \
+ HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S)
+#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG, _val); \
+ ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S));\
+ } while (0)
+
/*
* @brief host -> target HTT RX_CCE_SUPER_RULE_SETUP message
@@ -10541,14 +10577,16 @@
*
* The message would appear as follows:
*
- * |31 16|15 12|11 8|7 0|
+ * |31 25|24|23 16|15 12|11 8|7 0|
* |----------------------------+----------+---------+--------------|
* | vdev ID | pdev ID | chip ID | msg type |
* |----------------------------+----------+---------+--------------|
* | ML peer ID | SW peer ID |
- * |----------------------------+--------------------+--------------|
- * | reserved | status |
- * |-------------------------------------------------+--------------|
+ * |------------+--+------------+--------------------+--------------|
+ * | reserved |SV| src_info | status |
+ * |------------+--+---------------------------------+--------------|
+ * Where:
+ * SV = src_info_valid flag
*
* The message is interpreted as follows:
* dword0 - b'0:7 - msg_type: This will be set to 0x24
@@ -10563,6 +10601,10 @@
* chosen as primary
* b'16:31 - ml_peer_id: Indicate the ml_peer_id to which the
* primary peer belongs.
+ * dword2 - b'0:7 - status: Indicates the status of Rx/TCL migration
+ * b'8:23 - src_info: Indicates New Virtual port number through
+ * which Rx Pipe connects to the correct PPE.
+ * b'24 - src_info_valid: Indicates src_info is valid.
*/
typedef struct {
@@ -10572,8 +10614,10 @@
vdev_id: 16; /* bits 31:16 */
A_UINT32 sw_link_peer_id: 16, /* bits 15:0 */
ml_peer_id: 16; /* bits 31:16 */
- A_UINT32 status: 8, /* bits 7:0 */
- reserved: 24; /* bits 31:8 */
+ A_UINT32 status: 8, /* bits 7:0 */
+ src_info: 16, /* bits 23:8 */
+ src_info_valid: 1, /* bit 24 */
+ reserved: 7; /* bits 31:25 */
} htt_h2t_primary_link_peer_migrate_resp_t;
#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00
@@ -10642,6 +10686,28 @@
((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S));\
} while (0)
+#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_M 0x00FFFF00
+#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S 8
+#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_GET(_var) \
+ (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_M) >> \
+ HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S)
+#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO, _val); \
+ ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S));\
+ } while (0)
+
+#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_M 0x01000000
+#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S 24
+#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_GET(_var) \
+ (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_M) >> \
+ HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S)
+#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID, _val); \
+ ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S));\
+ } while (0)
+
/*=== target -> host messages ===============================================*/
@@ -15377,7 +15443,7 @@
* dot11ba This field is the rate:
* 0: LDR
* 1: HDR
- * 2: Q2Q proprietary rate
+ * 2: Exclusive rate
*/
transmit_mcs : 4, /* [15:12] */
/* ofdma_transmission:
@@ -17753,12 +17819,12 @@
* to host ppdu stats indication message.
*
*
- * |31 16|15 12|11 10|9 8|7 0 |
- * |----------------------------------------------------------------------|
+ * |31 24|23 16|15 12|11 10|9 8|7 0 |
+ * |-----------------------------+-------+-------+--------+---------------|
* | payload_size | rsvd |pdev_id|mac_id | msg type |
- * |----------------------------------------------------------------------|
- * | ppdu_id |
- * |----------------------------------------------------------------------|
+ * |-------------+---------------+-------+-------+--------+---------------|
+ * | tgt_private | ppdu_id |
+ * |-------------+--------------------------------------------------------|
* | Timestamp in us |
* |----------------------------------------------------------------------|
* | reserved |
@@ -17798,8 +17864,9 @@
#define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_M 0xFFFF0000
#define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_S 16
-#define HTT_T2H_PPDU_STATS_PPDU_ID_M 0xFFFFFFFF
+#define HTT_T2H_PPDU_STATS_PPDU_ID_M 0x00FFFFFF
#define HTT_T2H_PPDU_STATS_PPDU_ID_S 0
+/* bits 31:24 are used by the target for internal purposes */
#define HTT_T2H_PPDU_STATS_MAC_ID_SET(word, value) \
do { \
@@ -17830,7 +17897,7 @@
#define HTT_T2H_PPDU_STATS_PPDU_ID_SET(word, value) \
do { \
- HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PPDU_ID, value); \
+ /*HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PPDU_ID, value);*/ \
(word) |= (value) << HTT_T2H_PPDU_STATS_PPDU_ID_S; \
} while (0)
#define HTT_T2H_PPDU_STATS_PPDU_ID_GET(word) \
@@ -19009,9 +19076,11 @@
};
#define HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0 \
- A_UINT32 w0_fw_rsvd:30; \
+ A_UINT32 w0_fw_rsvd:29; \
+ A_UINT32 w0_manual_ulofdma_trig:1; \
A_UINT32 w0_valid:1; \
A_UINT32 w0_version:1;
+
struct htt_ul_ofdma_user_info_v0_bitmap_w0 {
HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0
};
@@ -19032,9 +19101,9 @@
#define HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0 \
A_UINT32 w0_fw_rsvd:27; \
- A_UINT32 w0_sub_version:3; /* set to a value of “0” on WKK/Beryllium targets (future expansion) */ \
+ A_UINT32 w0_sub_version:3; /* set to a value of "0" on WKK/Beryllium targets (future expansion) */ \
A_UINT32 w0_valid:1; /* field aligns with V0 definition */ \
- A_UINT32 w0_version:1; /* set to a value of “1” to indicate picking htt_ul_ofdma_user_info_v1_bitmap (field aligns with V0 definition) */
+ A_UINT32 w0_version:1; /* set to a value of "1" to indicate picking htt_ul_ofdma_user_info_v1_bitmap (field aligns with V0 definition) */
struct htt_ul_ofdma_user_info_v1_bitmap_w0 {
HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0
@@ -19101,6 +19170,9 @@
#define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_M 0x0000ffff
#define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S 0
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_MANUAL_ULOFDMA_TRIG_M 0x20000000
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_MANUAL_ULOFDMA_TRIG_S 29
+
#define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M 0x40000000
#define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S 30
@@ -21517,59 +21589,59 @@
ml_peer_id: 16; /* bits 31:16 */
} htt_t2h_primary_link_peer_migrate_ind_t;
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S 8
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_GET(_var) \
- (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M) >> \
- HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S)
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_SET(_var, _val) \
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S 8
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_GET(_var) \
+ (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M) >> \
+ HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S)
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_SET(_var, _val) \
do { \
- HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID, _val); \
- ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S));\
+ HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID, _val); \
+ ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S));\
} while (0)
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M 0x0000F000
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S 12
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_GET(_var) \
- (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M) >> \
- HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S)
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_SET(_var, _val) \
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M 0x0000F000
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S 12
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_GET(_var) \
+ (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M) >> \
+ HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S)
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_SET(_var, _val) \
do { \
- HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID, _val); \
- ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S));\
+ HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID, _val); \
+ ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S));\
} while (0)
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M 0xFFFF0000
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S 16
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_GET(_var) \
- (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M) >> \
- HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S)
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_SET(_var, _val) \
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M 0xFFFF0000
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S 16
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_GET(_var) \
+ (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M) >> \
+ HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S)
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_SET(_var, _val) \
do { \
- HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID, _val); \
- ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S));\
+ HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID, _val); \
+ ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S));\
} while (0)
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M 0x0000FFFF
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S 0
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_GET(_var) \
- (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M) >> \
- HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S)
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_SET(_var, _val) \
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M 0x0000FFFF
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S 0
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_GET(_var) \
+ (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M) >> \
+ HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S)
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_SET(_var, _val) \
do { \
- HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID, _val); \
- ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S));\
+ HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID, _val); \
+ ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S));\
} while (0)
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M 0xFFFF0000
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S 16
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_GET(_var) \
- (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M) >> \
- HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S)
-#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_SET(_var, _val) \
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M 0xFFFF0000
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S 16
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_GET(_var) \
+ (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M) >> \
+ HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S)
+#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_SET(_var, _val) \
do { \
- HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID, _val); \
- ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\
+ HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID, _val); \
+ ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\
} while (0)
/**
diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h
index 83802fb..54dd0b6 100644
--- a/fw/htt_ppdu_stats.h
+++ b/fw/htt_ppdu_stats.h
@@ -876,6 +876,16 @@
reserved3: 31;
};
};
+ /* is_manual_ulofdma_trigger:
+ * Flag to indicate if a given UL OFDMA trigger is manually triggered
+ * from the Host
+ */
+ A_UINT32 is_manual_ulofdma_trigger;
+ /* is_combined_ul_bsrp_trigger:
+ * Flag to indicate if a given UL BSRP trigger is sent combined as
+ * part of existing DL/UL data sequence
+ */
+ A_UINT32 is_combined_ul_bsrp_trigger;
} htt_ppdu_stats_common_tlv;
#define HTT_PPDU_STATS_USER_COMMON_TLV_TID_NUM_M 0x000000ff
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index b5cc19f..9db7ed5 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -148,6 +148,7 @@
* 6 bit htt_msdu_flow_stats_tlv
* 7 bit htt_peer_sched_stats_tlv
* 8 bit htt_peer_ax_ofdma_stats_tlv
+ * 9 bit htt_peer_be_ofdma_stats_tlv
* - config_param2: [Bit31 : Bit0] mac_addr31to0
* - config_param3: [Bit15 : Bit0] mac_addr47to32
* [Bit 16] If this bit is set, reset per peer stats
@@ -520,6 +521,7 @@
HTT_DBG_PDEV_MBSSID_CTRL_FRAME_STATS = 54,
/** HTT_DBG_SOC_SSR_STATS
+ * Used for non-MLO UMAC recovery stats.
* PARAMS:
* - No Params
* RESP MSG:
@@ -527,6 +529,15 @@
*/
HTT_DBG_SOC_SSR_STATS = 55,
+ /** HTT_DBG_MLO_UMAC_SSR_STATS
+ * Used for MLO UMAC recovery stats.
+ * PARAMS:
+ * - No Params
+ * RESP MSG:
+ * - htt_mlo_umac_ssr_stats_tlv
+ */
+ HTT_DBG_MLO_UMAC_SSR_STATS = 56,
+
/* keep this last */
HTT_DBG_NUM_EXT_STATS = 256,
@@ -1866,6 +1877,7 @@
HTT_MSDU_FLOW_STATS_TLV = 6,
HTT_PEER_SCHED_STATS_TLV = 7,
HTT_PEER_AX_OFDMA_STATS_TLV = 8,
+ HTT_PEER_BE_OFDMA_STATS_TLV = 9,
HTT_PEER_STATS_MAX_TLV = 31,
} htt_peer_stats_tlv_enum;
@@ -1909,8 +1921,20 @@
/* Last updated value of DL and UL queue depths for each peer per AC */
A_UINT32 last_updated_dl_qdepth[HTT_NUM_AC_WMM];
A_UINT32 last_updated_ul_qdepth[HTT_NUM_AC_WMM];
+ /* Per peer Manual 11ax UL OFDMA trigger and trigger error counts */
+ A_UINT32 ax_manual_ulofdma_trig_count;
+ A_UINT32 ax_manual_ulofdma_trig_err_count;
} htt_peer_ax_ofdma_stats_tlv;
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ A_UINT32 peer_id;
+ /* Per peer Manual 11be UL OFDMA trigger and trigger error counts */
+ A_UINT32 be_manual_ulofdma_trig_count;
+ A_UINT32 be_manual_ulofdma_trig_err_count;
+} htt_peer_be_ofdma_stats_tlv;
+
+
/* config_param0 */
#define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_M 0x00000001
@@ -2000,6 +2024,7 @@
htt_tx_tid_stats_v1_tlv tx_tid_stats_v1[1];
htt_peer_sched_stats_tlv peer_sched_stats;
htt_peer_ax_ofdma_stats_tlv ax_ofdma_stats;
+ htt_peer_be_ofdma_stats_tlv be_ofdma_stats;
} htt_peer_stats_t;
/* =========== ACTIVE PEER LIST ========== */
@@ -2518,6 +2543,14 @@
A_UINT32 standalone_ax_bsr_trigger_tried[HTT_NUM_AC_WMM];
/** 11AX HE MU Standalone Freq. BSRP Trigger completed with error(s) */
A_UINT32 standalone_ax_bsr_trigger_err[HTT_NUM_AC_WMM];
+ /** 11AX HE Manual Single-User UL OFDMA Trigger frame sent over the air */
+ A_UINT32 manual_ax_su_ulofdma_basic_trigger[HTT_NUM_AC_WMM];
+ /** 11AX HE Manual Single-User UL OFDMA Trigger completed with error(s) */
+ A_UINT32 manual_ax_su_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM];
+ /** 11AX HE Manual Multi-User UL OFDMA Trigger frame sent over the air */
+ A_UINT32 manual_ax_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM];
+ /** 11AX HE Manual Multi-User UL OFDMA Trigger completed with error(s) */
+ A_UINT32 manual_ax_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM];
} htt_tx_selfgen_ax_stats_tlv;
typedef struct {
@@ -2565,6 +2598,14 @@
A_UINT32 standalone_be_bsr_trigger_tried[HTT_NUM_AC_WMM];
/** 11BE EHT MU Standalone Freq. BSRP Trigger completed with error(s) */
A_UINT32 standalone_be_bsr_trigger_err[HTT_NUM_AC_WMM];
+ /** 11BE EHT Manual Single-User UL OFDMA Trigger frame sent over the air */
+ A_UINT32 manual_be_su_ulofdma_basic_trigger[HTT_NUM_AC_WMM];
+ /** 11BE EHT Manual Single-User UL OFDMA Trigger completed with error(s) */
+ A_UINT32 manual_be_su_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM];
+ /** 11BE EHT Manual Multi-User UL OFDMA Trigger frame sent over the air */
+ A_UINT32 manual_be_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM];
+ /** 11BE EHT Manual Multi-User UL OFDMA Trigger completed with error(s) */
+ A_UINT32 manual_be_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM];
} htt_tx_selfgen_be_stats_tlv;
typedef struct { /* DEPRECATED */
@@ -8842,6 +8883,585 @@
htt_pdev_bw_mgr_stats_tlv bw_mgr_tlv;
} htt_pdev_bw_mgr_stats_t;
+
+/*============= start MLO UMAC SSR stats ============= { */
+
+typedef enum {
+ HTT_MLO_UMAC_SSR_DBG_POINT_INVALID = 0,
+ HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_DISABLE_RXDMA_PREFETCH,
+ HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_PMACS_HWMLOS,
+ HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_GLOBAL_WSI,
+ HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_PMACS_DMAC,
+ HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_TCL,
+ HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_TQM,
+ HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_WBM,
+ HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_REO,
+ HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_HOST,
+ HTT_MLO_UMAC_SSR_DBG_POINT_RESET_PREREQUISITES,
+ HTT_MLO_UMAC_SSR_DBG_POINT_RESET_PRE_RING_RESET,
+ HTT_MLO_UMAC_SSR_DBG_POINT_RESET_APPLY_SOFT_RESET,
+ HTT_MLO_UMAC_SSR_DBG_POINT_RESET_POST_RING_RESET,
+ HTT_MLO_UMAC_SSR_DBG_POINT_RESET_FW_TQM_CMDQS,
+ HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_HOST,
+ HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_UMAC_INTERRUPTS,
+ HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_WBM,
+ HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_REO,
+ HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_TQM,
+ HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_PMACS_DMAC,
+ HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_TQM_SYNC_CMD,
+ HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_GLOBAL_WSI,
+ HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_PMACS_HWMLOS,
+ HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_ENABLE_RXDMA_PREFETCH,
+ HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_TCL,
+ HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_HOST_ENQ,
+ HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_VERIFY_UMAC_RECOVERED,
+ /* The below debug point values are reserved for future expansion. */
+ HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED28,
+ HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED29,
+ HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED30,
+ HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED31,
+ HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED32,
+ HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED33,
+ HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED34,
+ HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED35,
+ HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED36,
+ HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED37,
+ HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED38,
+ HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED39,
+ HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED40,
+ /*
+ * Due to backwards compatibility requirements, no futher DBG_POINT values
+ * can be added (but the above reserved values can be repurposed).
+ */
+ HTT_MLO_UMAC_SSR_DBG_POINT_MAX,
+} HTT_MLO_UMAC_SSR_DBG_POINTS;
+
+typedef enum {
+ HTT_MLO_UMAC_RECOVERY_HANDSHAKE_INVALID = 0,
+ HTT_MLO_UMAC_RECOVERY_HANDSHAKE_DO_PRE_RESET,
+ HTT_MLO_UMAC_RECOVERY_HANDSHAKE_DO_POST_RESET_START,
+ HTT_MLO_UMAC_RECOVERY_HANDSHAKE_DO_POST_RESET_COMPLETE,
+ /* The below recovery handshake values are reserved for future expansion. */
+ HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED4,
+ HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED5,
+ HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED6,
+ HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED7,
+ HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED8,
+ /*
+ * Due to backwards compatibility requirements, no futher
+ * RECOVERY_HANDSHAKE values can be added (but the above
+ * reserved values can be repurposed).
+ */
+ HTT_MLO_UMAC_RECOVERY_HANDSHAKE_COUNT,
+} HTT_MLO_UMAC_RECOVERY_HANDSHAKES;
+
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ A_UINT32 start_ms;
+ A_UINT32 end_ms;
+ A_UINT32 delta_ms;
+ A_UINT32 reserved;
+ A_UINT32 footprint; /* holds a HTT_MLO_UMAC_SSR_DBG_POINTS value */
+ A_UINT32 tqm_hw_tstamp;
+} htt_mlo_umac_ssr_dbg_tlv;
+
+typedef struct {
+ A_UINT32 last_mlo_htt_handshake_delta_ms;
+ A_UINT32 max_mlo_htt_handshake_delta_ms;
+ union {
+ A_UINT32 umac_recovery_done_mask;
+ struct {
+ A_UINT32 pre_reset_disable_rxdma_prefetch : 1,
+ pre_reset_pmacs_hwmlos : 1,
+ pre_reset_global_wsi : 1,
+ pre_reset_pmacs_dmac : 1,
+ pre_reset_tcl : 1,
+ pre_reset_tqm : 1,
+ pre_reset_wbm : 1,
+ pre_reset_reo : 1,
+ pre_reset_host : 1,
+ reset_prerequisites : 1,
+ reset_pre_ring_reset : 1,
+ reset_apply_soft_reset : 1,
+ reset_post_ring_reset : 1,
+ reset_fw_tqm_cmdqs : 1,
+ post_reset_host : 1,
+ post_reset_umac_interrupts : 1,
+ post_reset_wbm : 1,
+ post_reset_reo : 1,
+ post_reset_tqm : 1,
+ post_reset_pmacs_dmac : 1,
+ post_reset_tqm_sync_cmd : 1,
+ post_reset_global_wsi : 1,
+ post_reset_pmacs_hwmlos : 1,
+ post_reset_enable_rxdma_prefetch : 1,
+ post_reset_tcl : 1,
+ post_reset_host_enq : 1,
+ post_reset_verify_umac_recovered : 1,
+ reserved : 5;
+ } done_mask;
+ };
+} htt_mlo_umac_ssr_mlo_stats_t;
+
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ htt_mlo_umac_ssr_mlo_stats_t mlo;
+} htt_mlo_umac_ssr_mlo_stats_tlv;
+
+/* dword0 - b'0 - PRE_RESET_DISABLE_RXDMA_PREFETCH */
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_M 0x1
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S 0
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_M) >> \
+ HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S)
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S));\
+ } while (0)
+
+/* dword0 - b'1 - PRE_RESET_PMACS_HWMLOS */
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_M 0x2
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S 1
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_M) >> \
+ HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S)
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S));\
+ } while (0)
+
+/* dword0 - b'2 - PRE_RESET_GLOBAL_WSI */
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_M 0x4
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S 2
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_M) >> \
+ HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S)
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S));\
+ } while (0)
+
+/* dword0 - b'3 - PRE_RESET_PMACS_DMAC */
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_M 0x8
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S 3
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_M) >> \
+ HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S)
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S));\
+ } while (0)
+
+/* dword0 - b'4 - PRE_RESET_TCL */
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_M 0x10
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S 4
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_M) >> \
+ HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S)
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S));\
+ } while (0)
+
+/* dword0 - b'5 - PRE_RESET_TQM */
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_M 0x20
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S 5
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_M) >> \
+ HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S)
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S));\
+ } while (0)
+
+/* dword0 - b'6 - PRE_RESET_WBM */
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_M 0x40
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S 6
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_M) >> \
+ HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S)
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S));\
+ } while (0)
+
+/* dword0 - b'7 - PRE_RESET_REO */
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_M 0x80
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S 7
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_M) >> \
+ HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S)
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S));\
+ } while (0)
+
+/* dword0 - b'8 - PRE_RESET_HOST */
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_M 0x100
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S 8
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_M) >> \
+ HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S)
+#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S));\
+ } while (0)
+
+/* dword0 - b'9 - RESET_PREREQUISITES */
+#define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_M 0x200
+#define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S 9
+#define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_M) >> \
+ HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S)
+#define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S));\
+ } while (0)
+
+/* dword0 - b'10 - RESET_PRE_RING_RESET */
+#define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_M 0x400
+#define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S 10
+#define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_M) >> \
+ HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S)
+#define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S));\
+ } while (0)
+
+/* dword0 - b'11 - RESET_APPLY_SOFT_RESET */
+#define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_M 0x800
+#define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S 11
+#define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_M) >> \
+ HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S)
+#define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S));\
+ } while (0)
+
+/* dword0 - b'12 - RESET_POST_RING_RESET */
+#define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_M 0x1000
+#define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S 12
+#define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_M) >> \
+ HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S)
+#define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S));\
+ } while (0)
+
+/* dword0 - b'13 - RESET_FW_TQM_CMDQS */
+#define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_M 0x2000
+#define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S 13
+#define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_M) >> \
+ HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S)
+#define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S));\
+ } while (0)
+
+/* dword0 - b'14 - POST_RESET_HOST */
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_M 0x4000
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S 14
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_M) >> \
+ HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S)
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S));\
+ } while (0)
+
+/* dword0 - b'15 - POST_RESET_UMAC_INTERRUPTS */
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_M 0x8000
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S 15
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_M) >> \
+ HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S)
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S));\
+ } while (0)
+
+/* dword0 - b'16 - POST_RESET_WBM */
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_M 0x10000
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S 16
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_M) >> \
+ HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S)
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S));\
+ } while (0)
+
+/* dword0 - b'17 - POST_RESET_REO */
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_M 0x20000
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S 17
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_M) >> \
+ HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S)
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_REO, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S));\
+ } while (0)
+
+/* dword0 - b'18 - POST_RESET_TQM */
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_M 0x40000
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S 18
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_M) >> \
+ HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S)
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S));\
+ } while (0)
+
+/* dword0 - b'19 - POST_RESET_PMACS_DMAC */
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_M 0x80000
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S 19
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_M) >> \
+ HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S)
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S));\
+ } while (0)
+
+/* dword0 - b'20 - POST_RESET_TQM_SYNC_CMD */
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_M 0x100000
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S 20
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_M) >> \
+ HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S)
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S));\
+ } while (0)
+
+/* dword0 - b'21 - POST_RESET_GLOBAL_WSI */
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_M 0x200000
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S 21
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_M) >> \
+ HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S)
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S));\
+ } while (0)
+
+/* dword0 - b'22 - POST_RESET_PMACS_HWMLOS */
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_M 0x400000
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S 22
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_M) >> \
+ HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S)
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S));\
+ } while (0)
+
+/* dword0 - b'23 - POST_RESET_ENABLE_RXDMA_PREFETCH */
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_M 0x800000
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S 23
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_M) >> \
+ HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S)
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S));\
+ } while (0)
+
+/* dword0 - b'24 - POST_RESET_TCL */
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_M 0x1000000
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S 24
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_M) >> \
+ HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S)
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S));\
+ } while (0)
+
+/* dword0 - b'25 - POST_RESET_HOST_ENQ */
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_M 0x2000000
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S 25
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_M) >> \
+ HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S)
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S));\
+ } while (0)
+
+/* dword0 - b'26 - POST_RESET_VERIFY_UMAC_RECOVERED */
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_M 0x4000000
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S 26
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_GET(word0) \
+ (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_M) >> \
+ HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S)
+#define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_SET(word0, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED, _val); \
+ ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S));\
+ } while (0)
+
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ A_UINT32 last_trigger_request_ms;
+ A_UINT32 last_start_ms;
+ A_UINT32 last_start_disengage_umac_ms;
+ A_UINT32 last_enter_ssr_platform_thread_ms;
+ A_UINT32 last_exit_ssr_platform_thread_ms;
+ A_UINT32 last_start_engage_umac_ms;
+ A_UINT32 last_done_successful_ms;
+ A_UINT32 post_reset_tqm_sync_cmd_completion_ms;
+ A_UINT32 htt_sync_mlo_initiate_umac_recovery_ms;
+ A_UINT32 htt_sync_do_pre_reset_ms;
+ A_UINT32 htt_sync_do_post_reset_start_ms;
+ A_UINT32 htt_sync_do_post_reset_complete_ms;
+} htt_mlo_umac_ssr_kpi_tstamp_stats_tlv;
+
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ A_UINT32 htt_sync_start_ms;
+ A_UINT32 htt_sync_delta_ms;
+ A_UINT32 post_t2h_start_ms;
+ A_UINT32 post_t2h_delta_ms;
+ A_UINT32 post_t2h_msg_read_shmem_ms;
+ A_UINT32 post_t2h_msg_write_shmem_ms;
+ A_UINT32 post_t2h_msg_send_msg_to_host_ms;
+} htt_mlo_umac_htt_handshake_stats_tlv;
+
+typedef struct {
+ /*
+ * Note that the host cannot use this struct directly, but instead needs
+ * to use the TLV header within each element of each of the arrays in
+ * this struct to determine where the subsequent item resides.
+ */
+ htt_mlo_umac_ssr_dbg_tlv dbg_point[HTT_MLO_UMAC_SSR_DBG_POINT_MAX];
+ htt_mlo_umac_htt_handshake_stats_tlv htt_handshakes[HTT_MLO_UMAC_RECOVERY_HANDSHAKE_COUNT];
+} htt_mlo_umac_ssr_kpi_delta_stats_t;
+
+typedef struct {
+ /*
+ * Since each item within htt_mlo_umac_ssr_kpi_delta_stats_t has its own
+ * TLV header, and since no additional fields are added in this struct
+ * beyond the htt_mlo_umac_ssr_kpi_delta_stats_t info, no additional
+ * TLV header is needed.
+ *
+ * Note that the host cannot use this struct directly, but instead needs
+ * to use the TLV header within each item inside the
+ * htt_mlo_umac_ssr_kpi_delta_stats_t to determine where the subsequent
+ * item resides.
+ */
+ htt_mlo_umac_ssr_kpi_delta_stats_t kpi_delta;
+} htt_mlo_umac_ssr_kpi_delta_stats_tlv;
+
+typedef struct {
+ A_UINT32 last_e2e_delta_ms;
+ A_UINT32 max_e2e_delta_ms;
+ A_UINT32 per_handshake_max_allowed_delta_ms;
+ /* Total done count */
+ A_UINT32 total_success_runs_cnt;
+ A_UINT32 umac_recovery_in_progress;
+ /* Count of Disengaged in Pre reset */
+ A_UINT32 umac_disengaged_count;
+ /* Count of UMAC Soft/Control Reset */
+ A_UINT32 umac_soft_reset_count;
+ /* Count of Engaged in Post reset */
+ A_UINT32 umac_engaged_count;
+} htt_mlo_umac_ssr_common_stats_t;
+
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ htt_mlo_umac_ssr_common_stats_t cmn;
+} htt_mlo_umac_ssr_common_stats_tlv;
+
+typedef struct {
+ A_UINT32 trigger_requests_count;
+ A_UINT32 trigger_count_for_umac_hang;
+ A_UINT32 trigger_count_for_mlo_target_recovery_mode1;
+ A_UINT32 trigger_count_for_unknown_signature;
+ A_UINT32 total_trig_dropped;
+ A_UINT32 trigger_count_for_unit_test_direct_trigger;
+ A_UINT32 trigger_count_for_tx_de_wdg_dummy_frame_tout;
+ A_UINT32 trigger_count_for_peer_delete_wdg_dummy_frame_tout;
+ A_UINT32 trigger_count_for_reo_hang;
+ A_UINT32 trigger_count_for_tqm_hang;
+ A_UINT32 trigger_count_for_tcl_hang;
+ A_UINT32 trigger_count_for_wbm_hang;
+} htt_mlo_umac_ssr_trigger_stats_t;
+
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ htt_mlo_umac_ssr_trigger_stats_t trigger;
+} htt_mlo_umac_ssr_trigger_stats_tlv;
+
+typedef struct {
+ /*
+ * Note that the host cannot use this struct directly, but instead needs
+ * to use the TLV header within each element to determine where the
+ * subsequent element resides.
+ */
+ htt_mlo_umac_ssr_kpi_delta_stats_tlv kpi_delta_tlv;
+ htt_mlo_umac_ssr_kpi_tstamp_stats_tlv kpi_tstamp_tlv;
+} htt_mlo_umac_ssr_kpi_stats_t;
+
+typedef struct {
+ /*
+ * Since the embedded sub-struct within htt_mlo_umac_ssr_kpi_stats_tlv
+ * has its own TLV header, and since no additional fields are added in
+ * this struct beyond the htt_mlo_umac_ssr_kpi_stats_t info, no additional
+ * TLV header is needed.
+ *
+ * Note that the host cannot use this struct directly, but instead needs
+ * to use the TLV header within the htt_mlo_umac_ssr_kpi_stats_t sub-struct
+ * to determine how much data is present for this struct.
+ */
+ htt_mlo_umac_ssr_kpi_stats_t kpi;
+} htt_mlo_umac_ssr_kpi_stats_tlv;
+
+typedef struct {
+ /*
+ * Note that the host cannot use this struct directly, but instead needs
+ * to use the TLV header within each element to determine where the
+ * subsequent element resides.
+ */
+ htt_mlo_umac_ssr_trigger_stats_tlv trigger_tlv;
+ htt_mlo_umac_ssr_kpi_stats_tlv kpi_tlv;
+ htt_mlo_umac_ssr_mlo_stats_tlv mlo_tlv;
+ htt_mlo_umac_ssr_common_stats_tlv cmn_tlv;
+} htt_mlo_umac_ssr_stats_tlv;
+
+/*============= end MLO UMAC SSR stats ============= } */
+
typedef struct {
A_UINT32 total_done;
A_UINT32 trigger_requests_count;
diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index aeae8d5..ae77041 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -618,6 +618,16 @@
WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT = 365, /* Support rx peer meta data v1a and v1b */
WMI_SERVICE_CFR_CAPTURE_PDEV_ID_SOC = 366, /* Host can send PDEV_ID_SOC with CFR capture request and FW can derive pdev_id from TA address */
WMI_SERVICE_11BE_MLO_TDLS_SUPPORT = 367, /* Indicates FW supports 11be MLO TDLS. Host should enable 11be on TDLS only when FW indicates the support. */
+ WMI_SERVICE_MANUAL_ULOFDMA_TRIGGER_SUPPORT = 368, /* Support for Host triggered Manual UL OFDMA trigger frame feature */
+ WMI_SERVICE_STANDALONE_SOUND = 369, /* FW supports standalone sounding */
+ WMI_SERVICE_AFC_RESP_BINARY_FORMAT_SUPPORTED = 370, /* Service bit to indicate the supported AFC payload response format */
+ WMI_SERVICE_CCA_BUSY_INFO_FOREACH_20MHZ = 371, /* FW supports reporting of CCA busy info for each 20Mhz subband of wideband scan channel */
+ WMI_SERVICE_MLO_TSF_SYNC = 372, /* FW supports TSF sync across multiple chips */
+ WMI_SERVICE_RF_PATH_SEL_INIT_SUPPORT = 373, /* FW supports RF Path selection using WMI Init command field */
+ WMI_SERVICE_VDEV_PARAM_CHWIDTH_WITH_NOTIFY_SUPPORT = 374, /* FW supports VDEV param channel width switch with OMN/OMI notification */
+ WMI_SERVICE_RESTRICTED_TWT_REQUESTER = 375, /* Indicates FW supports Restricted TWT REQUESTER */
+ WMI_SERVICE_RESTRICTED_TWT_RESPONDER = 376, /* Indicates FW supports Restricted TWT RESPONDER */
+ WMI_SERVICE_AUX_MAC_SUPPORT = 377,
WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 15ff785..f880d7c 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1120,11 +1120,23 @@
WMITLV_TAG_STRUC_wmi_twt_nudge_dialog_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_twt_nudge_dialog_complete_event_fixed_param,
WMITLV_TAG_STRUC_wmi_pdev_vendor_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_vendor_pdev_event_fixed_param =
+ WMITLV_TAG_STRUC_wmi_pdev_vendor_event_fixed_param,
WMITLV_TAG_STRUC_wmi_pdev_vendor_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_vendor_pdev_cmd_fixed_param =
+ WMITLV_TAG_STRUC_wmi_pdev_vendor_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_vdev_vendor_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_vendor_vdev_event_fixed_param =
+ WMITLV_TAG_STRUC_wmi_vdev_vendor_event_fixed_param,
WMITLV_TAG_STRUC_wmi_vdev_vendor_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_vendor_vdev_cmd_fixed_param =
+ WMITLV_TAG_STRUC_wmi_vdev_vendor_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_peer_vendor_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_vendor_peer_event_fixed_param =
+ WMITLV_TAG_STRUC_wmi_peer_vendor_event_fixed_param,
WMITLV_TAG_STRUC_wmi_peer_vendor_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_vendor_peer_cmd_fixed_param =
+ WMITLV_TAG_STRUC_wmi_peer_vendor_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_roam_msg_info_tlv_param,
WMITLV_TAG_STRUC_wmi_vdev_set_tpc_power_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_vdev_ch_power_info,
@@ -1346,8 +1358,24 @@
WMITLV_TAG_STRUC_wmi_mlo_vdev_get_link_info_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info_event_fixed_param,
WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info,
+ WMITLV_TAG_STRUC_wmi_vdev_set_manual_su_trig_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_vdev_set_manual_mu_trig_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param,
+ WMITLV_TAG_STRUC_wmi_mlo_peer_link_control_param,
+ WMITLV_TAG_STRUC_wmi_dma_buf_release_cv_upload_meta_data,
+ WMITLV_TAG_STRUC_wmi_standalone_sounding_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_standalone_sounding_evt_fixed_param,
+ WMITLV_TAG_STRUC_wmi_ctrl_path_blanking_stats_struct,
+ WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo,
+ WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param,
+ WMITLV_TAG_STRUC_wmi_cca_busy_subband_info,
+ WMITLV_TAG_STRUC_wmi_mlo_link_disable_request_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_ctrl_path_peer_stats_struct,
+ WMITLV_TAG_STRUC_wmi_vdev_pause_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_gpio_state_req_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_gpio_state_res_event_fixed_param,
} WMITLV_TAG_ID;
-
/*
* IMPORTANT: Please add _ALL_ WMI Commands Here.
* Otherwise, these WMI TLV Functions will be process them.
@@ -1867,6 +1895,15 @@
OP(WMI_PDEV_SET_TGTR2P_TABLE_CMDID) \
OP(WMI_PEER_BULK_SET_CMDID) \
OP(WMI_MLO_VDEV_GET_LINK_INFO_CMDID) \
+ OP(WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID) \
+ OP(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID) \
+ OP(WMI_VDEV_STANDALONE_SOUND_CMDID) \
+ OP(WMI_PDEV_SET_RF_PATH_CMDID) \
+ OP(WMI_VDEV_PAUSE_CMDID) \
+ OP(WMI_GPIO_STATE_REQ_CMDID) \
+ OP(WMI_VENDOR_PDEV_CMDID) \
+ OP(WMI_VENDOR_VDEV_CMDID) \
+ OP(WMI_VENDOR_PEER_CMDID) \
/* add new CMD_LIST elements above this line */
@@ -2169,6 +2206,14 @@
OP(WMI_PDEV_SET_TGTR2P_TABLE_EVENTID) \
OP(WMI_CSA_IE_RECEIVED_EVENTID) \
OP(WMI_MLO_VDEV_LINK_INFO_EVENTID) \
+ OP(WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID) \
+ OP(WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID) \
+ OP(WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID) \
+ OP(WMI_MLO_LINK_DISABLE_REQUEST_EVENTID) \
+ OP(WMI_GPIO_STATE_RES_EVENTID) \
+ OP(WMI_VENDOR_PDEV_EVENTID) \
+ OP(WMI_VENDOR_VDEV_EVENTID) \
+ OP(WMI_VENDOR_PEER_EVENTID) \
/* add new EVT_LIST elements above this line */
@@ -3004,6 +3049,11 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_output_cmd_fixed_param, wmi_gpio_output_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_OUTPUT_CMDID);
+/* GPIO State Req Cmd */
+#define WMITLV_TABLE_WMI_GPIO_STATE_REQ_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_state_req_cmd_fixed_param, wmi_gpio_state_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_STATE_REQ_CMDID);
+
/* Antenna Controller config Cmd */
#define WMITLV_TABLE_WMI_ANT_CONTROLLER_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ant_controller_cmd_fixed_param, wmi_ant_controller_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -4538,7 +4588,8 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_ids, WMITLV_SIZE_VAR)\
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, mac_addr_list, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, twt_dialog_ids, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, odd_addr_read_args, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, odd_addr_read_args, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, peer_ids, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_CTRL_PATH_STATS_CMDID);
/* Request Halphy Stats through Ctrl Path */
@@ -5089,7 +5140,8 @@
#define WMITLV_TABLE_WMI_MLO_PEER_TID_TO_LINK_MAP_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_tid_to_link_map_fixed_param, wmi_peer_tid_to_link_map_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tid_to_link_map, tid_to_link_map, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_preferred_link_map, peer_preferred_link_map, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_preferred_link_map, peer_preferred_link_map, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_peer_link_control_param, mlo_peer_link_control_param, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PEER_TID_TO_LINK_MAP_CMDID);
/** WMI cmd used to setup Tid to Link Mapping for a vdev */
@@ -5304,6 +5356,44 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_vdev_get_link_info_cmd_fixed_param, wmi_mlo_vdev_get_link_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_VDEV_GET_LINK_INFO_CMDID);
+/* WMI command to set Manual SU UL OFDMA Trigger params */
+#define WMITLV_TABLE_WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_set_manual_su_trig_cmd_fixed_param, wmi_vdev_set_manual_su_trig_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID);
+
+/* WMI command to set Manual MU UL OFDMA Trigger params */
+#define WMITLV_TABLE_WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_set_manual_mu_trig_cmd_fixed_param, wmi_vdev_set_manual_mu_trig_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, peer_macaddr, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID);
+
+/* Standalone Sound Cmd */
+#define WMITLV_TABLE_WMI_VDEV_STANDALONE_SOUND_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_standalone_sounding_cmd_fixed_param, wmi_standalone_sounding_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, peer_list, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STANDALONE_SOUND_CMDID);
+
+/* WMI cmd to set RF path for PHY */
+#define WMITLV_TABLE_WMI_PDEV_SET_RF_PATH_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_cmd_fixed_param, wmi_pdev_set_rf_path_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_RF_PATH_CMDID);
+
+/* VDEV PAUSE cmd */
+#define WMITLV_TABLE_WMI_VDEV_PAUSE_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_pause_cmd_fixed_param, wmi_vdev_pause_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_PAUSE_CMDID);
+
+/* pdev,vdev,peer cmd messages for tunneling vendor-specific contents */
+#define WMITLV_TABLE_WMI_VENDOR_PDEV_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_vendor_cmd_fixed_param, wmi_pdev_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PDEV_CMDID);
+#define WMITLV_TABLE_WMI_VENDOR_VDEV_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_vendor_cmd_fixed_param, wmi_vdev_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_VDEV_CMDID);
+#define WMITLV_TABLE_WMI_VENDOR_PEER_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_vendor_cmd_fixed_param, wmi_peer_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PEER_CMDID);
+
/************************** TLV definitions of WMI events *******************************/
@@ -5485,7 +5575,8 @@
/* Channel Info Event */
#define WMITLV_TABLE_WMI_CHAN_INFO_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chan_info_event_fixed_param, wmi_chan_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_scan_blanking_params_info, scan_blanking_params, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_scan_blanking_params_info, scan_blanking_params, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cca_busy_subband_info, cca_busy_subband_info, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_CHAN_INFO_EVENTID);
/* RSSI dB to dBm conversion params info event to host */
@@ -5721,6 +5812,11 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_input_event_fixed_param, wmi_gpio_input_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_INPUT_EVENTID);
+/* GPIO State Res Event */
+#define WMITLV_TABLE_WMI_GPIO_STATE_RES_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_state_res_event_fixed_param, wmi_gpio_state_res_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_STATE_RES_EVENTID);
+
/* CSA Handling Event */
#define WMITLV_TABLE_WMI_CSA_HANDLING_EVENTID(id,op,buf,len)\
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_fixed_param, wmi_csa_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -6740,7 +6836,9 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_afc_stats_struct, ctrl_path_afc_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_pmlo_stats_struct, ctrl_path_pmlo_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_cfr_stats_struct, ctrl_path_cfr_stats, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_t2lm_stats_struct, ctrl_path_t2lm_stats, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_t2lm_stats_struct, ctrl_path_t2lm_stats, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_blanking_stats_struct, ctrl_path_blanking_stats, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_peer_stats_struct, ctrl_path_peer_stats, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID);
/*
@@ -6815,7 +6913,8 @@
#define WMITLV_TABLE_WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dma_buf_release_fixed_param, wmi_dma_buf_release_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_entry, entries, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_spectral_meta_data, meta_data, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_spectral_meta_data, meta_data, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_cv_upload_meta_data, cv_meta_data, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID);
/* ctl failsafe check event */
@@ -7198,6 +7297,40 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_vdev_link_info, mlo_vdev_link_info, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_VDEV_LINK_INFO_EVENTID);
+/* Manual UL OFDMA Trigger Feedback Event */
+#define WMITLV_TABLE_WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param, wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, peer_macaddr, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID);
+
+/* WMI standalone sound complete event */
+#define WMITLV_TABLE_WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_standalone_sounding_evt_fixed_param, wmi_standalone_sounding_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, snd_failed, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID);
+
+/* Manual UL OFDMA Trigger RX PPDU Per user info Event */
+#define WMITLV_TABLE_WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param, wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_manual_ul_ofdma_trig_rx_peer_userinfo, rx_peer_userinfo, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID);
+
+/* MLO_LINK_DISABLE_REQUEST Event */
+#define WMITLV_TABLE_WMI_MLO_LINK_DISABLE_REQUEST_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_disable_request_event_fixed_param, wmi_mlo_link_disable_request_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_DISABLE_REQUEST_EVENTID);
+
+/* pdev,vdev,peer event messages for tunneling vendor-specific contents */
+#define WMITLV_TABLE_WMI_VENDOR_PDEV_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_vendor_event_fixed_param, wmi_pdev_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PDEV_EVENTID);
+#define WMITLV_TABLE_WMI_VENDOR_VDEV_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_vendor_event_fixed_param, wmi_vdev_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_VDEV_EVENTID);
+#define WMITLV_TABLE_WMI_VENDOR_PEER_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_vendor_event_fixed_param, wmi_peer_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PEER_EVENTID);
+
#ifdef __cplusplus
}
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index e32701f..536fdfd 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -316,6 +316,7 @@
WMI_GRP_QUIET_OFL, /* 0x4a Quiet offloads */
WMI_GRP_ODD, /* 0x4b ODD */
WMI_GRP_TDMA, /* 0x4c TDMA */
+ WMI_GRP_MANUAL_UL_TRIG /* 0x4d Manual UL OFDMA Trigger */
} WMI_GRP_ID;
#define WMI_CMD_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1)
@@ -517,6 +518,9 @@
WMI_PDEV_MESH_RX_FILTER_ENABLE_CMDID,
/* WMI cmd to set Target rate to power table */
WMI_PDEV_SET_TGTR2P_TABLE_CMDID,
+ /* WMI cmd to set RF path for PHY */
+ WMI_PDEV_SET_RF_PATH_CMDID,
+
/* VDEV (virtual device) specific commands */
/** vdev create */
@@ -624,6 +628,9 @@
/** Enable SR prohibit feature for TIDs of vdev */
WMI_VDEV_PARAM_ENABLE_SR_PROHIBIT_CMDID,
+ /** pause vdev's Tx, Rx, or both for a specific duration */
+ WMI_VDEV_PAUSE_CMDID,
+
/* peer specific commands */
/** create a peer */
@@ -1229,6 +1236,9 @@
/* H2T HPA message */
WMI_HPA_CMDID,
+ /* WMI comamnd for standalone sounding */
+ WMI_VDEV_STANDALONE_SOUND_CMDID,
+
/* Offload 11k related requests */
WMI_11K_OFFLOAD_REPORT_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_11K_OFFLOAD),
/* invoke neighbor report from FW */
@@ -1244,6 +1254,8 @@
/* Antenna Controller, connected to wlan debug uart/GPIO. */
WMI_ANT_CONTROLLER_CMDID,
+ WMI_GPIO_STATE_REQ_CMDID,
+
/* FWTEST Commands */
WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_FWTEST),
/** set NoA descs **/
@@ -1563,6 +1575,13 @@
/* WMI commands specific to TDMA */
WMI_TDMA_SCHEDULE_REQUEST_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_TDMA),
+
+ /* WMI commands specific to manually-triggered UL */
+ /** WMI Command to set Manual SU UL OFDMA trigger parameters */
+ WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MANUAL_UL_TRIG),
+
+ /** WMI Command to set Manual MU UL OFDMA trigger parameters */
+ WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID,
} WMI_CMD_ID;
typedef enum {
@@ -2199,6 +2218,9 @@
/* T2H HPA message */
WMI_HPA_EVENTID,
+ /* WMI standalone command complete Event */
+ WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID,
+
/* GPIO Event */
WMI_GPIO_INPUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_GPIO),
@@ -2217,6 +2239,8 @@
/* Smart Antenna Controller status */
WMI_SMARTANT_STATE_CHANGE_EVENTID,
+ WMI_GPIO_STATE_RES_EVENTID,
+
/* TDLS Event */
WMI_TDLS_PEER_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_TDLS),
@@ -2369,12 +2393,24 @@
WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_EVENTID,
/* Response event for WMI_MLO_VDEV_GET_LINK_INFO_CMDID */
WMI_MLO_VDEV_LINK_INFO_EVENTID,
+ /** request host to do T2LM neg to the un-disabled link */
+ WMI_MLO_LINK_DISABLE_REQUEST_EVENTID,
/* WMI event specific to Quiet handling */
WMI_QUIET_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_QUIET_OFL),
/* ODD events */
WMI_ODD_LIVEDUMP_RESPONSE_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_ODD),
+
+ /** WMI events specific to manually-triggered UL */
+ /**
+ * WMI Event to send Manual UL OFDMA Trigger frame status feedback to Host
+ */
+ WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MANUAL_UL_TRIG),
+ /**
+ * WMI Event to send Manual UL OFDMA Trigger frame RX PPDU info to Host
+ */
+ WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID,
} WMI_EVT_ID;
/* defines for OEM message sub-types */
@@ -4405,8 +4441,20 @@
* 1 -> disable wds_mec_intrabss offload
* Refer to WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_MEC_INTRABSS_OFFLOAD_GET /
* SET macros.
+ * Bit 16 - latency_flowq_support
+ * Flag to indicate whether host supports latency tolerant queue.
+ * By default, it is disabled.
+ * 0 -> disable latency_flowq_support
+ * 1 -> enable latency_flowq_support
+ * Refer to WMI_RSRC_CFG_FLAGS2_LATENCY_FLOWQ_SUPPORT_GET/SET macros.
+ * Bit 17 - rf_path_mode
+ * Flag to indicate overlapping_freq_mode
+ * By default, it will be primary mode (0)
+ * 0 - Primary
+ * 1 - Secondary
+ * Refer to WMI_RSRC_CFG_FLAGS2_RF_PATH_MODE_GET/SET macros.
*
- * Bits 31:16 - Reserved
+ * Bits 31:18 - Reserved
*/
A_UINT32 flags2;
/** @brief host_service_flags - can be used by Host to indicate
@@ -4850,6 +4898,16 @@
#define WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_MEC_INTRABSS_OFFLOAD_SET(flags2, value) \
WMI_SET_BITS(flags2, 15, 1, value)
+#define WMI_RSRC_CFG_FLAGS2_LATENCY_FLOWQ_SUPPORT_GET(flags2) \
+ WMI_GET_BITS(flags2, 16, 1)
+#define WMI_RSRC_CFG_FLAGS2_LATENCY_FLOWQ_SUPPORT_SET(flags2, value) \
+ WMI_SET_BITS(flags2, 16, 1, value)
+
+#define WMI_RSRC_CFG_FLAGS2_RF_PATH_MODE_GET(flags2) \
+ WMI_GET_BITS(flags2, 17, 1)
+#define WMI_RSRC_CFG_FLAGS2_RF_PATH_MODE_SET(flags2, value) \
+ WMI_SET_BITS(flags2, 17, 1, value)
+
#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_GET(host_service_flags) \
WMI_GET_BITS(host_service_flags, 0, 1)
@@ -5640,6 +5698,12 @@
#define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT 0x40000
#define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000
#define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000
+/** pause home channel when scan channel is same as home channel */
+#define WMI_SCAN_FLAG_PAUSE_HOME_CHANNEL 0x200000
+/**
+ * report CCA busy for each possible 20Mhz subbands of the wideband scan channel
+ */
+#define WMI_SCAN_FLAG_REPORT_CCA_BUSY_FOREACH_20MHZ 0x400000
/** for adaptive scan mode using 3 bits (21 - 23 bits) */
#define WMI_SCAN_DWELL_MODE_MASK 0x00E00000
@@ -5748,6 +5812,11 @@
/* Include MLO IE in Probe req */
#define WMI_SCAN_FLAG_EXT_INCL_MLIE_PRB_REQ 0x00004000
+#define WMI_SCAN_FLAG_EXT_LOW_LATENCY_SCAN 0x00008000
+#define WMI_SCAN_FLAG_EXT_RELIABLE_SCAN 0x00010000
+#define WMI_SCAN_FLAG_EXT_FAST_SCAN 0x00020000
+#define WMI_SCAN_FLAG_EXT_LOW_POWER_SCAN 0x00040000
+
/**
* new 6 GHz flags per chan (short ssid or bssid) in struct
@@ -7151,6 +7220,13 @@
A_UINT32 value;
} wmi_echo_cmd_fixed_param;
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag would be equivalent to WMITLV_TAG_STRUC_wmi_mlo_link_disable_request_event_fixed_param */
+ /** AP MLD address request to be disabled some set of link */
+ wmi_mac_addr mld_addr;
+ /** Request link id set to disable */
+ A_UINT32 linkid_bitmap;
+} wmi_mlo_link_disable_request_event_fixed_param;
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_regdomain_cmd_fixed_param */
@@ -9036,6 +9112,15 @@
* 1-31 | Reserved.
*/
WMI_PDEV_PARAM_SET_CONC_LOW_LATENCY_MODE,
+
+ /*
+ * Parameter to enable/disable low power listen mode
+ * bit | config_mode
+ * -----------------
+ * 0 | 0:disable, 1:enable.
+ * 1-31 | Reserved.
+ */
+ WMI_PDEV_PARAM_LPL_SETTING,
} WMI_PDEV_PARAM;
#define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
@@ -11736,8 +11821,539 @@
A_UINT32 qos_null_tx_send_compl_over_wmi;
/** total event alloc failure count for qos null tx send */
A_UINT32 qos_null_tx_send_event_alloc_failed;
+
+ /** wlan_pdev fields num_macs, vdev_up_count and vdev_active_count
+ * num_macs_phy_vdev_up_active:
+ * This word contains the following bitfields:
+ * number of macs from wlan_pdev
+ * (WMI_PDEV_STATS_NUM_MACS_SET,GET)
+ * number of vdev up count
+ * (WMI_PDEV_STATS_VDEV_UP_CNT_SET,GET)
+ * number of vdev active count
+ * (WMI_PDEV_STATS_VDEV_UP_CNT_SET,GET)
+ */
+ A_UINT32 opaque_debug_num_macs_phy_vdev_up_active;
+ /** refer wlan_pdev ic flags */
+ A_UINT32 opaque_debug_ic_flags;
+ /** vdev_id that are paused per pdev */
+ A_UINT32 opaque_debug_paused_ap_vdev_bitmap;
+ /** opaque_debug_flags:
+ * refer to WLAN_PS_DESC_BIN_HWM_HIT or WLAN_PS_DESC_BIN_LWM_HIT
+ */
+ A_UINT32 opaque_debug_flags;
+ /** wlan_pdev fields remote_peer_cnt, max_rf_chains_2G and max_rf_chains_5G
+ * remote_peer_cnt_max_rf_chains_2G_5G:
+ * This word contains the following bitfields:
+ * max chains supported in the 2.4 GHz band
+ * (WMI_PDEV_STATS_MAX_RF_CHAIN_2G_SET,GET)
+ * max chains supported in the 5 GHz band,
+ * (WMI_PDEV_STATS_MAX_RF_CHAIN_5G_SET,GET)
+ * number of remote peers
+ * (WMI_PDEV_STATS_REMOTE_PEER_CNT_SET,GET)
+ */
+ A_UINT32 opaque_debug_remote_peer_cnt_max_rf_chains_2G_5G;
+ /** wlan_pdev max HT Capability info, WMI_HT_CAP defines */
+ A_UINT32 opaque_debug_max_ht_cap_info;
+ /** wlan_pdev max VHT capability info, WMI_VHT_CAP defines */
+ A_UINT32 opaque_debug_max_vht_cap_info;
+ /** opaque_debug_max_vht_supp_mcs:
+ * wlan_pdev max VHT Supported MCS which is
+ * vht_supp_mcs_2G or vht_supp_mcs_5G
+ */
+ A_UINT32 opaque_debug_max_vht_supp_mcs;
+ /** wlan_pdev max HE capability info, WMI_HE_CAP defines */
+ A_UINT32 opaque_debug_max_he_cap_info;
+ A_UINT32 opaque_debug_max_he_cap_info_ext;
+ /** the nominal chain mask for transmit */
+ A_UINT32 opaque_debug_tx_chain_mask;
+ /** the nominal chain mask for receive */
+ A_UINT32 opaque_debug_rx_chain_mask;
+ /** opaque_debug_ema_flags:
+ * This word contains the following bitfields:
+ * ema_flags: ema_max_vap_cnt and ema_max_profile_period from wlan_pdev
+ * ema_max_vap_cnt- number of maximum EMA Tx vaps (VAPs having both
+ * VDEV_FLAGS_EMA_MODE and VDEV_FLAGS_TRANSMIT_AP set)
+ * (WMI_PDEV_STATS_EMA_MAX_VAP_CNT_SET,GET)
+ * ema_max_profile_period - maximum profile periodicity
+ * (maximum number of beacons after which VAP profiles repeat)
+ * for any EMA VAP on any pdev.
+ * (WMI_PDEV_STATS_EMA_MAX_PROFILE_PERIOD_SET,GET)
+ */
+ A_UINT32 opaque_debug_ema_flags;
+ /** wlan_pdev - maximum ML peers supported */
+ A_UINT32 opaque_debug_num_ml_peer_entries;
+ /** This word contains the following bitfields:
+ * wlan_pdev fields - num_max_hw_links, current_chip_id and max_num_chips
+ * (related to MLO)
+ * Max number of HW links
+ * (WMI_PDEV_STATS_NUM_MAX_HW_LINKS_SET,GET)
+ * Current Chip Id
+ * (WMI_PDEV_STATS_CURRENT_CHIP_ID_SET,GET)
+ * Max number of chips
+ * (WMI_PDEV_STATS_MAX_NUM_CHIPS_SET,GET)
+ */
+ A_UINT32 opaque_debug_mlo_flags;
+ /** Indicate beacon size in bytes */
+ A_UINT32 opaque_debug_large_bcn_size;
+ /** proposed by the host value of MSDUQs per each LinkView peer's TID */
+ A_UINT32 opaque_debug_num_of_linkview_msduqs_per_tid;
+ /** bcn_filter_context variables */
+ A_UINT32 opaque_debug_bcns_dropped;
+ A_UINT32 opaque_debug_bcns_recvd;
+ A_UINT32 opaque_debug_bcns_delivered;
+ /** Tids that are paused/unpaused based on module_id */
+ A_UINT32 opaque_debug_vdev_all_tid_pause_bitmap;
+ /** Tids that are blocked/unblocked based on module_id */
+ A_UINT32 opaque_debug_vdev_all_tid_block_bitmap;
+ /** wal_pdev rx filter, WAL_RX_FILTER_FLAGS defines */
+ A_UINT32 opaque_debug_rx_filter;
+ /** This word contains the following bitfields:
+ * aggr_nonaggr_retry_th:
+ * wal_pdev fields - agg_retry_th and non_agg_retry_th
+ * This value holds max retry threshold up to which a Data packet
+ * will be retried when ack is not received.
+ * agg_retry_th - Threshold value used when aggregation is enabled
+ * (WMI_PDEV_STATS_AGG_RETRY_TH_SET,GET)
+ * non_agg_retry_th - Threshold value used for non-aggregation.
+ * (WMI_PDEV_STATS_NON_AGG_RETRY_TH_SET)
+ */
+ A_UINT32 opaque_debug_aggr_nonaggr_retry_th;
+ /** This word contains the following bitfields:
+ * num_max_rx_ba_sessions:
+ * Number of rx BA session establised
+ * (WMI_PDEV_STATS_NUM_RX_BA_SESSIONS_SET,GET)
+ * Max number of rx BA session from wal_pdev
+ * (WMI_PDEV_STATS_MAX_RX_BA_SESSIONS_SET,GET)
+ */
+ A_UINT32 opaque_debug_num_max_rx_ba_sessions;
+ /** It holds WHAL_CHANNEL_SWITCH_FLAGS values */
+ A_UINT32 opaque_debug_chan_switch_flags;
+ /** reset_cause holds PDEV_RESET_CONSEC_FAILURE or PDEV_RESET_TXQ_TIMEOUT */
+ A_UINT32 opaque_debug_consecutive_failure_reset_cause;
+ /** PPDU duration limit, in us */
+ A_UINT32 opaque_debug_mu_ppdu_dur_limit_us;
+ /** pdev reset in progress */
+ A_UINT32 opaque_debug_reset_in_progress;
+ /** wal_dev - vdev_migrate_state refer to WAL_VDEV_MIGRATE_STATE */
+ A_UINT32 opaque_debug_vdev_migrate_state;
+ /** opaque_debug_rts_rc_flag:
+ * wal_pdev rts ratecode - this value reflects whatever
+ * WMI_PDEV_PARAM_RTS_FIXED_RATE value the host has specified for the pdev.
+ */
+ A_UINT32 opaque_debug_rts_rc_flag;
+ /* Num of peer delete in progress */
+ A_UINT32 opaque_debug_num_of_peer_delete_in_progress;
+ /** wal_pdev total number of active vdev count */
+ A_UINT32 opaque_debug_total_active_vdev_cnt;
+ /** wal_pdev - max number of vdevs per pdev */
+ A_UINT32 opaque_debug_max_vdevs;
+ /* NonOccupancyList(NOL) context */
+ A_UINT32 opaque_debug_dfs_nol_count;
+ /** NOL timeout in seconds */
+ A_UINT32 opaque_debug_dfs_nol_timeout;
+ A_UINT32 opaque_debug_dfs_use_nol;
+ /** channel availability check mode, refer enum WMI_ADFS_OCAC_MODE */
+ A_UINT32 opaque_debug_cac_mode;
+ A_UINT32 opaque_debug_dyn_ppdu_dur; /* in ms */
+ /** This word contains the following bitfields:
+ * wal_pdev home channel info
+ * home_chan_mhz_flags:
+ * primary channel frequency in mhz
+ * (WMI_PDEV_STATS_HOME_CHAN_MHZ_SET,GET)
+ * flags to specify other channel attributes
+ * (WMI_PDEV_STATS_HOME_CHAN_FLAGS_SET, GET)
+ */
+ A_UINT32 opaque_debug_home_chan_mhz_flags;
+ /** home channel center frequency in MHz */
+ A_UINT32 opaque_debug_home_band_center_freq;
+ /** home channel phy_mode, refer enum WLAN_PHY_MODE */
+ A_UINT32 opaque_debug_home_phy_mode;
+ /** This word contains the following bitfields:
+ * wal_pdev current channel info
+ * cur_chan_mhz_flags:
+ * primary channel frequency in mhz
+ * (WMI_PDEV_STATS_CUR_CHAN_MHZ_SET,GET)
+ * flags to specify other channel attributes
+ * (WMI_PDEV_STATS_CUR_CHAN_FLAGS_SET,GET)
+ */
+ A_UINT32 opaque_debug_cur_chan_mhz_flags;
+ /** current channel center frequency in MHz */
+ A_UINT32 opaque_debug_cur_band_center_freq;
+ /** current channel phy_mode, refer enum WLAN_PHY_MODE */
+ A_UINT32 opaque_debug_cur_phy_mode;
+ /* Beacon context info */
+ A_UINT32 opaque_debug_bcn_q_num_bcns_queued_to_hw;
+ /** beacon queue AIFS */
+ A_UINT32 opaque_debug_aifs;
+ /** beacon queue cwmin */
+ A_UINT32 opaque_debug_cwmin;
+ /** beacon queue cwmax */
+ A_UINT32 opaque_debug_cwmax;
+ /** FILS discovery period in TU */
+ A_UINT32 opaque_debug_fils_period;
+ /** Beacon interval in TU */
+ A_UINT32 opaque_debug_beacon_period;
+ A_UINT32 opaque_debug_staggered_beacon_intvl;
+ /** wal_pdev tx context, refer enum WAL_TX_CTXT_FLAGS */
+ A_UINT32 opaque_debug_tx_ctxt_flags;
+ /** opaque_debug_burst_mode_pending_isr
+ * wal_pdev tx_ctxt fields - burst_mode refer enum WAL_TX_BURST_MODE
+ * and pending_isr_status count
+ */
+ A_UINT32 opaque_debug_burst_mode_pending_isr;
+ /** max burst duration from ppdu duration in us */
+ A_UINT32 opaque_debug_burst_dur;
+ /** counter for tx hw stuck */
+ A_UINT32 opaque_debug_tx_hw_stuck_cnt;
+ /** counter for tx consecutive lifetime expiry */
+ A_UINT32 opaque_debug_consecutive_lifetime_expiries;
+ /** wal_pdev rx context, refer enum WAL_RX_CTXT_FLAGS */
+ A_UINT32 opaque_debug_rx_ctxt_flags;
+ /** wal_pdev fields in rx context for rx_suspend or resume count */
+ A_UINT32 opaque_debug_rx_suspend_cnt;
+ A_UINT32 opaque_debug_rx_resume_cnt;
+ A_UINT32 opaque_debug_rx_pcie_suspend_cnt;
+ A_UINT32 opaque_debug_rx_pcie_resume_cnt;
+ /** This word contains the following bitfields:
+ * wal_pdev fields
+ * pdev paused - WMI_PDEV_STATS_PAUSED_SET,GET
+ * pdev suspend - WMI_PDEV_STATS_SUSPENDED_SET,GET
+ * cac_enabed - MI_PDEV_STATS_CAC_ENABLED_SET,GET
+ * monitor VAP present - WMI_PDEV_STATS_IS_MONITOR_TYPE_PRESENT_SET,GET
+ * beacon tx mode - WMI_PDEV_STATS_BCN_TX_MODE_SET,GET
+ * isTXsuspended - WMI_PDEV_STATS_IS_TXSUSPENDED_SET,GET
+ * isSCHEDsuspended - WMI_PDEV_STATS_IS_SCHEDSUSPENDED_SET,GET
+ * sched_algo_resume_needed -
+ * WMI_PDEV_STATS_SCHED_ALGO_RESUME_NEEDED_SET,GET
+ * abort_reason - WMI_PDEV_STATS_ABORT_REASON_SET,GET
+ * atf_cfg - WMI_PDEV_STATS_ATF_CONFIG_SET,GET
+ * Green AP TX chainmask valid - WMI_PDEV_STATS_GAP_TX_CH_MASK_VALID_SET,GET
+ * Green AP RX chainmask valid - WMI_PDEV_STATS_GAP_RX_CH_MASK_VALID_SET,GET
+ * Green AP Phy mode valid - WMI_PDEV_STATS_GAP_PHY_MODE_VALID_SET,GET
+ * burst_enable - WMI_PDEV_STATS_BURST_ENABLE_SET,GET
+ */
+ A_UINT32 opaque_debug_wal_pdev_bitfield;
+ /** This word contains the following bitfields:
+ * gap_phy_mode_freq:
+ * When GreenAP is enabled, phy_mode (WMI_PDEV_STATS_GAP_PHY_MODE_SET,GET)
+ * and center freq(MHz) (WMI_PDEV_STATS_GAP_BAND_CENTER_FREQ1_SET,GET)
+ * in GAP context is displayed
+ */
+ A_UINT32 opaque_debug_gap_phy_mode_freq;
+ /**
+ * The following 5 opaque_debug_reserved_field variables are provided
+ * purely for debugging by technicians who have outside knowledge of
+ * what kind of values the target has placed into these fields.
+ */
+ A_UINT32 opaque_debug_reserved_field_1;
+ A_UINT32 opaque_debug_reserved_field_2;
+ A_UINT32 opaque_debug_reserved_field_3;
+ A_UINT32 opaque_debug_reserved_field_4;
+ A_UINT32 opaque_debug_reserved_field_5;
} wmi_ctrl_path_pdev_stats_struct;
+#define WMI_PDEV_STATS_NUM_MACS_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_PDEV_STATS_NUM_MACS_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_PDEV_STATS_NUM_PHY_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_PDEV_STATS_NUM_PHY_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_PDEV_STATS_VDEV_UP_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_PDEV_STATS_VDEV_UP_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_PDEV_STATS_VDEV_ACTIVE_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+#define WMI_PDEV_STATS_VDEV_ACTIVE_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_PDEV_STATS_REMOTE_PEER_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PDEV_STATS_REMOTE_PEER_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PDEV_STATS_MAX_RF_CHAIN_2G_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_PDEV_STATS_MAX_RF_CHAIN_2G_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_PDEV_STATS_MAX_RF_CHAIN_5G_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+#define WMI_PDEV_STATS_MAX_RF_CHAIN_5G_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_PDEV_STATS_EMA_MAX_VAP_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8 )
+#define WMI_PDEV_STATS_EMA_MAX_VAP_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8 , val)
+#define WMI_PDEV_STATS_EMA_MAX_PROFILE_PERIOD_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_PDEV_STATS_EMA_MAX_PROFILE_PERIOD_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_PDEV_STATS_NUM_SELF_PEERS_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_PDEV_STATS_NUM_SELF_PEERS_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_PDEV_STATS_MAX_ACTIVE_VDEVS_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+#define WMI_PDEV_STATS_MAX_ACTIVE_VDEVS_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_PDEV_STATS_NUM_MAX_HW_LINKS_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_PDEV_STATS_NUM_MAX_HW_LINKS_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_PDEV_STATS_CURRENT_CHIP_ID_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_PDEV_STATS_CURRENT_CHIP_ID_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_PDEV_STATS_MAX_NUM_CHIPS_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_PDEV_STATS_MAX_NUM_CHIPS_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_PDEV_STATS_NUM_HOME_CHANS_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+#define WMI_PDEV_STATS_NUM_HOME_CHANS_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_PDEV_STATS_AGG_RETRY_TH_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_PDEV_STATS_AGG_RETRY_TH_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_PDEV_STATS_NON_AGG_RETRY_TH_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_PDEV_STATS_NON_AGG_RETRY_TH_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_PDEV_STATS_MAX_NON_DATA_RETRY_TH_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_PDEV_STATS_MAX_NON_DATA_RETRY_TH_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_PDEV_STATS_NUM_CONSECUTIVE_BCN_TX_FILT_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+#define WMI_PDEV_STATS_NUM_CONSECUTIVE_BCN_TX_FILT_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_PDEV_STATS_NUM_RX_BA_SESSIONS_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PDEV_STATS_NUM_RX_BA_SESSIONS_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PDEV_STATS_MAX_RX_BA_SESSIONS_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+#define WMI_PDEV_STATS_MAX_RX_BA_SESSIONS_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_PDEV_STATS_PPDU_DUR_LIMIT_US_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PDEV_STATS_PPDU_DUR_LIMIT_US_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PDEV_STATS_MU_PPDU_DUR_LIMIT_US_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+#define WMI_PDEV_STATS_MU_PPDU_DUR_LIMIT_US_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_PDEV_STATS_RTS_RC_FLAGS_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_PDEV_STATS_RTS_RC_FLAGS_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_PDEV_STATS_RTS_RC_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_PDEV_STATS_RTS_RC_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_PDEV_STATS_GAP_TX_CH_MASK_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_PDEV_STATS_GAP_TX_CH_MASK_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_PDEV_STATS_GAP_RX_CH_MASK_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_PDEV_STATS_GAP_RX_CH_MASK_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+#define WMI_PDEV_STATS_GAP_PHY_MODE_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PDEV_STATS_GAP_PHY_MODE_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PDEV_STATS_GAP_BAND_CENTER_FREQ1_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_PDEV_STATS_GAP_BAND_CENTER_FREQ1_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+#define WMI_PDEV_STATS_CONSECUTIVE_FAILURE_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PDEV_STATS_CONSECUTIVE_FAILURE_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PDEV_STATS_NUM_FILS_DISC_ENQD_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+#define WMI_PDEV_STATS_NUM_FILS_DISC_ENQD_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_PDEV_STATS_RESET_CAUSE_BITMAP_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_PDEV_STATS_RESET_CAUSE_BITMAP_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_PDEV_STATS_SWBA_NUM_OF_VDEVS_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+#define WMI_PDEV_STATS_SWBA_NUM_OF_VDEVS_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_PDEV_STATS_HOME_CHAN_MHZ_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PDEV_STATS_HOME_CHAN_MHZ_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PDEV_STATS_HOME_CHAN_FLAGS_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+#define WMI_PDEV_STATS_HOME_CHAN_FLAGS_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_PDEV_STATS_HOME_CHAN_BAND_FREQ_1_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PDEV_STATS_HOME_CHAN_BAND_FREQ_1_SET(flag,val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PDEV_STATS_HOME_CHAN_BAND_FREQ_2_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+#define WMI_PDEV_STATS_HOME_CHAN_BAND_FREQ_2_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_PDEV_STATS_CUR_CHAN_MHZ_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PDEV_STATS_CUR_CHAN_MHZ_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PDEV_STATS_CUR_CHAN_FLAGS_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+#define WMI_PDEV_STATS_CUR_CHAN_FLAGS_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_PDEV_STATS_CUR_CHAN_BAND_FREQ_1_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PDEV_STATS_CUR_CHAN_BAND_FREQ_1_SET(flag,val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PDEV_STATS_CUR_CHAN_BAND_FREQ_2_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+#define WMI_PDEV_STATS_CUR_CHAN_BAND_FREQ_2_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_PDEV_STATS_BURST_MODE_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_PDEV_STATS_BURST_MODE_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_PDEV_STATS_PENDING_ISR_STATUS_GET(flag) \
+ WMI_GET_BITS(flag, 8, 16)
+#define WMI_PDEV_STATS_PENDING_ISR_STATUS_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 16, val)
+#define WMI_PDEV_STATS_BCN_Q_NUM_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_PDEV_STATS_BCN_Q_NUM_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_PDEV_STATS_NUM_BCNS_QUEUED_TO_HW_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_PDEV_STATS_NUM_BCNS_QUEUED_TO_HW_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_PDEV_STATS_SWFDA_VDEV_ID_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_PDEV_STATS_SWFDA_VDEV_ID_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+
+#define WMI_PDEV_STATS_ABORT_RESULT_GET(flag) \
+ WMI_GET_BITS(flag, 0, 1)
+#define WMI_PDEV_STATS_ABORT_RESULT_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 1, val)
+#define WMI_PDEV_STATS_SCHED_ALGO_RESUME_NEEDED_GET(flag) \
+ WMI_GET_BITS(flag, 1, 1)
+#define WMI_PDEV_STATS_SCHED_ALGO_RESUME_NEEDED_SET(flag, val) \
+ WMI_SET_BITS(flag, 1, 1, val)
+#define WMI_PDEV_STATS_ABORT_REASON_GET(flag) \
+ WMI_GET_BITS(flag, 2, 3)
+#define WMI_PDEV_STATS_ABORT_REASON_SET(flag, val) \
+ WMI_SET_BITS(flag, 2, 3, val)
+#define WMI_PDEV_STATS_IS_TXSUSPENDED_GET(flag) \
+ WMI_GET_BITS(flag, 5, 1)
+#define WMI_PDEV_STATS_IS_TXSUSPENDED_SET(flag, val) \
+ WMI_SET_BITS(flag, 5, 1, val)
+#define WMI_PDEV_STATS_IS_SCHEDSUSPENDED_GET(flag) \
+ WMI_GET_BITS(flag, 6, 1)
+#define WMI_PDEV_STATS_IS_SCHEDSUSPENDED_SET(flag, val) \
+ WMI_SET_BITS(flag, 6, 1, val)
+#define WMI_PDEV_STATS_IS_TXSUSPENDED_WITH_AFC_GET(flag) \
+ WMI_GET_BITS(flag, 7, 1)
+#define WMI_PDEV_STATS_IS_TXSUSPENDED_WITH_AFC_SET(flag, val) \
+ WMI_SET_BITS(flag, 7, 1, val)
+#define WMI_PDEV_STATS_IS_SCHEDSUSPENDED_WITH_AFC_GET(flag) \
+ WMI_GET_BITS(flag, 8, 1)
+#define WMI_PDEV_STATS_IS_SCHEDSUSPENDED_WITH_AFC_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 1, val)
+#define WMI_PDEV_STATS_SW_RETRY_MPDU_COUNT_TH_GET(flag) \
+ WMI_GET_BITS(flag, 9, 1)
+#define WMI_PDEV_STATS_SW_RETRY_MPDU_COUNT_TH_SET(flag, val) \
+ WMI_SET_BITS(flag, 9, 1, val)
+#define WMI_PDEV_STATS_SENDBAR_COMPL_IN_PROGRESS_GET(flag) \
+ WMI_GET_BITS(flag, 10, 1)
+#define WMI_PDEV_STATS_SENDBAR_COMPL_IN_PROGRESS_SET(flag, val) \
+ WMI_SET_BITS(flag, 10, 1, val)
+#define WMI_PDEV_STATS_CAC_ENABLED_GET(flag) \
+ WMI_GET_BITS(flag, 11, 1)
+#define WMI_PDEV_STATS_CAC_ENABLED_SET(flag, val) \
+ WMI_SET_BITS(flag, 11, 1, val)
+#define WMI_PDEV_STATS_PAUSED_GET(flag) \
+ WMI_GET_BITS(flag, 12, 1)
+#define WMI_PDEV_STATS_PAUSED_SET(flag, val) \
+ WMI_SET_BITS(flag, 12, 1, val)
+#define WMI_PDEV_STATS_SUSPENDED_GET(flag) \
+ WMI_GET_BITS(flag, 13, 1)
+#define WMI_PDEV_STATS_SUSPENDED_SET(flag, val) \
+ WMI_SET_BITS(flag, 13, 1, val)
+#define WMI_PDEV_STATS_MAC_COLD_RESET_GET(flag) \
+ WMI_GET_BITS(flag, 14, 1)
+#define WMI_PDEV_STATS_MAC_COLD_RESET_SET(flag, val) \
+ WMI_SET_BITS(flag, 14, 1, val)
+#define WMI_PDEV_STATS_SAFE_TO_ACCESS_HW_GET(flag) \
+ WMI_GET_BITS(flag, 15, 1)
+#define WMI_PDEV_STATS_SAFE_TO_ACCESS_HW_SET(flag, val) \
+ WMI_SET_BITS(flag, 15, 1, val)
+#define WMI_PDEV_STATS_STA_PS_STATECHG_ENABLE_GET(flag) \
+ WMI_GET_BITS(flag, 16, 1)
+#define WMI_PDEV_STATS_STA_PS_STATECHG_ENABLE_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 1, val)
+#define WMI_PDEV_STATS_WAL_HOST_SCAN_IN_PROGRESS_GET(flag) \
+ WMI_GET_BITS(flag, 17, 1)
+#define WMI_PDEV_STATS_WAL_HOST_SCAN_IN_PROGRESS_SET(flag, val) \
+ WMI_SET_BITS(flag, 17, 1, val)
+#define WMI_PDEV_STATS_ATF_CONFIG_GET(flag) \
+ WMI_GET_BITS(flag, 18, 1)
+#define WMI_PDEV_STATS_ATF_CONFIG_SET(flag, val) \
+ WMI_SET_BITS(flag, 18, 1, val)
+#define WMI_PDEV_STATS_EAPOL_AC_OVERRIDE_GET(flag) \
+ WMI_GET_BITS(flag, 19, 1)
+#define WMI_PDEV_STATS_EAPOL_AC_OVERRIDE_SET(flag, val) \
+ WMI_SET_BITS(flag, 19, 1, val)
+#define WMI_PDEV_STATS_CALC_NEXT_DTIM_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 20, 1)
+#define WMI_PDEV_STATS_CALC_NEXT_DTIM_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 20, 1, val)
+#define WMI_PDEV_STATS_ATF_STRICT_SCH_GET(flag) \
+ WMI_GET_BITS(flag, 21, 1)
+#define WMI_PDEV_STATS_ATF_STRICT_SCH_SET(flag, val) \
+ WMI_SET_BITS(flag, 21, 1, val)
+#define WMI_PDEV_STATS_BCN_TX_MODE_GET(flag) \
+ WMI_GET_BITS(flag, 22, 2)
+#define WMI_PDEV_STATS_BCN_TX_MODE_SET(flag, val) \
+ WMI_SET_BITS(flag, 22, 2, val)
+#define WMI_PDEV_STATS_IS_MONITOR_TYPE_PRESENT_GET(flag) \
+ WMI_GET_BITS(flag, 24, 1)
+#define WMI_PDEV_STATS_IS_MONITOR_TYPE_PRESENT_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 1, val)
+#define WMI_PDEV_STATS_DYN_BW_GET(flag) \
+ WMI_GET_BITS(flag, 25, 1)
+#define WMI_PDEV_STATS_DYN_BW_SET(flag, val) \
+ WMI_SET_BITS(flag, 25, 1, val)
+#define WMI_PDEV_STATS_IS_MLO_SUPPORTED_GET(flag) \
+ WMI_GET_BITS(flag, 26, 1)
+#define WMI_PDEV_STATS_IS_MLO_SUPPORTED_SET(flag, val) \
+ WMI_SET_BITS(flag, 26, 1, val)
+#define WMI_PDEV_STATS_GAP_TX_CH_MASK_VALID_GET(flag) \
+ WMI_GET_BITS(flag, 27, 1)
+#define WMI_PDEV_STATS_GAP_TX_CH_MASK_VALID_SET(flag, val) \
+ WMI_SET_BITS(flag, 27, 1, val)
+#define WMI_PDEV_STATS_GAP_RX_CH_MASK_VALID_GET(flag) \
+ WMI_GET_BITS(flag, 28, 1)
+#define WMI_PDEV_STATS_GAP_RX_CH_MASK_VALID_SET(flag, val) \
+ WMI_SET_BITS(flag, 28, 1, val)
+#define WMI_PDEV_STATS_GAP_PHY_MODE_VALID_GET(flag) \
+ WMI_GET_BITS(flag, 29, 1)
+#define WMI_PDEV_STATS_GAP_PHY_MODE_VALID_SET(flag, val) \
+ WMI_SET_BITS(flag, 29, 1, val)
+#define WMI_PDEV_STATS_GAP_CLKGATE_VALID_GET(flag) \
+ WMI_GET_BITS(flag, 30, 1)
+#define WMI_PDEV_STATS_GAP_CLKGATE_VALID_SET(flag, val) \
+ WMI_SET_BITS(flag, 30, 1, val)
+#define WMI_PDEV_STATS_BURST_ENABLE_GET(flag) \
+ WMI_GET_BITS(flag, 31, 1)
+#define WMI_PDEV_STATS_BURST_ENABLE_SET(flag, val) \
+ WMI_SET_BITS(flag, 31, 1, val)
+
typedef struct {
/** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_btcoex_stats_struct*/
A_UINT32 tlv_header;
@@ -12546,6 +13162,924 @@
A_UINT32 cfr_resp_failure_count;
} wmi_ctrl_path_cfr_stats_struct;
+
+#define WMI_MAX_MLO_LINKS 5
+#define WMI_HE_MAP_COUNT 3
+#define WMI_EHT_MAP_COUNT 3
+
+typedef struct {
+ /* TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_ctrl_path_peer_stats_struct
+ */
+ A_UINT32 tlv_header;
+ /* mac address - part of wlan_peer */
+ wmi_mac_addr mac_addr;
+ /* wlan_peer flags - refer to IEEE80211_NODE_* flags in wlan_peer.h */
+ A_UINT32 opaque_debug_flags;
+ /* opaque_debug_vht_caps:
+ * Negotiated VHT capabilities in the wlan_peer struct
+ * Refer to ieee80211_defs.h.
+ */
+ A_UINT32 opaque_debug_vht_caps;
+ /* opaque_debug_flags_ext:
+ * Extended flags in the wlan_peer struct
+ * Refer to IEEE80211_NODE_* flags in wlan_peer.h.
+ */
+ A_UINT32 opaque_debug_flags_ext;
+ /* TID queues marked for TWT flush, present in wlan_peer */
+ A_UINT32 opaque_debug_twt_flush_tidmap;
+ /* Number of TWT SPs to be expired, present in wlan_peer */
+ A_UINT32 opaque_debug_n_TWT_SPs_to_expire;
+ /* opaque_debug_rc_flags:
+ * Peer rate information, part of struct rate_node
+ * Refer to whal_rate_api.h for complete RC_FLAGS details.
+ */
+ A_UINT32 opaque_debug_rc_flags;
+ /* opaque_debug_sm_event_mask_eosp_cnt:
+ * This word contains the following bitfields:
+ * - Power save state machine event mask,
+ * part of wal_ps_buf_peer_handle_t.
+ * Refer to enum wal_ps_buf_peer_reg_ev_handlers.
+ * Use WMI_PEER_STATS_SM_MASK_SET,GET macros.
+ * - End of service period (EOSP) sent retry counter,
+ * part of wal_ps_buf_peer_handle_t.
+ * Use WMI_PEER_STATS_EOSP_RETRY_CNT_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_sm_event_mask_eosp_cnt;
+ /* opaque_debug_ps_buf_peer_flag1:
+ * Power save related send_n, ps_poll, unscheduled service period
+ * related fields;
+ * Part of wal_ps_buf_peer_handle_t.
+ * Refer to wal_ps_buf_peer_ctx struct definition.
+ */
+ A_UINT32 opaque_debug_ps_buf_peer_flag1;
+ /* opaque_debug_ps_buf_peer_flag2:
+ * Power save related trigger/delivery tid related fields.
+ * part of wal_ps_buf_peer_handle_t.
+ * Refer to wal_ps_buf_peer_ctx struct definition.
+ */
+ A_UINT32 opaque_debug_ps_buf_peer_flag2;
+ /* opaque_debug_ps_buf_peer_flag3:
+ * Power save related last trigger related information,
+ * part of wal_ps_buf_peer_handle_t.
+ * Refer to wal_ps_buf_peer_ctx struct definition.
+ */
+ A_UINT32 opaque_debug_ps_buf_peer_flag3;
+ /* opaque_debug_last_rx_trigger_time:
+ * Time of the most recently received uplink trigger frame,
+ * part of wal_ps_buf_peer_handle_t - in microseconds units.
+ */
+ A_UINT32 opaque_debug_last_rx_trigger_time;
+ /* opaque_debug_last_poll_time:
+ * TSF of the most recently received uplink PS-Poll,
+ * part of wal_ps_buf_peer_handle_t - in TU
+ */
+ A_UINT32 opaque_debug_last_poll_time;
+ /* opaque_debug_oldest_tx_buffered_waiting_ms:
+ * Enqueue time of most recent MSDU that AP has buffered for
+ * sleeping station, part of wal_ps_buf_peer_handle_t, in ms units.
+ */
+ A_UINT32 opaque_debug_oldest_tx_buffered_waiting_ms;
+ /* opaque_debug_last_rxtx_activity:
+ * The last time when there was a rx or tx traffic from a client,
+ * part of wal_ps_buf_peer_handle_t, in ms units.
+ */
+ A_UINT32 opaque_debug_last_rxtx_activity;
+ /* opaque_debug_twt_flush_expiry_timestamp:
+ * Peer's TWT flush expiry timestamp in us,
+ * part of peer_twt_flush struct.
+ */
+ A_UINT32 opaque_debug_twt_flush_expiry_timestamp;
+ /* opaque_debug_hw_link_id:
+ * Unique link id across SOCs, determined during QMI handshake,
+ * part of wlan_peer_ml_info_t.
+ */
+ A_UINT32 opaque_debug_hw_link_id;
+ /* opaque_debug_ml_partner_hw_link_id_bitmap:
+ * Hardware link id of the of partner links that are to be cleaned up.
+ * This is filled by host during peer delete cmd.
+ * It it part of wlan_peer_ml_info_t.
+ */
+ A_UINT32 opaque_debug_ml_partner_hw_link_id_bitmap;
+ /* opaque_debug_link_flags:
+ * MLO link flags: related to assoc, anchor, master and primary UMAC links.
+ * Refer to resmgr_mlo_link_flags.
+ * Part of wlan_peer_ml_info_t.
+ */
+ A_UINT32 opaque_debug_link_flags;
+ /* MLO peer id - part of wlan_ml_peer_t */
+ A_UINT32 opaque_debug_ml_peer_id;
+ /* MLD mac address - part of wlan_ml_peer_t */
+ wmi_mac_addr opaque_debug_mld_mac_addr;
+ /* opaque_debug_assoc_id_usage_cnt:
+ * Part of wlan_peer.
+ * This word contains the following bitfields:
+ * - assoc id of the peer
+ * Use WMI_PEER_STATS_ASSOCIATE_ID_SET,GET macros.
+ * - peer usage count to track if peer alloc command is sent
+ * for new or existing peer,
+ * Use WMI_PEER_STATS_USAGE_CNT_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_assoc_id_usage_cnt;
+ /* opaque_debug_default_ht_caps:
+ * Part of wlan_peer.
+ * This word contains the following bitfields:
+ * - default peer capabilities of the peer - refer ieee80211_defs.h
+ * Use WMI_PEER_STATS_DEF_CAPS_SET,GET macros.
+ * - HT capabilities of the peer - refer ieee80211_defs.h
+ * Use WMI_PEER_STATS_HT_CAPS_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_default_ht_caps;
+ /* opaque_debug_inact_gen:
+ * Part of wlan_peer.
+ * This word contains the following bitfields:
+ * - Overall tx/rx inactivity time of the peer in seconds
+ * Use WMI_PEER_STATS_INACT_GEN_SET,GET macros.
+ * - Data tx/rx inactivity time of the peer in seconds.
+ * Use WMI_PEER_STATS_DATA_INACT_GEN_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_inact_gen;
+ /* opaque_debug_id_type:
+ * Part of wlan_peer.
+ * This word contains the following bitfields:
+ * - Type of peer whether it is bss,self or remote peer.
+ * Refer to enum wmi_peer_type.
+ * Use WMI_PEER_STATS_TYPE_SET,GET macros.
+ * - MAC ID that the peer belongs to
+ * Use WMI_PEER_STATS_MAC_ID_SET,GET macros.
+ * - sw peer id of the peer
+ * Use WMI_PEER_STATS_ID_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_id_type;
+ /* Deleted tids bitmask within the peer - part of wal_peer */
+ A_UINT32 opaque_debug_deleted_tidmask;
+ /* number of local pending frames for completions - part of wal_peer */
+ A_UINT32 opaque_debug_num_of_local_frames_pending;
+ /* flags part of wal_peer - refer to wal_peer_flags_t */
+ A_UINT32 opaque_debug_wal_peer_flags;
+ /* opaque_debug_keyid0_ast_index:
+ * The AST index for key id 0 which is always allocated,
+ * part of wal_peer.
+ */
+ A_UINT32 opaque_debug_keyid0_ast_index;
+ /* opaque_debug_all_tids_block_module_bitmap:
+ * Bitmap of block IDs requesting block of all TIDs,
+ * part of wal_peer.
+ * Refer to enum WLAN_PAUSE_ID.
+ * This block/pause ID can be mapped to a WLAN_MODULE_ID module ID.
+ */
+ A_UINT32 opaque_debug_all_tids_block_module_bitmap;
+ /* opaque_debug_all_tids_pause_module_bitmap:
+ * Bitmap of pause IDs requesting block of all TIDs,
+ * part of wal_peer.
+ * Refer to enum WLAN_PAUSE_ID.
+ * This pause ID can be mapped to a WLAN_MODULE_ID module ID.
+ */
+ A_UINT32 opaque_debug_all_tids_pause_module_bitmap;
+ /* opaque_debug_data_tids_block_module_bitmap:
+ * Bitmap of block ids requesting block of data tids,
+ * part of wal_peer.
+ * Refer to enum WLAN_PAUSE_ID.
+ * This block/pause ID can be mapped to a WLAN_MODULE_ID module ID.
+ */
+ A_UINT32 opaque_debug_data_tids_block_module_bitmap;
+ /* opaque_debug_data_tids_pause_module_bitmap:
+ * Bitmap of pause ids requesting block of data tids,
+ * part of wal_peer.
+ * Refer to enum WLAN_PAUSE_ID.
+ * This pause ID can be mapped to a WLAN_MODULE_ID module ID.
+ */
+ A_UINT32 opaque_debug_data_tids_pause_module_bitmap;
+ /* The time stamp when first ppdu fails in us, part of wal_peer */
+ A_UINT32 opaque_debug_ppdu_fail_time;
+ /* opaque_debug_rate_params:
+ * This word contains the following bitfields:
+ * - Non data rate code of the peer - part of wal_peer
+ * Use WMI_PEER_STATS_BSS_NON_DATA_RC_SET,GET macros.
+ * - channel bandwidth supported by the peer, part of wal_peer.
+ * The mapping is as follows:
+ * 0 = 20 MHz, 1 = 40 MHz, 2 = 80 MHz, 3 = 160 MHz, 4 = 320 MHz
+ * Use WMI_PEER_STATS_CH_WIDTH_SET,GET macros.
+ * - MCS used for the last PPDU received from the peer, part of wal_peer
+ * Use WMI_PEER_STATS_RX_MCS_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_rate_params;
+ /* consecutive QOS null frame tx fail count, part of wal_peer */
+ A_UINT32 opaque_debug_consecutive_null_failure;
+ /* peer delete state refer enum PEER_DELETE_SM_STATE, part of wal_peer */
+ A_UINT32 opaque_debug_peer_delete_sm_state;
+ /* opaque_debug_cache_rate_info_low32,_high32:
+ * Lower/upper 32 bits respectively of cached rate info variable
+ * updated by the HTT metadata.
+ * This rate_info is based on the values from struct
+ * htt_tx_msdu_desc_ext2_t .
+ * If htt_tx_desc_ext2->update_peer_cache is set to 1 and
+ * HTT_TX_TCL_METADATA_PEER_ID_GET(tcl_cmd_num) returns valid peer ID
+ * then rate_info cache of the peer is updated.
+ * Part of wal_peer.
+ */
+ A_UINT32 opaque_debug_cache_rate_info_low32;
+ A_UINT32 opaque_debug_cache_rate_info_high32;
+ /* opaque_debug_peer_delete_rc4_rekey:
+ * This word contains the following bitfields:
+ * - Flag that denotes if Peer delete all is in progress or not,
+ * part of wal_peer.
+ * Use WMI_PEER_STATS_DELETE_ALL_FLAG_SET,GET macros.
+ * - RC4 rekey counter, part of wal_peer.
+ * Use WMI_PEER_STATS_RC4_REKEY_CNT_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_peer_delete_rc4_rekey;
+ /* opaque_debug_mcbc_tids_pause_bitmap:
+ * Bitmap containing Multicast and broadcast tids that are paused,
+ * part of wal_peer.
+ */
+ A_UINT32 opaque_debug_mcbc_tids_pause_bitmap;
+ /* opaque_debug_next_to_last_pn_low32,_high32:
+ * Lower/upper 32 bits respectively of last used PN value received,
+ * part of wal_peer.
+ */
+ A_UINT32 opaque_debug_next_to_last_pn_low32;
+ A_UINT32 opaque_debug_next_to_last_pn_high32;
+ /* opaque_debug_last_pn_low32,_high32:
+ * Lower/upper 32 bits respectively of current PN value received,
+ * part of wal_peer.
+ */
+ A_UINT32 opaque_debug_last_pn_low32;
+ A_UINT32 opaque_debug_last_pn_high32;
+ /* opaque_debug_twt_ap_peer_ctx_flags:
+ * This word contains the following bitfields:
+ * - TWT AP peer's context flags, part of twt_ap_peer_handle_t struct.
+ * Refer twt_ap_twt_session_t definition.
+ * Use WMI_PEER_STATS_TWT_AP_FLAGS_SET,GET macros.
+ * - TWT session counter, part of twt_ap_peer_handle_t struct.
+ * Use WMI_PEER_STATS_TWT_AP_SESSION_CNT_SET,GET macros.
+ * - TWT frame retry counter, part of twt_ap_peer_handle_t struct.
+ * Use WMI_PEER_STATS_TWT_FRM_RETRY_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_twt_ap_peer_ctx_flags;
+ /* opaque_debug_twt_ap_counters:
+ * This word contains the following bitfields:
+ * - TWT UL trigger counter, part of twt_ap_peer_handle_t struct.
+ * Use WMI_PEER_STATS_TWT_UL_TRIGGER_SET,GET macros.
+ * - TWT Broadcast session counter, part of twt_ap_peer_handle_t struct.
+ * Use WMI_PEER_STATS_TWT_BC_SESSION_SET,GET macros.
+ * - TWT pending report counter, part of twt_ap_peer_handle_t struct.
+ * Use WMI_PEER_STATS_TWT_PENDING_REPORT_SET,GET macros.
+ * - TWT flow IDs, part of twt_ap_peer_handle_t struct.
+ * Use WMI_PEER_STATS_TWT_FLOW_IDS_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_twt_ap_counters;
+ /* opaque_debug_tx_state_bmap_low32,_high32:
+ * Lower/upper 32 bits respectively of list of currently running
+ * BA Tx states for tids in this peer, part of wal_ba_peer_handle_t.
+ */
+ A_UINT32 opaque_debug_tx_state_bmap_low32;
+ A_UINT32 opaque_debug_tx_state_bmap_high32;
+ /* opaque_debug_addba_mode:
+ * This word contains the following bitfields:
+ * - ADDBA mode whether its automatic or manual,
+ * WAL_BA_ADDBA_MODE_AUTO = 0 and WAL_BA_ADDBA_MODE_MANUAL = 1
+ * Part of wal_ba_peer_handle_t.
+ * Use WMI_PEER_STATS_ADDBBA_TX_MODE_SET,GET macros.
+ * - ADDBA request's response code, part of wal_ba_peer_handle_t.
+ * Use WMI_PEER_STATS_ADDBBA_RESP_MODE_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_addba_mode;
+ /* opaque_debug_tx_retry_bmap:
+ * Bitmap of tids and their TX BlockAck retry counters.
+ * Each TID uses 2 bits for its BA retry counter.
+ * Part of wal_ba_peer_handle_t.
+ */
+ A_UINT32 opaque_debug_tx_retry_bmap;
+ /* opaque_debug_rx_state_bmap:
+ * Bitmap of tids and their RX BlockAck retry counters.
+ * 00 - BA not setup
+ * 01 - BA in progress
+ * 10 - reserved
+ * 11 - BA setup.
+ * Each TID uses 2 bits for its BA RX state;
+ * for instance TID 0's BA info occupies bits 1:0 and so on.
+ * Part of wal_ba_peer_handle_t.
+ */
+ A_UINT32 opaque_debug_rx_state_bmap;
+ /* opaque_debug_tx_pending_delba_tid_bmap:
+ * TID bitmap containaing information DELBA tx pending,
+ * part of wal_ba_peer_handle_t.
+ */
+ A_UINT32 opaque_debug_tx_pending_delba_tid_bmap;
+ /* opaque_debug_link_monitor_tid_num:
+ * link monitor tid num in bss_peer ba_peer_handle,
+ * part of wal_ba_peer_handle_t.
+ */
+ A_UINT32 opaque_debug_link_monitor_tid_num;
+ /* opaque_debug_rc4_eapol_key_complete:
+ * Flag that denotes rc4 eapol key exchange is complete,
+ * part of wal_peer_ext.
+ */
+ A_UINT32 opaque_debug_rc4_eapol_key_complete;
+ /* qcache peer flags, refer to qpeer_flags_t */
+ A_UINT32 opaque_debug_qpeer_flags;
+ /* bitmap of TIDs requested for flush, part of wal_qcache_peer */
+ A_UINT32 opaque_debug_delete_requested_tidmask;
+ /* bitmap of created TIDs, part of wal_qcache_peer */
+ A_UINT32 opaque_debug_tid_created_tidmask;
+ /* opaque_debug_qpeer_rt_flags0,_flags1,_flags2:
+ * RT thread related fields in qpeer, refer to _wal_qcache_peer.
+ */
+ A_UINT32 opaque_debug_qpeer_rt_flags0;
+ A_UINT32 opaque_debug_qpeer_rt_flags1;
+ A_UINT32 opaque_debug_qpeer_rt_flags2;
+ /* opaque_debug_qpeer_sa_flags0,_flags1:
+ * SA thread related fields in qpeer, refer to _wal_qcache_peer.
+ */
+ A_UINT32 opaque_debug_qpeer_sa_flags0;
+ A_UINT32 opaque_debug_qpeer_sa_flags1;
+ /* BE thread related fields in qpeer, refer to _wal_qcache_peer */
+ A_UINT32 opaque_debug_qpeer_be_flags;
+ /* qpeer event bitmap, refer to wal_peer_event_type */
+ A_UINT32 opaque_debug_event_bitmap;
+ /* tx fail count for a peer, part of dcache peer */
+ A_UINT32 opaque_debug_seq_no_tx_fail_cnt;
+ /* Last transmission rate in kbps for a peer, part of dcache peer */
+ A_UINT32 opaque_debug_last_tx_rate_kbps;
+ /* opaque_debug_amsdu_size:
+ * This word contains the following bitfields:
+ * - MAX AMSDU size of the peer, part of dcache peer.
+ * Use WMI_PEER_STATS_MAX_AMSDU_SIZE_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_amsdu_size;
+ /* opaque_debug_fake_sleep_time:
+ * Time elapsed in ms after entering into fake sleep after xretry failure,
+ * part of dcache peer.
+ */
+ A_UINT32 opaque_debug_fake_sleep_time;
+ /* opaque_debug_tx_frame_qos_ctrl:
+ * This word contains the following bitfields:
+ * - Tx frame control FC flags in ieee80211_defs.h, part of dcache peer.
+ * Use WMI_PEER_STATS_TX_FRAME_CTRL_SET,GET macros.
+ * - Tx QOS control FC flags in ieee80211_defs.h, part of dcache peer.
+ * Use WMI_PEER_STATS_TX_QOS_CTRL_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_tx_frame_qos_ctrl;
+ /* opaque_debug_consec_fail_subfrm_sz:
+ * This word contains the following bitfields:
+ * - Consecutive tx fail count for the peer, part of dcache peer.
+ * Use WMI_PEER_STATS_CONSEC_FAIL_SET,GET macros.
+ * - subframe size configured for the peer, part of dcache peer.
+ * Use WMI_PEER_STATS_SUBFRAME_SIZE_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_consec_fail_subfrm_sz;
+ /* opaque_debug_tx_fail_partial_aid:
+ * This word contains the following bitfields:
+ * - tx fail count for the peer, part of dcache peer.
+ * Use WMI_PEER_STATS_TX_FAIL_CNT_SET,GET macros.
+ * - Partial AID of the peer, part of dcache peer.
+ * Use WMI_PEER_STATS_TX_PARTIAL_AID_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_tx_fail_partial_aid;
+ /* opaque_debug_max_nss:
+ * Part of dcache peer.
+ * This word contains the following bitfields:
+ * - Peer NSS value sent by host during WMI_PEER_ASSOC cmd.
+ * Use WMI_PEER_STATS_MAX_NSS_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_max_nss;
+ /* opaque_debug_he_cap_info:
+ * Peer HE capabilities info sent during peer assoc cmd.
+ * Refer to WMI_HECAP_* macros in wmi_unified.h.
+ * Part of dcache peer.
+ */
+ A_UINT32 opaque_debug_he_cap_info;
+ /* opaque_debug_he_cap_info_ext:
+ * Peer extended HE capabilities info sent during peer assoc cmd.
+ * Refer to WMI_HECAP_* macros in wmi_unified.h.
+ * Part of dcache peer.
+ */
+ A_UINT32 opaque_debug_he_cap_info_ext;
+ /* opaque_debug_eht_cap_info:
+ * Peer EHT capabilities info.
+ * Refer to ieee80211_defs.h, part of dcache peer.
+ */
+ A_UINT32 opaque_debug_eht_cap_info;
+ /* TAC thread related fields in dcache peer refer wal_dcache_peer_t */
+ A_UINT32 opaque_debug_dcache_tac_flags;
+ /* RT thread related fields in dcache peer refer wal_dcache_peer_t */
+ A_UINT32 opaque_debug_dcache_rt_flags;
+ /* Supported RC modes for the peer refer enum RC_MODE, part of dcache */
+ A_UINT32 opaque_debug_rc_mode_supported_mask;
+ /* opaque_debug_wlan_peer_bitfield_mask:
+ * Part of wlan peer. This word contains the following bitfields:
+ * - Flag that denotes whether peer delete response is being sent
+ * to host or not.
+ * Use WMI_PEER_STATS_DEL_RESP_TO_HOST_SET,GET macros.
+ * - Flag that denotes if peer delete is in progress or not.
+ * Use WMI_PEER_STATS_DELETE_IN_PROGRESS_SET,GET macros.
+ * - Flag that denotes if peer migration is in progress or not.
+ * Use WMI_PEER_STATS_MIGRATION_IN_PROGRESS_SET,GET macros.
+ * - Flag that denotes peer's connection/authorized state.
+ * Refer WAL_PEER_STATE_* macros in wal_peer.h.
+ * Use WMI_PEER_STATS_CONN_STATE_SET,GET macros.
+ * - TX chain mask at 160MHz of the peer set during peer assoc command.
+ * Use WMI_PEER_STATS_TX_CHAIN_MASK_160_SET,GET macros.
+ * - Tx chain mask set during peer assoc command.
+ * Use WMI_PEER_STATS_TX_CHAIN_MASK_SET,GET macros.
+ * - copy of tx chain mask of peer saved for AP MIMO PS.
+ * Use WMI_PEER_STATS_ASSOC_CHAIN_MASK_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_wlan_peer_bitfield_mask;
+ /* opaque_debug_wal_peer_bitfields:
+ * Part of wal_peer. This word contains the following bitfields:
+ * - Flag that denotes if QOS null is sent over WMI or not.
+ * Use WMI_PEER_STATS_QOS_NULL_OVER_WMI_SET,GET macros.
+ * - Flag that denotes whether peer assoc is received
+ * for the first time or not.
+ * Use WMI_PEER_STATS_NEW_ASSOC_SET,GET macros.
+ * - Flag that denotes whether TWT filter is enabled or not.
+ * Use WMI_PEER_STATS_TWT_FILT_FLAG_SET,GET macros.
+ * - Flag that denotes whether TWT is registered or not.
+ * Use WMI_PEER_STATS_TWT_REG_FLAG_SET,GET macros.
+ * - Flag that denotes whether WMM txQ uplink trigger is disabled or not.
+ * Use WMI_PEER_STATS_WMM_UL_TRIG_FLAG_SET,GET macros.
+ * - Number of active TIDs that do not have BA setup.
+ * Use WMI_PEER_STATS_ACTIVE_NOT_BA_TID_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_wal_peer_bitfields;
+ /* flags in RT context refer wal_peer_ext_t */
+ A_UINT32 opaque_debug_wal_peer_rt_flags;
+ /* opaque_debug_ml_attributes:
+ * Part of wal_ml_peer. This word contains the following bitfields:
+ * - Num of MLO links
+ * Use WMI_PEER_STATS_NUM_LINKS_SET,GET macros.
+ * - ML peer id
+ * Use WMI_PEER_STATS_ML_PEER_ID_SET,GET macros.
+ * - Primary link ID
+ * Use WMI_PEER_STATS_PRI_LINK_ID_SET,GET macros.
+ * - Primary chip ID
+ * Use WMI_PEER_STATS_PRI_CHIP_ID_SET,GET macros.
+ * - Initial link count
+ * Use WMI_PEER_STATS_LINK_INIT_CNT_SET,GET macros.
+ * - Number of local links
+ * Use WMI_PEER_STATS_NUM_LOCAL_LINKS_SET,GET macros.
+ * - Bitmap of participating chips
+ * Use WMI_PEER_STATS_CHIPS_BITMAP_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_ml_attributes;
+ /* wal peer MLO flags refer ml_peer_flags_t */
+ A_UINT32 opaque_debug_ml_flags;
+ /* opaque_debug_ml_link_info_flags:
+ * Part of link_info in wlan_peer_ml_info_t.
+ * This word contains the following bitfields:
+ * - flag denoting if MLO-link is valid or not
+ * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_VALID_SET,GET macros.
+ * - flag denoting if MLO-link is active or not
+ * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_ACTIVE_SET,GET macros.
+ * - flag denoting if MLO-link is primary or not
+ * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_PRI_SET,GET macros.
+ * - flag denoting if MLO-link is assoc link or not
+ * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_ASSOC_LINK_SET,GET macros.
+ * - Chip ID of the MLO-link
+ * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_CHIP_ID_SET,GET macros.
+ * - IEEE link ID of the MLO-link
+ * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_IEEE_LINK_SET,GET macros.
+ * - HW link ID of the MLO-link
+ * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_HW_LINK_SET,GET macros.
+ * - logical link ID of the MLO-link
+ * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_LOGICAL_LINK_SET,GET macros.
+ * - flag denoting if MLO-link is master link or not
+ * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_MASTER_LINK_SET,GET macros.
+ * - flag denoting if MLO-link is anchor link or not
+ * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_ANCHOR_LINK_SET,GET macros.
+ * - flag denoting if MLO-link is initialized or not
+ * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_INIT_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_ml_link_info_flags[WMI_MAX_MLO_LINKS];
+ /* opaque_debug_ml_link_info_id:
+ * Part of link_info in wlan_peer_ml_info_t.
+ * This word contains the following bitfields:
+ * - sw_peer_id corresponding to the link
+ * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_PEER_ID_SET,GET macros.
+ * - vdev id corresponding to the link
+ * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_VDEV_ID_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_ml_link_info_id[WMI_MAX_MLO_LINKS];
+ /* MLO link info primary tid mask, part of link_info in wlan_peer_ml_info_t */
+ A_UINT32 opaque_debug_ml_link_info_pri_tidmask[WMI_MAX_MLO_LINKS];
+ /* opaque_debug_rc_node_params:
+ * Part of struct TX_PEER_PARAMS.
+ * This word contains the following bitfields:
+ * - NSS of the peer in 160MHZ
+ * Use WMI_PEER_STATS_NSS_160_SET,GET macros.
+ * - phymode of the peer - refer enum WLAN_PHY_MODE
+ * Use WMI_PEER_STATS_RC_PHYMODE_SET,GET macros.
+ * - legacy rate set for the peer
+ * Use WMI_PEER_STATS_LEGACY_RATE_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_rc_node_params;
+ /* opaque_debug_rc_vht_mcs_set:
+ * Rate node param - negotiated VHT MCS map,
+ * part of struct TX_PEER_PARAMS
+ */
+ A_UINT32 opaque_debug_rc_vht_mcs_set;
+ /* opaque_debug_rc_node_params1:
+ * Part of link_info in wlan_peer_ml_info_t.
+ * This word contains the following bitfields:
+ * - Minimum data rate set for the peer in Mbps
+ * Use WMI_PEER_STATS_MIN_DATA_RATE_SET,GET macros.
+ * - Max VHT rate set for the peer
+ * Use WMI_PEER_STATS_VHT_MAX_RATE_SET,GET macros.
+ * - Max VHT streams set for the peer
+ * Use WMI_PEER_STATS_VHT_MAX_STREAMS_SET,GET macros.
+ * - BSS - Channel frequency set for the peer in MHz
+ * Use WMI_PEER_STATS_RC_CHAN_FREQ_SET,GET macros.
+ */
+ A_UINT32 opaque_debug_rc_node_params1;
+ /* opaque_debug_he_mcs_nss_set_tx,_rx:
+ * Rate node param - negotiated HE MCS tx+rx maps,
+ * part of struct TX_PEER_PARAMS.
+ * The lower 8 bits (bits 23:16) within the upper 16 bits indicate
+ * MCS 12/13 enablement for BW <= 80MHz; the upper 8 bits (bits 31:24)
+ * within the 16 bits indicate MCS 12/13 enablement for BW > 80MHz.
+ * The 16 bits for the index values are within the upper bits (bits 31:16)
+ * of a 32-bit word. and WMI_HE_MAP_COUNT is based on HE_MCS_MAP_CNT
+ * in ieee80211_defs.h.
+ */
+ A_UINT32 opaque_debug_he_mcs_nss_set_tx[WMI_HE_MAP_COUNT];
+ A_UINT32 opaque_debug_he_mcs_nss_set_rx[WMI_HE_MAP_COUNT];
+ /* opaque_debug_eht_mcs_nss_set_tx,_rx:
+ * Rate node param - negotiated EHT MCS tx+rx maps,
+ * part of struct TX_PEER_PARAMS.
+ * B0-B3 indicates max NSS that supports mcs 0-7
+ * B4-B7 indicates max NSS that supports mcs 8-9
+ * B8-B11 indicates max NSS that supports mcs 10-11
+ * B12-B15 indicates max NSS that supports mcs 12-13
+ * B16-B31 reserved.
+ * WMI_EHT_MAP_COUNT is based on EHT_MCS_MAP_CNT in ieee80211_defs.h.
+ */
+ A_UINT32 opaque_debug_eht_mcs_nss_set_tx[WMI_EHT_MAP_COUNT];
+ A_UINT32 opaque_debug_eht_mcs_nss_set_rx[WMI_EHT_MAP_COUNT];
+ /* opaque_debug_rc_user_start_mcs_rate:
+ * Rate node user_start_rate is MCS value set based on phymode.
+ * For possible values refer "INITIAL_" macros in ratectrl.h.
+ * Part of struct TX_PEER_PARAMS.
+ * This is the starting value of MCS that was used by rate control
+ * for the first transmissions to the peer, until PER information
+ * from the peer allowed the rate control algorithm to determine
+ * the suitable MCS.
+ */
+ A_UINT32 opaque_debug_rc_user_start_mcs_rate;
+ /*
+ * The following 4 opaque_debug_field variables are provided purely
+ * for debugging by technicians who have outside knowledge of what
+ * kind of values the target has placed into these fields.
+ * They are not to be interpreted by the host driver in any manner.
+ */
+ A_UINT32 opaque_debug_field_1;
+ A_UINT32 opaque_debug_field_2;
+ A_UINT32 opaque_debug_field_3;
+ A_UINT32 opaque_debug_field_4;
+} wmi_ctrl_path_peer_stats_struct;
+
+#define WMI_PEER_STATS_SM_MASK_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PEER_STATS_SM_MASK_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PEER_STATS_EOSP_RETRY_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_PEER_STATS_EOSP_RETRY_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+/* bits 31:24 unused/reserved */
+
+#define WMI_PEER_STATS_ASSOCIATE_ID_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PEER_STATS_ASSOCIATE_ID_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PEER_STATS_USAGE_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_PEER_STATS_USAGE_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+#define WMI_PEER_STATS_DEF_CAPS_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PEER_STATS_DEF_CAPS_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PEER_STATS_HT_CAPS_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_PEER_STATS_HT_CAPS_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+#define WMI_PEER_STATS_INACT_GEN_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PEER_STATS_INACT_GEN_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PEER_STATS_DATA_INACT_GEN_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_PEER_STATS_DATA_INACT_GEN_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+#define WMI_PEER_STATS_PEER_TYPE_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_PEER_STATS_PEER_TYPE_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_PEER_STATS_MAC_ID_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_PEER_STATS_MAC_ID_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_PEER_STATS_PEER_ID_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_PEER_STATS_PEER_ID_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+#define WMI_PEER_STATS_BSS_NON_DATA_RC_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_PEER_STATS_BSS_NON_DATA_RC_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_PEER_STATS_CH_WIDTH_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_PEER_STATS_CH_WIDTH_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_PEER_STATS_RX_MCS_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_PEER_STATS_RX_MCS_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+/* bits 31:24 unused/reserved */
+
+#define WMI_PEER_STATS_DELETE_ALL_FLAG_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_PEER_STATS_DELETE_ALL_FLAG_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_PEER_STATS_RC4_REKEY_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_PEER_STATS_RC4_REKEY_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+/* bits 31:16 unused/reserved */
+
+#define WMI_PEER_STATS_TWT_AP_FLAGS_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PEER_STATS_TWT_AP_FLAGS_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PEER_STATS_TWT_AP_SESSION_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_PEER_STATS_TWT_AP_SESSION_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_PEER_STATS_TWT_FRM_RETRY_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_PEER_STATS_TWT_FRM_RETRY_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_PEER_STATS_TWT_UL_TRIGGER_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_PEER_STATS_TWT_UL_TRIGGER_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_PEER_STATS_TWT_BC_SESSION_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_PEER_STATS_TWT_BC_SESSION_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_PEER_STATS_TWT_PENDING_REPORT_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_PEER_STATS_TWT_PENDING_REPORT_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_PEER_STATS_TWT_FLOW_IDS_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_PEER_STATS_TWT_FLOW_IDS_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_PEER_STATS_ADDBBA_TX_MODE_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PEER_STATS_ADDBBA_TX_MODE_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PEER_STATS_ADDBBA_RESP_MODE_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_PEER_STATS_ADDBBA_RESP_MODE_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+#define WMI_PEER_STATS_MAX_AMSDU_SIZE_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PEER_STATS_MAX_AMSDU_SIZE_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+/* bits 31:16 unused/reserved */
+
+#define WMI_PEER_STATS_TX_FRAME_CTRL_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PEER_STATS_TX_FRAME_CTRL_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PEER_STATS_TX_QOS_CTRL_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_PEER_STATS_TX_QOS_CTRL_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+#define WMI_PEER_STATS_CONSEC_FAIL_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PEER_STATS_CONSEC_FAIL_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PEER_STATS_SUBFRAME_SIZE_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_PEER_STATS_SUBFRAME_SIZE_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+#define WMI_PEER_STATS_TX_FAIL_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PEER_STATS_TX_FAIL_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PEER_STATS_TX_PARTIAL_AID_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_PEER_STATS_TX_PARTIAL_AID_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+#define WMI_PEER_STATS_MAX_NSS_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_PEER_STATS_MAX_NSS_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+/* bits 31:8 unused/reserved */
+
+#define WMI_PEER_STATS_DEL_RESP_TO_HOST_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 1, val)
+#define WMI_PEER_STATS_DEL_RESP_TO_HOST_GET(flag) \
+ WMI_GET_BITS(flag, 0, 1)
+#define WMI_PEER_STATS_DELETE_IN_PROGRESS_SET(flag, val) \
+ WMI_SET_BITS(flag, 1, 1, val)
+#define WMI_PEER_STATS_DELETE_IN_PROGRESS_GET(flag) \
+ WMI_GET_BITS(flag, 1, 1)
+#define WMI_PEER_STATS_MIGRATION_IN_PROGRESS_SET(flag, val) \
+ WMI_SET_BITS(flag, 2, 1, val)
+#define WMI_PEER_STATS_MIGRATION_IN_PROGRESS_GET(flag) \
+ WMI_GET_BITS(flag, 2, 1)
+#define WMI_PEER_STATS_CONN_STATE_SET(flag, val) \
+ WMI_SET_BITS(flag, 3, 4, val)
+#define WMI_PEER_STATS_CONN_STATE_GET(flag) \
+ WMI_GET_BITS(flag, 3, 4)
+#define WMI_PEER_STATS_TX_CHAIN_MASK_160_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_PEER_STATS_TX_CHAIN_MASK_160_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_PEER_STATS_TX_CHAIN_MASK_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_PEER_STATS_TX_CHAIN_MASK_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_PEER_STATS_ASSOC_CHAIN_MASK_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_PEER_STATS_ASSOC_CHAIN_MASK_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_PEER_STATS_QOS_NULL_OVER_WMI_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 1, val)
+#define WMI_PEER_STATS_QOS_NULL_OVER_WMI_GET(flag) \
+ WMI_GET_BITS(flag, 0, 1)
+#define WMI_PEER_STATS_NEW_ASSOC_SET(flag, val) \
+ WMI_SET_BITS(flag, 1, 1, val)
+#define WMI_PEER_STATS_NEW_ASSOC_GET(flag) \
+ WMI_GET_BITS(flag, 1, 1)
+#define WMI_PEER_STATS_TWT_FILT_FLAG_SET(flag, val) \
+ WMI_SET_BITS(flag, 2, 1, val)
+#define WMI_PEER_STATS_TWT_FILT_FLAG_GET(flag) \
+ WMI_GET_BITS(flag, 2, 1)
+#define WMI_PEER_STATS_TWT_REG_FLAG_SET(flag, val) \
+ WMI_SET_BITS(flag, 3, 1, val)
+#define WMI_PEER_STATS_TWT_REG_FLAG_GET(flag) \
+ WMI_GET_BITS(flag, 3, 1)
+#define WMI_PEER_STATS_WMM_UL_TRIG_FLAG_SET(flag, val) \
+ WMI_SET_BITS(flag, 4, 1, val)
+#define WMI_PEER_STATS_WMM_UL_TRIG_FLAG_GET(flag) \
+ WMI_GET_BITS(flag, 4, 1)
+#define WMI_PEER_STATS_ACTIVE_NOT_BA_TID_SET(flag, val) \
+ WMI_SET_BITS(flag, 5, 4, val)
+#define WMI_PEER_STATS_ACTIVE_NOT_BA_TID_GET(flag) \
+ WMI_GET_BITS(flag, 5, 4)
+/* bits 31:10 unused/reserved */
+
+#define WMI_PEER_STATS_NUM_LINKS_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 2, val)
+#define WMI_PEER_STATS_NUM_LINKS_GET(flag) \
+ WMI_GET_BITS(flag, 0, 2)
+#define WMI_PEER_STATS_ML_PEER_ID_SET(flag, val) \
+ WMI_SET_BITS(flag, 2, 12, val)
+#define WMI_PEER_STATS_ML_PEER_ID_GET(flag) \
+ WMI_GET_BITS(flag, 2, 12)
+#define WMI_PEER_STATS_PRI_LINK_ID_SET(flag, val) \
+ WMI_SET_BITS(flag, 14, 3, val)
+#define WMI_PEER_STATS_PRI_LINK_ID_GET(flag) \
+ WMI_GET_BITS(flag, 14, 3)
+#define WMI_PEER_STATS_PRI_CHIP_ID_SET(flag, val) \
+ WMI_SET_BITS(flag, 17, 2, val)
+#define WMI_PEER_STATS_PRI_CHIP_ID_GET(flag) \
+ WMI_GET_BITS(flag, 17, 2)
+#define WMI_PEER_STATS_LINK_INIT_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 19, 3, val)
+#define WMI_PEER_STATS_LINK_INIT_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 19, 3)
+#define WMI_PEER_STATS_NUM_LOCAL_LINKS_SET(flag, val) \
+ WMI_SET_BITS(flag, 22, 2, val)
+#define WMI_PEER_STATS_NUM_LOCAL_LINKS_GET(flag) \
+ WMI_GET_BITS(flag, 22, 2)
+#define WMI_PEER_STATS_CHIPS_BITMAP_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_PEER_STATS_CHIPS_BITMAP_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_VALID_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 1, val)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_VALID_GET(flag) \
+ WMI_GET_BITS(flag, 0, 1)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ACTIVE_SET(flag, val) \
+ WMI_SET_BITS(flag, 1, 1, val)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ACTIVE_GET(flag) \
+ WMI_GET_BITS(flag, 1, 1)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_PRI_SET(flag, val) \
+ WMI_SET_BITS(flag, 2, 1, val)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_PRI_GET(flag) \
+ WMI_GET_BITS(flag, 2, 1)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ASSOC_LINK_SET(flag, val) \
+ WMI_SET_BITS(flag, 3, 1, val)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ASSOC_LINK_GET(flag) \
+ WMI_GET_BITS(flag, 3, 1)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_CHIP_ID_SET(flag, val) \
+ WMI_SET_BITS(flag, 4, 3, val)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_CHIP_ID_GET(flag) \
+ WMI_GET_BITS(flag, 4, 3)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_IEEE_LINK_SET(flag, val) \
+ WMI_SET_BITS(flag, 7, 8, val)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_IEEE_LINK_GET(flag) \
+ WMI_GET_BITS(flag, 7, 8)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_HW_LINK_SET(flag, val) \
+ WMI_SET_BITS(flag, 15, 3, val)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_HW_LINK_GET(flag) \
+ WMI_GET_BITS(flag, 15, 3)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_LOGICAL_LINK_SET(flag, val) \
+ WMI_SET_BITS(flag, 18, 2, val)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_LOGICAL_LINK_GET(flag) \
+ WMI_GET_BITS(flag, 18, 2)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_MASTER_LINK_SET(flag, val) \
+ WMI_SET_BITS(flag, 20, 1, val)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_MASTER_LINK_GET(flag) \
+ WMI_GET_BITS(flag, 20, 1)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ANCHOR_LINK_SET(flag, val) \
+ WMI_SET_BITS(flag, 21, 1, val)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ANCHOR_LINK_GET(flag) \
+ WMI_GET_BITS(flag, 21, 1)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_INIT_SET(flag, val) \
+ WMI_SET_BITS(flag, 22, 1, val)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_INIT_GET(flag) \
+ WMI_GET_BITS(flag, 22, 1)
+/* bits 31:23 unused/reserved */
+
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_PEER_ID_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_PEER_ID_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_VDEV_ID_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_PEER_STATS_ML_PEER_LINK_INFO_VDEV_ID_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+/* bits 31:24 unused/reserved */
+
+#define WMI_PEER_STATS_NSS_160_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_PEER_STATS_NSS_160_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_PEER_STATS_RC_PHYMODE_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_PEER_STATS_RC_PHYMODE_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_PEER_STATS_LEGACY_RATE_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_PEER_STATS_LEGACY_RATE_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+#define WMI_PEER_STATS_MIN_DATA_RATE_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_PEER_STATS_MIN_DATA_RATE_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_PEER_STATS_VHT_MAX_RATE_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 4, val)
+#define WMI_PEER_STATS_VHT_MAX_RATE_GET(flag) \
+ WMI_GET_BITS(flag, 8, 4)
+#define WMI_PEER_STATS_VHT_MAX_STREAMS_SET(flag, val) \
+ WMI_SET_BITS(flag, 12, 4, val)
+#define WMI_PEER_STATS_VHT_MAX_STREAMS_GET(flag) \
+ WMI_GET_BITS(flag, 12, 4)
+#define WMI_PEER_STATS_RC_CHAN_FREQ_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_PEER_STATS_RC_CHAN_FREQ_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+
+typedef struct {
+ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_cfr_stats_struct */
+ A_UINT32 tlv_header;
+ /* blanking_mode:
+ * blanking configuration. Refer to WMI_SCAN_BLANKING_MODE
+ */
+ A_UINT32 blanking_mode;
+ /* is_blanking_enabled:
+ * current blanking status. 0 = disabled, 1 = enabled
+ */
+ A_UINT32 is_blanking_enabled;
+ A_UINT32 gate_2g_enabled; /* 2.4GHZ gate pin state */
+ A_UINT32 gate_5g_enabled; /* 5GHz gate pin state */
+ A_UINT32 gate_6g_enabled; /* 6GHz gate pin state */
+ A_UINT32 blanking_count; /* scan radio blanking count */
+ A_UINT32 blanking_duration; /* scan radio blanking duration in us */
+} wmi_ctrl_path_blanking_stats_struct;
+
typedef struct {
/** TLV tag and len; tag equals
* WMITLV_TAG_STRUC_wmi_ctrl_path_stats_event_fixed_param */
@@ -12803,6 +14337,7 @@
* vdev extension statistics
*/
typedef struct {
+ /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_vdev_extd_stats */
A_UINT32 tlv_header;
/* vdev id */
A_UINT32 vdev_id;
@@ -12823,8 +14358,1178 @@
* Refer to WMI_VDEV_STATS_FLAGS_ defs.
*/
A_UINT32 flags;
+
+ /** opaque_debug_wal_vdev_flags:
+ * This will contain the value from wal_vdev wal vdev flags for vdev state
+ */
+ A_UINT32 opaque_debug_wal_vdev_flags;
+ /** control flags for this vdev */
+ A_UINT32 opaque_debug_vdev_flags;
+ /** vdevid of transmitted AP (mbssid case) */
+ A_UINT32 opaque_debug_vdevid_trans;
+ /** opaque_debug_profile_idx:
+ * the profile index of the connected non-trans ap (mbssid case).
+ * 0 means invalid.
+ */
+ A_UINT32 opaque_debug_profile_idx;
+ /** opaque_debug_profile_num:
+ * the total profile numbers of non-trans aps (mbssid case).
+ * 0 means legacy AP.
+ */
+ A_UINT32 opaque_debug_profile_num;
+ /* Contains the value of multi_vdev_restart status */
+ A_UINT32 opaque_debug_multi_vdev_restart;
+ /* Contains the value of created mac_id from wal_vdev */
+ A_UINT32 opaque_debug_created_mac_id;
+ /* Contains the value of consecutive count of the leaky AP */
+ A_UINT32 opaque_debug_consec_detect_leaky_ap_cnt;
+ /* Contains the value of Vdev manager debug flags */
+ A_UINT32 opaque_debug_vdev_mgr_dbg_flags;
+ /* Contains the value of max vdev pause delay in microseconds */
+ A_UINT32 opaque_debug_max_pause_delay_us;
+ /* opaque_debug_sta_offset:
+ * Contains the value of the offset of vdev TSF with BI (vdev_tsf%BI)
+ * for STA vdev.
+ */
+ A_UINT32 opaque_debug_sta_offset;
+ /* Contains the value of vdev pn sequence receive filter */
+ A_UINT32 opaque_debug_vdev_pn_rx_filter;
+ /* Contains the value of config params */
+ A_UINT32 opaque_debug_traffic_config;
+ /* opaque_debug_he_bss_rts_thld_tu:
+ * Contains Period of time in units for a non-AP STA to reserve the medium.
+ */
+ A_UINT32 opaque_debug_he_bss_rts_thld_tu;
+ /* opaque_debug_rts_threshold:
+ * Contains the value of Request to Send (RTS) Threshold of the packet size.
+ */
+ A_UINT32 opaque_debug_rts_threshold; /* dot11RTSThreshold */
+ /* Contains the value of Tx failure count threshold */
+ A_UINT32 opaque_debug_tx_fail_cnt_thres;
+ /* Contains the value of ratio = HI_WORD/LO_WORD */
+ A_UINT32 opaque_debug_mu_edca_sifs_ratio;
+ /* opaque_debug_kickout_th:
+ * Contains the value of kickout threshold that denotes units of
+ * lost block acks of consecutive tx failure threshold.
+ */
+ A_UINT32 opaque_debug_kickout_th;
+ /* opaque_debug_rate_dd_bmap:
+ * Contains the value of per vap config related to VAP aggregation
+ * of ratectrl drop-down limits.
+ */
+ A_UINT32 opaque_debug_rate_dd_bmap;
+ /* Contains the value of Maximum Transmission Unit frame size */
+ A_UINT32 opaque_debug_mtu_size;
+ /* Contains the value of vdev event bitmap from wal_vdev */
+ A_UINT32 opaque_debug_event_bitmap;
+ /* Contains the value of peer event bitmap from wal_vdev */
+ A_UINT32 opaque_debug_peer_event_bitmap;
+ /* Contains the value of Sched config of vdev allowed time during ATF */
+ A_UINT32 opaque_debug_atf_vdev_allowed_time;
+ /* opaque_debug_atf_vdev_used_unallocated_time:
+ * Contains the value of Sched config of vdev used unallocated time
+ * during ATF.
+ */
+ A_UINT32 opaque_debug_atf_vdev_used_unallocated_time;
+ /* Contains the value of Sched config of vdev unused time during ATF */
+ A_UINT32 opaque_debug_atf_vdev_unused_time;
+ /* Contains the value of Carrier frequency offset last programmed time */
+ A_UINT32 opaque_debug_last_prog_time;
+ /* Contains the value of Carrier frequency offset last receive time */
+ A_UINT32 opaque_debug_last_recv_time;
+ /* Contains the value of Packet count of received frames on the channel */
+ A_UINT32 opaque_debug_rx_pkt_on_channel;
+ /* Contains the value of Target beacon transmission time offset value */
+ A_UINT32 opaque_debug_tbtt_offset;
+ /* Contains the value of tid pause bitmap of the peer from wal_vdev */
+ A_UINT32 opaque_debug_peer_all_tid_pause_bitmap;
+ /* Contains the value of tid block bitmap of the peer from wal_vdev */
+ A_UINT32 opaque_debug_peer_all_tid_block_bitmap;
+ /* Contains the value of tdls peer kickout threshold */
+ A_UINT32 opaque_debug_tdls_peer_kickout_th;
+ /* opaque_debug_num_of_remote_peers_connected:
+ * Contains the value of num_of_remote_peers_connected;
+ * Below field is valid only for AP vap.
+ */
+ A_UINT32 opaque_debug_num_of_remote_peers_connected;
+ /* Contains the value of num of Multi group key support */
+ A_UINT32 opaque_debug_num_group_key_enabled;
+ /* Contains the value of delete all peer command flags */
+ A_UINT32 opaque_debug_delete_all_peer_flags;
+ /* Contains the value of Keepalive ARP sender address time */
+ A_UINT32 opaque_debug_keepalive_arp_sender_ipv4;
+ /* Contains the value of Keepalive ARP Target address time */
+ A_UINT32 opaque_debug_keepalive_arp_target_ipv4;
+ /* Contains the value of Keepalive interval duration time */
+ A_UINT32 opaque_debug_keepalive_interval;
+ /* Contains the value of Keepalive start timer timestamp */
+ A_UINT32 opaque_debug_keepalive_timer_start_timestamp;
+ /* Contains the value of max idle interval and status of STA */
+ A_UINT32 opaque_debug_sta_maxidle_interval;
+ A_UINT32 opaque_debug_sta_maxidle_method;
+ /* Contains the value of Timing synchronization function (TSF) time diff */
+ A_UINT32 opaque_debug_tsf_curr_time_diff;
+ /* opaque_debug_sleep_duration_us:
+ * Contains the value of Time in microsends to detect sleep duration
+ * of the client.
+ */
+ A_UINT32 opaque_debug_sleep_duration_us;
+ /* Contains the value of pause start time and to calculate pause delay */
+ A_UINT32 opaque_debug_pause_start_time_us;
+ A_UINT32 opaque_debug_pause_delay_us;
+ /* Contains the value of number of supported group key */
+ A_UINT32 opaque_debug_num_supported_group_key;
+ /* opaque_debug_avg_data_null_tx_delay:
+ * Contains the value of Average time taken to calculate data frame
+ * tx delay.
+ */
+ A_UINT32 opaque_debug_avg_data_null_tx_delay;
+ /* opaque_debug_avg_rx_leak_window:
+ * Contains the value of Average time taken to calculate data frame
+ * in receive window.
+ */
+ A_UINT32 opaque_debug_avg_rx_leak_window;
+ /* Contains the value of count for number of received deauth frames */
+ A_UINT32 opaque_debug_num_recv_deauth;
+ /* Contains the value of Beacon interval in microseconds */
+ A_UINT32 opaque_debug_bcn_intval_us;
+ /* opaque_debug_fils_period
+ * Contains the value of us, period configured through
+ * WMI_ENABLE_FILS_CMDID.
+ */
+ A_UINT32 opaque_debug_fils_period;
+ /* Contains the value of previous Timing synchronization function (TSF) */
+ A_UINT32 opaque_debug_prev_tsf;
+ /* Contains the value of time taken during client sleep */
+ A_UINT32 opaque_debug_sleep_entry_time;
+ /* Contains the value of Total sleep duration from wal_vdev */
+ A_UINT32 opaque_debug_tot_sleep_dur;
+ /* Contains the value of Vdev pause bitmap from wal_vdev */
+ A_UINT32 opaque_debug_pause_bitmap;
+ /* opaque_debug_last_send_to_host_deauth_tsf:
+ * Contains the value of Last TSF time last_send_to_host_deauth_tsf
+ * from wlan_vdev.
+ */
+ A_UINT32 opaque_debug_last_send_to_host_deauth_tsf;
+ /* Contains the value of debug_short_ssid from wlan_vdev */
+ A_UINT32 opaque_debug_short_ssid;
+ /* Bitfield macro's expansion variables */
+ /* opaque_debug_vdev_amsdu_bitfield:
+ * bit 7:0 - Contains the value of dis_dyn_bw_rts from wlan_vdev,
+ * 15:8 - max_amsdu,
+ * 23:16 - def_amsdu,
+ * 31:24 - he_bss_color
+ */
+ A_UINT32 opaque_debug_vdev_amsdu_bitfield;
+ /* opaque_debug_vdev_ac_failure_configs:
+ * bit 7:0 - Contains the value of dhe_def_pe_duratio from wal_vdev,
+ * 15:8 - minimum_allowed_mcs,
+ * 23:16 - max_11ac_to_leg_rts_fallback_th,
+ * 31:24 - max_11ac_rts_consec_failure_th
+ */
+ A_UINT32 opaque_debug_vdev_ac_failure_configs;
+ /* opaque_debug_vdev_pkt_type_info:
+ * bit 7:0 - Contains the value of input_pkt_type from wal_vdev,
+ * 15:8 - recv_pkt_type,
+ * 23:16 - disable_intra_fwd,
+ * 31:24 - ps_awake
+ */
+ A_UINT32 opaque_debug_vdev_pkt_type_info;
+ /* opaque_debug_vdev_ba_param_bitfield:
+ * bit 7:0 - Contains the value of snr_cal_count from wal_vdev,
+ * 15:8 - amsdu_auto_enable,
+ * 23:16 - param_ba_timeout,
+ * 31:24 - param_ba_buffer_size
+ */
+ A_UINT32 opaque_debug_vdev_ba_param_bitfield;
+ /* opaque_debug_vdev_aggr_bitfield:
+ * bit 7:0 - Contains the value of param_amsdu_support from wal_vdev,
+ * 15:8 - param_ba_retry_max,
+ * 23:16 - tx_aggr_size,
+ * 31:24 - rx_aggr_size
+ */
+ A_UINT32 opaque_debug_vdev_aggr_bitfield;
+ /* opaque_debug_vdev_event_delivery:
+ * bit 7:0 - Contains the value of tqm_bypass_enabled from wal_vdev,
+ * 15:8 - wmmac_timer_vote_cnt,
+ * 23:16 - peer_event_delivery_in_progress,
+ * 31:24 - vdev_event_delivery_in_progress
+ */
+ A_UINT32 opaque_debug_vdev_event_delivery;
+ /* opaque_debug_vdev_cap_slot_bitfield:
+ * bit 7:0 - Contains the value of bcn_max_slot from wal_vdev,
+ * 15:8 - bcn_curr_slot,
+ * 23:16 - mgmt_tx_power,
+ * 31:24 - mbssid_capable_association
+ */
+ A_UINT32 opaque_debug_vdev_cap_slot_bitfield;
+ /* opaque_debug_vdev_bcn_configs:
+ * bit 7:0 - Contains the value of mbssid_txbssid_association from
+ * wal_vdev,
+ * 15:8 - consec_beacon_skip,
+ * 23:16 - consec_beacon_skip_cnt,
+ * 31:24 - max_consec_beacon_skip
+ */
+ A_UINT32 opaque_debug_vdev_bcn_configs;
+ /* Contains the value of opaque_debug_vdev_cmd_info */
+ A_UINT32 opaque_debug_vdev_cmd_info;
+ /* opaque_debug_vdev_mac_configs:
+ * bit 7:0 - Contains the value of pause_cnt from wlan_vdev,
+ * 15:8 - e_mac_id,
+ * 23:16 - is_transmit_bssid,
+ * 31:24 - rts_rc_flag
+ */
+ A_UINT32 opaque_debug_vdev_mac_configs;
+ /* opaque_debug_vdev_mode_configs:
+ * bit 7:0 - Contains the value of ic_opmode from wlan_vdev,
+ * 15:8 - ic_subopmode,
+ * 23:16 - ic_curmode,
+ * 31:24 - vdev_up_cmd_cnt
+ */
+ A_UINT32 opaque_debug_vdev_mode_configs;
+ /* opaque_debug_vdev_keepalive_bitfields:
+ * bit 7:0 - keepalive_method
+ * 15:8 - keepalive_prohibit_data_mgmt
+ * 23:16 - resp_type
+ * 31:24 - ap_detect_out_of_sync_sleeping_sta_time_secs
+ */
+ A_UINT32 opaque_debug_vdev_keepalive_bitfields;
+ /* opaque_debug_vdev_bcn_drift_info:
+ * bit 7:0 - bcn_drift_cnt
+ * 15:8 - bcn_drift_calibration
+ * 23:16 - rts_cts_default
+ * 31:24 - vdev_down_cmd_cnt
+ */
+ A_UINT32 opaque_debug_vdev_bcn_drift_info;
+ /* opaque_debug_vdev_arp_configs:
+ * bit 7:0 - Contains the value of tbtt_link_type from wlan_vdev,
+ * 15:8 - is_arp_in_air,
+ * 23:16 - is_ns_in_air,
+ * 31:24 - num_of_keepalive_attempts
+ */
+ A_UINT32 opaque_debug_vdev_arp_configs;
+ /* opaque_debug_vdev_streams_configs:
+ * bit 7:0 - n_beacons_since_last_rssi_report
+ * 15:8 - num_ofld_peer_alloced
+ * 23:16 - preferred_tx_streams
+ * 31:24 - preferred_rx_streams
+ */
+ A_UINT32 opaque_debug_vdev_streams_configs;
+ /* opaque_debug_vdev_chains_configs:
+ * bit 7:0 - Contains the value of preferred_tx_streams_160 from
+ * wlan_vdev,
+ * 15:8 - preferred_rx_streams_160,
+ * 23:16 - tx_chains_num_11b,
+ * 31:24 - tx_chains_num_11ag
+ */
+ A_UINT32 opaque_debug_vdev_chains_configs;
+ /* opaque_debug_vdev_power_cap_configs:
+ * bit 7:0 - Contains the value of supp_op_cls_ie_len from wlan_vdev,
+ * 15:8 - rm_en_cap_ie_len,
+ * 23:16 - power_cap_ie_len,
+ * 31:24 - supp_channel_ie_len
+ */
+ A_UINT32 opaque_debug_vdev_power_cap_configs;
+ /* opaque_debug_vdev_wmm_mbo_configs:
+ * bit 7:0 - Contains the value of wmm_tspec_ie_len from wlan_vdev,
+ * 15:8 - ccx_version_ie_len,
+ * 23:16 - extn_dh_ie_len,
+ * 31:24 - mbo_ie_len
+ */
+ A_UINT32 opaque_debug_vdev_wmm_mbo_configs;
+ /* opaque_debug_vdev_remote_configs:
+ * bit 7:0 - Contains the value of rsnxe_ie_len from wlan_vdev,
+ * 15:8 - remote_peer_cnt
+ * 23:16 - p2p_cli_pause_type
+ * 31:24 - mu_edca_update_count
+ */
+ A_UINT32 opaque_debug_vdev_remote_configs;
+ /* opaque_debug_vdev_stats_id_configs:
+ * bit 7:0 - vdev_stats_id
+ * 15:8 - vdev_stats_id_valid
+ * 23:16 - preferred_tx_streams_320
+ * 31:24 - preferred_rx_streams_320
+ */
+ A_UINT32 opaque_debug_vdev_stats_id_configs;
+ /* opaque_debug_vdev_assoc_peer_configs:
+ * bit 7:0 - unused / reserved
+ * 15:8 - group_cipher
+ * 31:16 - assoc_id
+ */
+ A_UINT32 opaque_debug_vdev_assoc_peer_configs;
+ /* opaque_debug_vdev_mhz_fils_configs:
+ * bit 15:0 - Contains the value of bss_channel_mhz from wal_vdev,
+ * 31:16 - config_fils_period
+ */
+ A_UINT32 opaque_debug_vdev_mhz_fils_configs;
+ /* opaque_debug_vdev_fils_period:
+ * bit 15:0 - Contains the value of calc_fils_period from wal_vdev,
+ * 31:16 - ic_txseqs_cmn
+ */
+ A_UINT32 opaque_debug_vdev_fils_period;
+ /* opaque_debug_vdev_inactive_time:
+ * bit 15:0 - Contains the value of
+ * ap_keepalive_min_idle_inactive_time_secs from wlan_vdev,
+ * 31:16 - ap_keepalive_max_idle_inactive_time_secs
+ */
+ A_UINT32 opaque_debug_vdev_inactive_time;
+ /* opaque_debug_vdev_chain_mask_configs:
+ * bit 15:0 - Contains the value of
+ * ap_keepalive_max_unresponsive_time_secs from wlan_vdev,
+ * 31:16 - chain_mask
+ */
+ A_UINT32 opaque_debug_vdev_chain_mask_configs;
+ /* opaque_debug_vdev_ie_len_configs:
+ * bit 15:0 - num_mcast_filters
+ * 31:16 - ext_cap_ie_len
+ */
+ A_UINT32 opaque_debug_vdev_ie_len_configs;
+ /* opaque_debug_vdev_fils_configs:
+ * bit 15:0 - Contains the value of fils_channel_guard_time from wlan_vdev,
+ * 31:16 - fd_tmpl_len
+ */
+ A_UINT32 opaque_debug_vdev_fils_configs;
+ /* opaque_debug_vdev_chan_configs:
+ * bit 15:0 - Contains the value of common_rsn_caps from wlan_vdev,
+ * 31:16 - off_ch_active_dwell_time
+ */
+ A_UINT32 opaque_debug_vdev_chan_configs;
+ /* opaque_debug_vdev_dwell_configs:
+ * bit 15:0 - Contains the value of off_ch_passive_dwell_time from
+ * wlan_vdev,
+ * 31:16 - current_pause_request_id
+ */
+ A_UINT32 opaque_debug_vdev_dwell_configs;
+ /* opaque_debug_vdev_wmi_configs:
+ * bit 0 - Contains the value of hide_ssid_enable from wlan_vdev,
+ * 1 - b_none_protocol_paused
+ * 2 - dpd_cal_state
+ * 4 - req_bcn_q_unpause
+ * 5 - bt_coex_enable_cts2s
+ * 6 - dpd_delay_n_beacon
+ * 8 - b_need_check_first_beacon
+ * 9 - ap_peer_keepalive_max_idle_time_reached
+ * 10 - leakyap_cts2s_enable
+ * 11 - stasapscc_in_mcc
+ * 12 - stasapscc_in_mcc_cts2s_enable
+ * 13 - is_vdev_stopping
+ * 14 - is_wmi_vdev_down
+ * 15 - is_vdev_down_pending
+ * 16 - vdev_delete_in_progress
+ * 17 - cac_enabled
+ * 18 - is_quaterrate
+ * 19 - is_halfrate
+ * 20 - stop_resp_event_blocked
+ * 21 - use_enhanced_mcast_filter
+ * 22 - is_start_pending_on_asm
+ * 23 - no_null_to_ap_for_roaming
+ * 24 - is_loopback_cal_pending
+ * 25 - vdev_delete_acked
+ * 26 - bc_proberesp_enable
+ * 27 - is_wmm_param
+ * 28 - is_connect_in_progress
+ * 29 - is_mu_edca_param
+ * 30 - send_del_resp_tohost
+ * 31 - is_restart_different_ch
+ */
+ A_UINT32 opaque_debug_vdev_wmi_configs;
+ /* opaque_debug_vdev_hu_mu_configs:
+ * bit 0 - Contains the value of proto_ps_status from wlan_vdev,
+ * 1 - smps_intolerant
+ * 2 - is_offload_registered_for_connection
+ * 3 - is_bss_beacon_offload_registered
+ * 4 - is_prob_resp_offload_registered
+ * 5 - is_ibss_beacon_offload_registered
+ * 6 - is_keepalive_attempts_exhausted
+ * 7 - is_bcn_tx_ie_changed_log
+ * 8 - he_su_bfee
+ * 9 - he_su_bfer
+ * 10 - he_mu_bfee
+ * 11 - he_mu_bfer
+ * 12 - he_dl_ofdma
+ * 13 - he_ul_ofdma
+ * 14 - he_ul_mumimo
+ * 15 - ul_mu_resp
+ * 23:16 - alt_rssi_non_srg
+ * 31:24 - alt_rssi_srg
+ */
+ A_UINT32 opaque_debug_vdev_hu_mu_configs;
+ /* opaque_debug_vdev_sm_chan_configs:
+ * bit 0 - Contains the value of he_bss_color_en from wlan_vdev,
+ * 1 - he_txbf_ofdma
+ * 2 - non_srg_enable
+ * 3 - srg_enable
+ * 4 - srp_enable
+ * 5 - sr_initialized
+ * 6 - sr_rings_initialized
+ * 10:7 - per_ac_obss_pd_enable
+ * 11 - ifup
+ * 12 - ifactive
+ * 13 - ifpaused
+ * 14 - ifoutofsync
+ * 15 - is_free
+ * 16 - is_nawds
+ * 17 - hw_flag
+ * 18 - ch_req_flag
+ * 20 - restart_resp
+ * 21 - first_beacon_recv_wait
+ * 22 - erpenabled
+ * 23 - start_responded
+ * 24 - bcn_sync_crit_req_act
+ * 25 - recal_notif_registered
+ * 26 - bcn_tx_paused
+ * 27 - he_bss_color_en_bypass
+ * 28 - default_ba_mode
+ * 29 - ba_256_bitmap_enable
+ * 30 - ba_256_bitmap_tx_disable
+ * 31 - is_multi_group_key_enabled
+ */
+ A_UINT32 opaque_debug_vdev_sm_chan_configs;
+ /*
+ * The following 4 opaque_debug variables are provided purely for
+ * debugging by technicians who have outside knowledge of what kind of
+ * values the target has placed into these fields.
+ * The host must not interpret the values of these fields, since the
+ * meaning of the values provided in these fields may change without
+ * regard for backwards compatibility or interoperability.
+ */
+ A_UINT32 opaque_debug_field_1;
+ A_UINT32 opaque_debug_field_2;
+ A_UINT32 opaque_debug_field_3;
+ A_UINT32 opaque_debug_field_4;
} wmi_vdev_extd_stats;
+
+#define WMI_VDEV_STATS_DIS_DYN_BW_RTS_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_DIS_DYN_BW_RTS_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_MAX_AMSDU_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_MAX_AMSDU_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_DEF_AMSDU_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_DEF_AMSDU_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_HW_BSS_COLOR_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_HW_BSS_COLOR_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_HE_DEF_PE_DURATION_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_HE_DEF_PE_DURATION_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_MINIMUM_ALLOWED_MCS_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_MINIMUM_ALLOWED_MCS_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_MAX_11AC_TO_LEG_RTS_FALLBACK_TH_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_MAX_11AC_TO_LEG_RTS_FALLBACK_TH_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_MAX_11AC_RTS_CONSEC_FAILURE_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_MAX_11AC_RTS_CONSEC_FAILURE_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_INPUT_PKT_TYPE_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_INPUT_PKT_TYPE_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_RECV_PKT_TYPE_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_RECV_PKT_TYPE_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_DISABLE_INTRA_FWD_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_DISABLE_INTRA_FWD_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_PS_AWAKE_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_PS_AWAKE_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_SNR_CAL_COUNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_SNR_CAL_COUNT_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_AMSDU_AUTO_ENABLE_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_AMSDU_AUTO_ENABLE_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_PARAM_BA_TIMEOUT_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_PARAM_BA_TIMEOUT_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_PARAM_BA_BUFFER_SIZE_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_PARAM_BA_BUFFER_SIZE_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_PARAM_AMSDU_SUPPORT_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_PARAM_AMSDU_SUPPORT_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_PARAM_BA_RETRY_MAX_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_PARAM_BA_RETRY_MAX_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_TX_AGGR_SIZE_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_TX_AGGR_SIZE_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_RX_AGGR_SIZE_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_RX_AGGR_SIZE_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_TQM_BYPASS_ENABLED_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_TQM_BYPASS_ENABLED_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_WMMAC_TIMER_VOTE_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_WMMAC_TIMER_VOTE_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_PEER_EVENT_DELIVERY_IN_PROGRESS_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_PEER_EVENT_DELIVERY_IN_PROGRESS_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_VDEV_EVENT_DELIVERY_IN_PROGRESS_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_VDEV_EVENT_DELIVERY_IN_PROGRESS_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_BCN_MAX_SLOT_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_BCN_MAX_SLOT_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_BCN_CURR_SLOT_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_BCN_CURR_SLOT_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_MGMT_TX_POWER_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_MGMT_TX_POWER_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_MBSSID_CAPABLE_ASSOCIATION_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_MBSSID_CAPABLE_ASSOCIATION_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_MBSSID_TXBSSID_ASSOCIATION_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_MBSSID_TXBSSID_ASSOCIATION_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_CONSEC_BEACON_SKIP_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_CONSEC_BEACON_SKIP_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_CONSEC_BEACON_SKIP_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_CONSEC_BEACON_SKIP_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_MAX_CONSEC_BEACON_SKIP_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_MAX_CONSEC_BEACON_SKIP_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_BCN_DRIFT_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_BCN_DRIFT_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_BCN_DRIFT_CALIBRATION_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_BCN_DRIFT_CALIBRATION_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_VDEV_DOWN_CMD_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_VDEV_DOWN_CMD_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_RTS_CTS_DEFAULT_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_RTS_CTS_DEFAULT_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_PAUSE_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_PAUSE_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_E_MAC_ID_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_E_MAC_ID_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_IS_TRANSMIT_BSSID_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_IS_TRANSMIT_BSSID_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_RTS_RC_FLAG_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_RTS_RC_FLAG_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_IC_OPMODE_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_IC_OPMODE_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_IC_SUBOPMODE_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_IC_SUBOPMODE_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_IC_CURMODE_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_IC_CURMODE_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_VDEV_UP_CMD_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_VDEV_UP_CMD_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_KEEPALIVE_METHOD_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_KEEPALIVE_METHOD_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_KEEPALIVE_PROHIBIT_DATA_MGMT_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_KEEPALIVE_PROHIBIT_DATA_MGMT_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_RESP_TYPE_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_RESP_TYPE_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_BCN_DRIFT_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_BCN_DRIFT_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_BCN_DRIFT_CALIBRATION_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_BCN_DRIFT_CALIBRATION_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_VDEV_DOWN_CMD_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_VDEV_DOWN_CMD_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_RTS_CTS_DEFAULT_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_RTS_CTS_DEFAULT_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_TBTT_LINK_TYPE_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_TBTT_LINK_TYPE_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_IS_ARP_IN_AIR_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_IS_ARP_IN_AIR_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_IS_NS_IN_AIR_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_IS_NS_IN_AIR_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_NUM_OF_KEEPALIVE_ATTEMPTS_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_NUM_OF_KEEPALIVE_ATTEMPTS_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_N_BEACONS_SINCE_LAST_RSSI_REPORT_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_N_BEACONS_SINCE_LAST_RSSI_REPORT_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_NUM_OFLD_PEER_ALLOCED_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_NUM_OFLD_PEER_ALLOCED_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_160_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_160_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_160_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_160_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_TX_CHAINS_NUM_11B_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_TX_CHAINS_NUM_11B_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_TX_CHAINS_NUM_11AG_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_TX_CHAINS_NUM_11AG_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_SUPP_OP_CLS_IE_LEN_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_SUPP_OP_CLS_IE_LEN_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_RM_EN_CAP_IE_LEN_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_RM_EN_CAP_IE_LEN_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_POWER_CAP_IE_LEN_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_POWER_CAP_IE_LEN_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_SUPP_CHANNEL_IE_LEN_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_SUPP_CHANNEL_IE_LEN_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_WMM_TSPEC_IE_LEN_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_WMM_TSPEC_IE_LEN_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_CCX_VERSION_IE_LEN_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_CCX_VERSION_IE_LEN_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_EXTN_DH_IE_LEN_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_EXTN_DH_IE_LEN_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_MBO_IE_LEN_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_MBO_IE_LEN_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_RSNXE_IE_LEN_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_RSNXE_IE_LEN_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_REMOTE_PEER_CNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_REMOTE_PEER_CNT_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_P2P_CLI_PAUSE_TYPE_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_P2P_CLI_PAUSE_TYPE_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_MU_EDCA_UPDATE_COUNT_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_MU_EDCA_UPDATE_COUNT_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_ID_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 8, val)
+#define WMI_VDEV_STATS_ID_GET(flag) \
+ WMI_GET_BITS(flag, 0, 8)
+#define WMI_VDEV_STATS_ID_VALID_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_ID_VALID_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_320_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_320_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_320_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_320_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+/* bits 7:0 unused / reserved */
+#define WMI_VDEV_STATS_GROUP_CIPHER_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 8, val)
+#define WMI_VDEV_STATS_GROUP_CIPHER_GET(flag) \
+ WMI_GET_BITS(flag, 8, 8)
+#define WMI_VDEV_STATS_ASSOC_ID_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_VDEV_STATS_ASSOC_ID_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+#define WMI_VDEV_STATS_BSS_CHANNEL_MHZ_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_VDEV_STATS_BSS_CHANNEL_MHZ_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_VDEV_STATS_CONFIG_FILS_PERIOD_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_VDEV_STATS_CONFIG_FILS_PERIOD_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+#define WMI_VDEV_STATS_CALC_FILS_PERIOD_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_VDEV_STATS_CALC_FILS_PERIOD_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_VDEV_STATS_IC_TXSEQS_CMN_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_VDEV_STATS_IC_TXSEQS_CMN_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+#define WMI_VDEV_STATS_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_VDEV_STATS_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_VDEV_STATS_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_VDEV_STATS_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+#define WMI_VDEV_STATS_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_VDEV_STATS_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_VDEV_STATS_CHAIN_MASK_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_VDEV_STATS_CHAIN_MASK_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+#define WMI_VDEV_STATS_NUM_MCAST_FILTERS_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_VDEV_STATS_NUM_MCAST_FILTERS_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_VDEV_STATS_EXT_CAP_IE_LEN_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_VDEV_STATS_EXT_CAP_IE_LEN_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+#define WMI_VDEV_STATS_FILS_CHANNEL_GUARD_TIME_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_VDEV_STATS_FILS_CHANNEL_GUARD_TIME_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_VDEV_STATS_FD_TMPL_LEN_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_VDEV_STATS_FD_TMPL_LEN_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+#define WMI_VDEV_STATS_COMMON_RSN_CAPS_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_VDEV_STATS_COMMON_RSN_CAPS_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_VDEV_STATS_OFF_CH_ACTIVE_DWELL_TIME_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_VDEV_STATS_OFF_CH_ACTIVE_DWELL_TIME_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+#define WMI_VDEV_STATS_OFF_CH_PASSIVE_DWELL_TIME_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 16, val)
+#define WMI_VDEV_STATS_OFF_CH_PASSIVE_DWELL_TIME_GET(flag) \
+ WMI_GET_BITS(flag, 0, 16)
+#define WMI_VDEV_STATS_CURRENT_PAUSE_REQUEST_ID_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 16, val)
+#define WMI_VDEV_STATS_CURRENT_PAUSE_REQUEST_ID_GET(flag) \
+ WMI_GET_BITS(flag, 16, 16)
+
+#define WMI_VDEV_STATS_HIDE_SSID_ENABLE_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 1, val)
+#define WMI_VDEV_STATS_HIDE_SSID_ENABLE_GET(flag) \
+ WMI_GET_BITS(flag, 0, 1)
+#define WMI_VDEV_STATS_B_NONE_PROTOCOL_PAUSED_SET(flag, val) \
+ WMI_SET_BITS(flag, 1, 1, val)
+#define WMI_VDEV_STATS_B_NONE_PROTOCOL_PAUSED_GET(flag) \
+ WMI_GET_BITS(flag, 1, 1)
+#define WMI_VDEV_STATS_DPD_CAL_STATE_SET(flag, val) \
+ WMI_SET_BITS(flag, 2, 2, val)
+#define WMI_VDEV_STATS_DPD_CAL_STATE_GET(flag) \
+ WMI_GET_BITS(flag, 2, 2)
+#define WMI_VDEV_STATS_REQ_BCN_Q_UNPAUSE_SET(flag, val) \
+ WMI_SET_BITS(flag, 4, 1, val)
+#define WMI_VDEV_STATS_REQ_BCN_Q_UNPAUSE_GET(flag) \
+ WMI_GET_BITS(flag, 4, 1)
+#define WMI_VDEV_STATS_BT_COEX_ENABLE_CTS2S_SET(flag, val) \
+ WMI_SET_BITS(flag, 5, 1, val)
+#define WMI_VDEV_STATS_BT_COEX_ENABLE_CTS2S_GET(flag) \
+ WMI_GET_BITS(flag, 5, 1)
+#define WMI_VDEV_STATS_DPD_DELAY_N_BEACON_SET(flag, val) \
+ WMI_SET_BITS(flag, 6, 2, val)
+#define WMI_VDEV_STATS_DPD_DELAY_N_BEACON_GET(flag) \
+ WMI_GET_BITS(flag, 6, 2)
+#define WMI_VDEV_STATS_B_NEED_CHECK_FIRST_BEACON_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 1, val)
+#define WMI_VDEV_STATS_B_NEED_CHECK_FIRST_BEACON_GET(flag) \
+ WMI_GET_BITS(flag, 8, 1)
+#define WMI_VDEV_STATS_AP_PEER_KEEPALIVE_MAX_IDLE_TIME_REACHED_SET(flag, val) \
+ WMI_SET_BITS(flag, 9, 1, val)
+#define WMI_VDEV_STATS_AP_PEER_KEEPALIVE_MAX_IDLE_TIME_REACHED_GET(flag) \
+ WMI_GET_BITS(flag, 9, 1)
+#define WMI_VDEV_STATS_LEAKYAP_CTS2S_ENABLE_SET(flag, val) \
+ WMI_SET_BITS(flag, 10, 1, val)
+#define WMI_VDEV_STATS_LEAKYAP_CTS2S_ENABLE_GET(flag) \
+ WMI_GET_BITS(flag, 10, 1)
+#define WMI_VDEV_STATS_STASAPSCC_IN_MCC_SET(flag, val) \
+ WMI_SET_BITS(flag, 11, 1, val)
+#define WMI_VDEV_STATS_STASAPSCC_IN_MCC_GET(flag) \
+ WMI_GET_BITS(flag, 11, 1)
+#define WMI_VDEV_STATS_STASAPSCC_IN_MCC_CTS2S_ENABLE_SET(flag, val) \
+ WMI_SET_BITS(flag, 12, 1, val)
+#define WMI_VDEV_STATS_STASAPSCC_IN_MCC_CTS2S_ENABLE_GET(flag) \
+ WMI_GET_BITS(flag, 12, 1)
+#define WMI_VDEV_STATS_IS_VDEV_STOPPING_SET(flag, val) \
+ WMI_SET_BITS(flag, 13, 1, val)
+#define WMI_VDEV_STATS_IS_VDEV_STOPPING_GET(flag) \
+ WMI_GET_BITS(flag, 13, 1)
+#define WMI_VDEV_STATS_IS_WMI_VDEV_DOWN_SET(flag, val) \
+ WMI_SET_BITS(flag, 14, 1, val)
+#define WMI_VDEV_STATS_IS_WMI_VDEV_DOWN_GET(flag) \
+ WMI_GET_BITS(flag, 14, 1)
+#define WMI_VDEV_STATS_IS_VDEV_DOWN_PENDING_SET(flag, val) \
+ WMI_SET_BITS(flag, 15, 1, val)
+#define WMI_VDEV_STATS_IS_VDEV_DOWN_PENDING_GET(flag) \
+ WMI_GET_BITS(flag, 15, 1)
+#define WMI_VDEV_STATS_VDEV_DELETE_IN_PROGRESS_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 1, val)
+#define WMI_VDEV_STATS_VDEV_DELETE_IN_PROGRESS_GET(flag) \
+ WMI_GET_BITS(flag, 16, 1)
+#define WMI_VDEV_STATS_CAC_ENABLED_SET(flag, val) \
+ WMI_SET_BITS(flag, 17, 1, val)
+#define WMI_VDEV_STATS_CAC_ENABLED_GET(flag) \
+ WMI_GET_BITS(flag, 17, 1)
+#define WMI_VDEV_STATS_IS_QUATERRATE_SET(flag, val) \
+ WMI_SET_BITS(flag, 18, 1, val)
+#define WMI_VDEV_STATS_IS_QUATERRATE_GET(flag) \
+ WMI_GET_BITS(flag, 18, 1)
+#define WMI_VDEV_STATS_IS_HALFRATE_SET(flag, val) \
+ WMI_SET_BITS(flag, 19, 1, val)
+#define WMI_VDEV_STATS_IS_HALFRATE_GET(flag) \
+ WMI_GET_BITS(flag, 19, 1)
+#define WMI_VDEV_STATS_STOP_RESP_EVENT_BLOCKED_SET(flag, val) \
+ WMI_SET_BITS(flag, 20, 1, val)
+#define WMI_VDEV_STATS_STOP_RESP_EVENT_BLOCKED_GET(flag) \
+ WMI_GET_BITS(flag, 20, 1)
+#define WMI_VDEV_STATS_USE_ENHANCED_MCAST_FILTER_SET(flag, val) \
+ WMI_SET_BITS(flag, 21, 1, val)
+#define WMI_VDEV_STATS_USE_ENHANCED_MCAST_FILTER_GET(flag) \
+ WMI_GET_BITS(flag, 21, 1)
+#define WMI_VDEV_STATS_IS_START_PENDING_ON_ASM_SET(flag, val) \
+ WMI_SET_BITS(flag, 22, 1, val)
+#define WMI_VDEV_STATS_IS_START_PENDING_ON_ASM_GET(flag) \
+ WMI_GET_BITS(flag, 22, 1)
+#define WMI_VDEV_STATS_NO_NULL_TO_AP_FOR_ROAMING_SET(flag, val) \
+ WMI_SET_BITS(flag, 23, 1, val)
+#define WMI_VDEV_STATS_NO_NULL_TO_AP_FOR_ROAMING_GET(flag) \
+ WMI_GET_BITS(flag, 23, 1)
+#define WMI_VDEV_STATS_IS_LOOPBACK_CAL_PENDING_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 1, val)
+#define WMI_VDEV_STATS_IS_LOOPBACK_CAL_PENDING_GET(flag) \
+ WMI_GET_BITS(flag, 24, 1)
+#define WMI_VDEV_STATS_VDEV_DELETE_ACKED_SET(flag, val) \
+ WMI_SET_BITS(flag, 25, 1, val)
+#define WMI_VDEV_STATS_VDEV_DELETE_ACKED_GET(flag) \
+ WMI_GET_BITS(flag, 25, 1)
+#define WMI_VDEV_STATS_BC_PROBERESP_ENABLE_SET(flag, val) \
+ WMI_SET_BITS(flag, 26, 1, val)
+#define WMI_VDEV_STATS_BC_PROBERESP_ENABLE_GET(flag) \
+ WMI_GET_BITS(flag, 26, 1)
+#define WMI_VDEV_STATS_IS_WMM_PARAM_SET_SET(flag, val) \
+ WMI_SET_BITS(flag, 27, 1, val)
+#define WMI_VDEV_STATS_IS_WMM_PARAM_SET_GET(flag) \
+ WMI_GET_BITS(flag, 27, 1)
+#define WMI_VDEV_STATS_IS_CONNECT_IN_PROGRESS_SET(flag, val) \
+ WMI_SET_BITS(flag, 28, 1, val)
+#define WMI_VDEV_STATS_IS_CONNECT_IN_PROGRESS_GET(flag) \
+ WMI_GET_BITS(flag, 28, 1)
+#define WMI_VDEV_STATS_IS_MU_EDCA_PARAM_SET_SET(flag, val) \
+ WMI_SET_BITS(flag, 29, 1, val)
+#define WMI_VDEV_STATS_IS_MU_EDCA_PARAM_SET_GET(flag) \
+ WMI_GET_BITS(flag, 29, 1)
+#define WMI_VDEV_STATS_SEND_DEL_RESP_TOHOST_SET(flag, val) \
+ WMI_SET_BITS(flag, 30, 1, val)
+#define WMI_VDEV_STATS_SEND_DEL_RESP_TOHOST_GET(flag) \
+ WMI_GET_BITS(flag, 30, 1)
+#define WMI_VDEV_STATS_IS_RESTART_DIFFERENT_CH_SET(flag, val) \
+ WMI_SET_BITS(flag, 31, 1, val)
+#define WMI_VDEV_STATS_IS_RESTART_DIFFERENT_CH_GET(flag) \
+ WMI_GET_BITS(flag, 31, 1)
+
+#define WMI_VDEV_STATS_PROTO_PS_STATUS_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 1, val)
+#define WMI_VDEV_STATS_PROTO_PS_STATUS_GET(flag) \
+ WMI_GET_BITS(flag, 0, 1)
+#define WMI_VDEV_STATS_SMPS_INTOLERANT_SET(flag, val) \
+ WMI_SET_BITS(flag, 1, 1, val)
+#define WMI_VDEV_STATS_SMPS_INTOLERANT_GET(flag) \
+ WMI_GET_BITS(flag, 1, 1)
+#define WMI_VDEV_STATS_IS_OFFLOAD_REGISTERED_FOR_CONNECTION_SET(flag, val) \
+ WMI_SET_BITS(flag, 2, 1, val)
+#define WMI_VDEV_STATS_IS_OFFLOAD_REGISTERED_FOR_CONNECTION_GET(flag) \
+ WMI_GET_BITS(flag, 2, 1)
+#define WMI_VDEV_STATS_IS_BSS_BEACON_OFFLOAD_REGISTERED_SET(flag, val) \
+ WMI_SET_BITS(flag, 3, 1, val)
+#define WMI_VDEV_STATS_IS_BSS_BEACON_OFFLOAD_REGISTERED_GET(flag) \
+ WMI_GET_BITS(flag, 3, 1)
+#define WMI_VDEV_STATS_IS_PROB_RESP_OFFLOAD_REGISTERED_SET(flag, val) \
+ WMI_SET_BITS(flag, 4, 1, val)
+#define WMI_VDEV_STATS_IS_PROB_RESP_OFFLOAD_REGISTERED_GET(flag) \
+ WMI_GET_BITS(flag, 4, 1)
+#define WMI_VDEV_STATS_IS_IBSS_BEACON_OFFLOAD_REGISTERED_SET(flag, val) \
+ WMI_SET_BITS(flag, 5, 1, val)
+#define WMI_VDEV_STATS_IS_IBSS_BEACON_OFFLOAD_REGISTERED_GET(flag) \
+ WMI_GET_BITS(flag, 5, 1)
+#define WMI_VDEV_STATS_IS_KEEPALIVE_ATTEMPTS_EXHAUSTED_SET(flag, val) \
+ WMI_SET_BITS(flag, 6, 1, val)
+#define WMI_VDEV_STATS_IS_KEEPALIVE_ATTEMPTS_EXHAUSTED_GET(flag) \
+ WMI_GET_BITS(flag, 6, 1)
+#define WMI_VDEV_STATS_IS_BCN_TX_IE_CHANGED_LOG_SET(flag, val) \
+ WMI_SET_BITS(flag, 7, 1, val)
+#define WMI_VDEV_STATS_IS_BCN_TX_IE_CHANGED_LOG_GET(flag) \
+ WMI_GET_BITS(flag, 7, 1)
+#define WMI_VDEV_STATS_HE_SU_BFEE_SET(flag, val) \
+ WMI_SET_BITS(flag, 8, 1, val)
+#define WMI_VDEV_STATS_HE_SU_BFEE_GET(flag) \
+ WMI_GET_BITS(flag, 8, 1)
+#define WMI_VDEV_STATS_HE_SU_BFER_SET(flag, val) \
+ WMI_SET_BITS(flag, 9, 1, val)
+#define WMI_VDEV_STATS_HE_SU_BFER_GET(flag) \
+ WMI_GET_BITS(flag, 9, 1)
+#define WMI_VDEV_STATS_HE_MU_BFEE_SET(flag, val) \
+ WMI_SET_BITS(flag, 10, 1, val)
+#define WMI_VDEV_STATS_HE_MU_BFEE_GET(flag) \
+ WMI_GET_BITS(flag, 10, 1)
+#define WMI_VDEV_STATS_HE_MU_BFER_SET(flag, val) \
+ WMI_SET_BITS(flag, 11, 1, val)
+#define WMI_VDEV_STATS_HE_MU_BFER_GET(flag) \
+ WMI_GET_BITS(flag, 11, 1)
+#define WMI_VDEV_STATS_HE_DL_OFDMA_SET(flag, val) \
+ WMI_SET_BITS(flag, 12, 1, val)
+#define WMI_VDEV_STATS_HE_DL_OFDMA_GET(flag) \
+ WMI_GET_BITS(flag, 12, 1)
+#define WMI_VDEV_STATS_HE_UL_OFDMA_SET(flag, val) \
+ WMI_SET_BITS(flag, 13, 1, val)
+#define WMI_VDEV_STATS_HE_UL_OFDMA_GET(flag) \
+ WMI_GET_BITS(flag, 13, 1)
+#define WMI_VDEV_STATS_HE_UL_MUMIMO_SET(flag, val) \
+ WMI_SET_BITS(flag, 14, 1, val)
+#define WMI_VDEV_STATS_HE_UL_MUMIMO_GET(flag) \
+ WMI_GET_BITS(flag, 14, 1)
+#define WMI_VDEV_STATS_UL_MU_RESP_SET(flag, val) \
+ WMI_SET_BITS(flag, 15, 1, val)
+#define WMI_VDEV_STATS_UL_MU_RESP_GET(flag) \
+ WMI_GET_BITS(flag, 15, 1)
+#define WMI_VDEV_STATS_ALT_RSSI_NON_SRG_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 8, val)
+#define WMI_VDEV_STATS_ALT_RSSI_NON_SRG_GET(flag) \
+ WMI_GET_BITS(flag, 16, 8)
+#define WMI_VDEV_STATS_ALT_RSSI_SRG_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 8, val)
+#define WMI_VDEV_STATS_ALT_RSSI_SRG_GET(flag) \
+ WMI_GET_BITS(flag, 24, 8)
+
+#define WMI_VDEV_STATS_HE_BSS_COLOR_EN_SET(flag, val) \
+ WMI_SET_BITS(flag, 0, 1, val)
+#define WMI_VDEV_STATS_HE_BSS_COLOR_EN_GET(flag) \
+ WMI_GET_BITS(flag, 0, 1)
+#define WMI_VDEV_STATS_HE_TXBF_OFDMA_SET(flag, val) \
+ WMI_SET_BITS(flag, 1, 1, val)
+#define WMI_VDEV_STATS_HE_TXBF_OFDMA_GET(flag) \
+ WMI_GET_BITS(flag, 1, 1)
+#define WMI_VDEV_STATS_NON_SRG_ENABLE_SET(flag, val) \
+ WMI_SET_BITS(flag, 2, 1, val)
+#define WMI_VDEV_STATS_NON_SRG_ENABLE_GET(flag) \
+ WMI_GET_BITS(flag, 2, 1)
+#define WMI_VDEV_STATS_SRG_ENABLE_SET(flag, val) \
+ WMI_SET_BITS(flag, 3, 1, val)
+#define WMI_VDEV_STATS_SRG_ENABLE_GET(flag) \
+ WMI_GET_BITS(flag, 3, 1)
+#define WMI_VDEV_STATS_SRP_ENABLE_SET(flag, val) \
+ WMI_SET_BITS(flag, 4, 1, val)
+#define WMI_VDEV_STATS_SRP_ENABLE_GET(flag) \
+ WMI_GET_BITS(flag, 4, 1)
+#define WMI_VDEV_STATS_SR_INITIALIZED_SET(flag, val) \
+ WMI_SET_BITS(flag, 5, 1, val)
+#define WMI_VDEV_STATS_SR_INITIALIZED_GET(flag) \
+ WMI_GET_BITS(flag, 5, 1)
+#define WMI_VDEV_STATS_SR_RINGS_INITIALIZED_SET(flag, val) \
+ WMI_SET_BITS(flag, 6, 1, val)
+#define WMI_VDEV_STATS_SR_RINGS_INITIALIZED_GET(flag) \
+ WMI_GET_BITS(flag, 6, 1)
+#define WMI_VDEV_STATS_PER_AC_OBSS_PD_ENABLE_SET(flag, val) \
+ WMI_SET_BITS(flag, 7, 4, val)
+#define WMI_VDEV_STATS_PER_AC_OBSS_PD_ENABLE_GET(flag) \
+ WMI_GET_BITS(flag, 7, 4)
+#define WMI_VDEV_STATS_IFUP_SET(flag, val) \
+ WMI_SET_BITS(flag, 11, 1, val)
+#define WMI_VDEV_STATS_IFUP_GET(flag) \
+ WMI_GET_BITS(flag, 11, 1)
+#define WMI_VDEV_STATS_IFACTIVE_SET(flag, val) \
+ WMI_SET_BITS(flag, 12, 1, val)
+#define WMI_VDEV_STATS_IFACTIVE_GET(flag) \
+ WMI_GET_BITS(flag, 12, 1)
+#define WMI_VDEV_STATS_IFPAUSED_SET(flag, val) \
+ WMI_SET_BITS(flag, 13, 1, val)
+#define WMI_VDEV_STATS_IFPAUSED_GET(flag) \
+ WMI_GET_BITS(flag, 13, 1)
+#define WMI_VDEV_STATS_IFOUTOFSYNC_SET(flag, val) \
+ WMI_SET_BITS(flag, 14, 1, val)
+#define WMI_VDEV_STATS_IFOUTOFSYNC_GET(flag) \
+ WMI_GET_BITS(flag, 14, 1)
+#define WMI_VDEV_STATS_IS_FREE_SET(flag, val) \
+ WMI_SET_BITS(flag, 15, 1, val)
+#define WMI_VDEV_STATS_IS_FREE_GET(flag) \
+ WMI_GET_BITS(flag, 15, 1)
+#define WMI_VDEV_STATS_IS_NAWDS_SET(flag, val) \
+ WMI_SET_BITS(flag, 16, 1, val)
+#define WMI_VDEV_STATS_IS_NAWDS_GET(flag) \
+ WMI_GET_BITS(flag, 16, 1)
+#define WMI_VDEV_STATS_HW_FLAG_SET(flag, val) \
+ WMI_SET_BITS(flag, 17, 1, val)
+#define WMI_VDEV_STATS_HW_FLAG_GET(flag) \
+ WMI_GET_BITS(flag, 17, 1)
+#define WMI_VDEV_STATS_CH_REQ_FLAG_SET(flag, val) \
+ WMI_SET_BITS(flag, 18, 2, val)
+#define WMI_VDEV_STATS_CH_REQ_FLAG_GET(flag) \
+ WMI_GET_BITS(flag, 18, 2)
+#define WMI_VDEV_STATS_RESTART_RESP_SET(flag, val) \
+ WMI_SET_BITS(flag, 20, 1, val)
+#define WMI_VDEV_STATS_RESTART_RESP_GET(flag) \
+ WMI_GET_BITS(flag, 20, 1)
+#define WMI_VDEV_STATS_FIRST_BEACON_RECV_WAIT_SET(flag, val) \
+ WMI_SET_BITS(flag, 21, 1, val)
+#define WMI_VDEV_STATS_FIRST_BEACON_RECV_WAIT_GET(flag) \
+ WMI_GET_BITS(flag, 21, 1)
+#define WMI_VDEV_STATS_ERPENABLED_SET(flag, val) \
+ WMI_SET_BITS(flag, 22, 1, val)
+#define WMI_VDEV_STATS_ERPENABLED_GET(flag) \
+ WMI_GET_BITS(flag, 22, 1)
+#define WMI_VDEV_STATS_START_RESPONDED_SET(flag, val) \
+ WMI_SET_BITS(flag, 23, 1, val)
+#define WMI_VDEV_STATS_START_RESPONDED_GET(flag) \
+ WMI_GET_BITS(flag, 23, 1)
+#define WMI_VDEV_STATS_BCN_SYNC_CRIT_REQ_ACT_SET(flag, val) \
+ WMI_SET_BITS(flag, 24, 1, val)
+#define WMI_VDEV_STATS_BCN_SYNC_CRIT_REQ_ACT_GET(flag) \
+ WMI_GET_BITS(flag, 24, 1)
+#define WMI_VDEV_STATS_RECAL_NOTIF_REGISTERED_SET(flag, val) \
+ WMI_SET_BITS(flag, 25, 1, val)
+#define WMI_VDEV_STATS_RECAL_NOTIF_REGISTERED_GET(flag) \
+ WMI_GET_BITS(flag, 25, 1)
+#define WMI_VDEV_STATS_BCN_TX_PAUSED_SET(flag, val) \
+ WMI_SET_BITS(flag, 26, 1, val)
+#define WMI_VDEV_STATS_BCN_TX_PAUSED_GET(flag) \
+ WMI_GET_BITS(flag, 26, 1)
+#define WMI_VDEV_STATS_HE_BSS_COLOR_EN_BYPASS_SET(flag, val) \
+ WMI_SET_BITS(flag, 27, 1, val)
+#define WMI_VDEV_STATS_HE_BSS_COLOR_EN_BYPASS_GET(flag) \
+ WMI_GET_BITS(flag, 27, 1)
+#define WMI_VDEV_STATS_DEFAULT_BA_MODE_SET(flag, val) \
+ WMI_SET_BITS(flag, 28, 1, val)
+#define WMI_VDEV_STATS_DEFAULT_BA_MODE_GET(flag) \
+ WMI_GET_BITS(flag, 28, 1)
+#define WMI_VDEV_STATS_BA_256_BITMAP_ENABLE_SET(flag, val) \
+ WMI_SET_BITS(flag, 29, 1, val)
+#define WMI_VDEV_STATS_BA_256_BITMAP_ENABLE_GET(flag) \
+ WMI_GET_BITS(flag, 29, 1)
+#define WMI_VDEV_STATS_BA_256_BITMAP_TX_DISABLE_SET(flag, val) \
+ WMI_SET_BITS(flag, 30, 1, val)
+#define WMI_VDEV_STATS_BA_256_BITMAP_TX_DISABLE_GET(flag) \
+ WMI_GET_BITS(flag, 30, 1)
+#define WMI_VDEV_STATS_IS_MULTI_GROUP_KEY_ENABLED_SET(flag, val) \
+ WMI_SET_BITS(flag, 31, 1, val)
+#define WMI_VDEV_STATS_IS_MULTI_GROUP_KEY_ENABLED_GET(flag) \
+ WMI_GET_BITS(flag, 31, 1)
+
+
/**
* peer statistics.
*/
@@ -13120,6 +15825,8 @@
#define WMI_MLO_FLAGS_SET_LINK_ADD(mlo_flags, value) WMI_SET_BITS(mlo_flags, 8, 1, value)
#define WMI_MLO_FLAGS_GET_LINK_DEL(mlo_flags) WMI_GET_BITS(mlo_flags, 9, 1)
#define WMI_MLO_FLAGS_SET_LINK_DEL(mlo_flags, value) WMI_SET_BITS(mlo_flags, 9, 1, value)
+#define WMI_MLO_FLAGS_GET_BRIDGE_PEER(mlo_flags) WMI_GET_BITS(mlo_flags, 10, 1)
+#define WMI_MLO_FLAGS_SET_BRIDGE_PEER(mlo_flags, value) WMI_SET_BITS(mlo_flags, 10, 1, value)
/* this structure used for pass mlo flags*/
typedef struct {
@@ -13135,7 +15842,8 @@
mlo_force_link_inactive:1, /* indicate this link is forced inactive */
mlo_link_add:1, /* Indicate dynamic link addition in an MLD VAP */
mlo_link_del:1, /* Indicate dynamic link deletion in an MLD VAP */
- unused: 22;
+ mlo_bridge_peer:1, /* Indicate if this link has bridge_peer */
+ unused: 21;
};
A_UINT32 mlo_flags;
};
@@ -15171,6 +17879,17 @@
*/
WMI_VDEV_PARAM_DISABLE_LPI_ANT_OPTIMIZATION, /* 0xB9 */
+ /*
+ * Param to update connected VDEV channel bandwidth.
+ * Target firmware should take care of notifying associated peers
+ * (except TDLS) about change in bandwidth, through OMN/OMI notification
+ * before performing bandwidth update internally.
+ * Please note incase of STA VDEV only BSS peer gets updated,
+ * associated TDLS peer bandwidth wont be impacted.
+ *
+ * The the updated bandwith is specified with a wmi_channel_width value.
+ */
+ WMI_VDEV_PARAM_CHWIDTH_WITH_NOTIFY, /* 0xBA */
/*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE ===
@@ -15331,6 +18050,13 @@
*/
WMI_VDEV_PARAM_SET_DISABLED_SCHED_MODES, /* 0x8012 */
+ /*
+ * SAP Power save with TWT vdev param command
+ * 0 - Disable SAP Power save TWT
+ * 1 - Enable SAP Power save TWT
+ */
+ WMI_VDEV_PARAM_SET_SAP_PS_WITH_TWT, /* 0x8013 */
+
/*=== END VDEV_PARAM_PROTOTYPE SECTION ===*/
} WMI_VDEV_PARAM;
@@ -17203,7 +19929,8 @@
#define WMI_PEER_CHWIDTH_PUNCTURE_BITMAP_GET_CHWIDTH(value32) WMI_GET_BITS(value32, 0x0, 8)
#define WMI_PEER_CHWIDTH_PUNCTURE_BITMAP_GET_PUNCTURE_BMAP(value32) WMI_GET_BITS(value32, 0x8, 16)
-/* peer channel bandwidth and puncture_bitmap
+/*
+ * peer channel bandwidth and puncture_bitmap
* BIT 0-7 - Peer channel width
* This bitfield holds a wmi_channel_width enum value.
* BIT 8-23 - Peer Puncture bitmap where each bit indicates whether
@@ -17216,7 +19943,6 @@
#define WMI_PEER_SET_TX_POWER 0x28
-
typedef struct {
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param */
/** unique id identifying the VDEV, generated by the caller */
@@ -17514,8 +20240,13 @@
A_UINT32 emlsr_trans_delay_us;
/** eMLSR padding delay in microseconds */
A_UINT32 emlsr_padding_delay_us;
- /** Medium Synchronization Duration in microseconds */
- A_UINT32 msd_dur_us;
+ union {
+ /** Medium Synchronization Duration field in units of 32 microseconds */
+ A_UINT32 msd_dur_subfield;
+ /** DEPRECATED - DO NOT USE.
+ * Medium Synchronization Duration in microseconds */
+ A_UINT32 msd_dur_us;
+ };
/** Medium Synchronization OFDM ED Threshold */
A_UINT32 msd_ofdm_ed_thr;
/** Medium Synchronization Max Num of TXOPs */
@@ -17808,9 +20539,18 @@
/**
* Following this structure is the optional TLV:
* struct wmi_scan_blanking_params_info[0/1];
+ * struct wmi_cca_busy_subband_info[];
+ * Reporting subband CCA busy info in host requested manner.
*/
} wmi_chan_info_event_fixed_param;
+typedef struct {
+ /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_cca_busy_subband_info */
+ A_UINT32 tlv_header;
+ /** rx clear count */
+ A_UINT32 rx_clear_count;
+} wmi_cca_busy_subband_info;
+
/**
* The below structure contains parameters related to the scan radio
* blanking feature
@@ -19251,6 +21991,12 @@
A_UINT32 timestamp;
/* Original timeout value in milli seconds when AP added to BL */
A_UINT32 original_timeout;
+ /*
+ * If disallow_linkid_bitmap is not 0, then means current entity
+ * is for MLD AP and bssid field is standing for MLD address.
+ * If all links for MLD AP is disallow, then the value shall be 0xffffffff
+ */
+ A_UINT32 disallow_linkid_bitmap;
} wmi_roam_blacklist_with_timeout_tlv_param;
/** WMI_ROAM_BLACKLIST_EVENT: generated whenever STA needs to move AP to blacklist for a particluar time
@@ -20224,6 +22970,8 @@
WOW_REASON_SCHED_PM_TERMINATED,
/* XGAP entry/exit response */
WOW_REASON_XGAP,
+ /* COEX channel avoid event */
+ WOW_REASON_COEX_CHAVD,
/* add new WOW_REASON_ defs before this line */
WOW_REASON_MAX,
@@ -20280,6 +23028,48 @@
WMI_WOW_RESUME_FLAG_TX_DATA = 0x00000001, /* TX data pending to be sent in resume */
} WMI_WOW_RESUME_FLAG_ENUM;
+/* wow nack reason codes */
+typedef enum {
+ /* WoW error due to unnkown reason */
+ WMI_WOW_NON_ACK_REASON_UNKNOWN = 0,
+
+ /* WoW error due to TX failure */
+ WMI_WOW_NON_ACK_REASON_TX = 1,
+
+ /* WoW error due to some data blocked */
+ WMI_WOW_NON_ACK_REASON_IS_BLOCK = 2,
+
+ /* WoW error in WFA mode */
+ WMI_WOW_NON_ACK_REASON_NOT_ALLOW = 3,
+
+ /* WoW error mac operation fail */
+ WMI_WOW_NON_ACK_REASON_HW_FAIL = 4,
+
+ /* WoW error due to timeout */
+ WMI_WOW_NON_ACK_REASON_TIMEOUT = 5,
+
+ /* WoW error due to RTT or CFR capture active */
+ WMI_WOW_NON_ACK_REASON_RTT_DMA = 6,
+
+ /* WoW error due to roam module holding lock */
+ WMI_WOW_NON_ACK_REASON_ROAM = 7,
+
+ /* WoW error remote peer not sleeping */
+ WMI_WOW_NON_ACK_REASON_PEER_ACTIVE = 8,
+
+ /* WoW error due to WoW entry defer failed */
+ WMI_WOW_NON_ACK_REASON_DEFER_FAILURE = 9,
+
+ /* WoW error due to WoW entry defer timeout */
+ WMI_WOW_NON_ACK_REASON_DEFER_TIMEOUT = 10,
+
+ /* WoW error due to FATAL event */
+ WMI_WOW_NON_ACK_REASON_FATAL_EVENT = 11,
+
+ /* WoW error if close to TBTT */
+ WMI_WOW_NON_ACK_REASON_CLOSE_TO_TBTT = 12,
+} WMI_WOW_NACK_STATUS;
+
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wow_hostwakeup_from_sleep_cmd_fixed_param */
/* reserved0:
@@ -22114,12 +24904,37 @@
A_UINT32 set; /* Set the GPIO pin*/
} wmi_gpio_output_cmd_fixed_param;
+/* WMI_GPIO_STATE_REQ_CMDID */
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gpio_state_req_cmd_fixed_param */
+ A_UINT32 gpio_num; /* GPIO number to get state */
+} wmi_gpio_state_req_cmd_fixed_param;
+
/* WMI_GPIO_INPUT_EVENTID */
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gpio_input_event_fixed_param */
A_UINT32 gpio_num; /* GPIO number which changed state */
} wmi_gpio_input_event_fixed_param;
+typedef enum {
+ /**
+ * The following wmi_gpio_state_type is mutually exclusive.
+ * 0: gpio_invalid_state
+ * 1: gpio_state is LO
+ * 2: gpio_state is HIGH
+ */
+ WMI_GPIO_STATE_INVALID, /* GPIO state is invalid. */
+ WMI_GPIO_STATE_LOW, /* GPIO state is low. */
+ WMI_GPIO_STATE_HIGH, /* GPIO state is high. */
+} WMI_GPIO_STATE_TYPE;
+
+/* WMI_GPIO_STATE_RES_EVENTID */
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gpio_state_res_event_fixed_param */
+ A_UINT32 gpio_num; /* GPIO number */
+ A_UINT32 gpio_state; /* state of GPIO pin defined in WMI_GPIO_STATE_TYPE 0 invalid 1 - LO, 2 -HI*/
+} wmi_gpio_state_res_event_fixed_param;
+
/* WMI_ANT_CONTROLLER_CMDID */
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ant_controller_cmd_fixed_param */
@@ -25674,12 +28489,24 @@
*/
} wmi_stats_ext_event_fixed_param;
+typedef enum {
+ /** Default: no replay required. */
+ WMI_PEER_DELETE_NO_REPLAY = 0,
+ /**
+ * Replay requested due to UMAC hang during Peer delete.
+ * Replay done by Host SW after MLO UMAC SSR recovered the UMAC.
+ */
+ WMI_PEER_DELETE_REPLAY_FOR_UMAC,
+} WMI_PEER_DELETE_REPLAY_T;
+
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_delete_resp_event_fixed_param */
/** unique id identifying the VDEV, generated by the caller */
A_UINT32 vdev_id;
/** peer MAC address */
wmi_mac_addr peer_macaddr;
+ /** WMI_PEER_DELETE_REPLAY_T */
+ A_UINT32 replay_type;
} wmi_peer_delete_resp_event_fixed_param;
typedef struct {
@@ -25694,6 +28521,8 @@
* 2 - EFAILED; Delete all peer failed
*/
A_UINT32 status;
+ /** WMI_PEER_DELETE_REPLAY_T */
+ A_UINT32 replay_type;
} wmi_vdev_delete_all_peer_resp_event_fixed_param;
typedef struct {
@@ -31337,6 +34166,8 @@
WMI_REQUEST_CTRL_PATH_PMLO_STAT = 12,
WMI_REQUEST_CTRL_PATH_CFR_STAT = 13,
WMI_REQUEST_CTRL_PATH_T2LM_STAT = 14,
+ WMI_REQUEST_CTRL_PATH_BLANKING_STAT = 15,
+ WMI_REQUEST_CTRL_PATH_PEER_STAT = 16,
} wmi_ctrl_path_stats_id;
typedef enum {
@@ -31627,6 +34458,16 @@
* and Tx/Rx trigger on any PHY will switch
* from 1x1 to 2x2 on that Phy
*/
+ WMI_HW_MODE_AUX_EMLSR_SINGLE = 9, /* PHYA0 and AUX are active in listen mode
+ * in 1x1 and Tx/Rx trigger on any.
+ * PHY will switch from 1x1 to 2x2
+ * on that Phy.
+ */
+ WMI_HW_MODE_AUX_EMLSR_SPLIT = 10, /* PHYA1 and AUX are active in listen mode
+ * in 1x1 and Tx/Rx trigger on any.
+ * PHY will switch from 1x1 to 2x2
+ * on that Phy.
+ */
} WMI_HW_MODE_CONFIG_TYPE;
/*
@@ -31806,6 +34647,12 @@
#define WMI_SUPPORT_AAR_GET(mld_capability) WMI_GET_BITS(mld_capability, 12, 1)
#define WMI_SUPPORT_AAR_SET(mld_capability, value) WMI_SET_BITS(mld_capability, 12, 1, value)
+/*
+ * 11BE Ext MLD Capability Set and Get macros
+ */
+#define WMI_EXT_MLD_OPERATION_PARAMETER_UPDATE_SUPP_GET(ext_mld_capability) WMI_GET_BITS(ext_mld_capability, 0, 1)
+#define WMI_EXT_MLD_OPERATION_PARAMETER_UPDATE_SUPP_SET(ext_mld_capability, value) WMI_SET_BITS(ext_mld_capability, 0, 1, value)
+
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES */
/* hw_mode_id - identify a particular set of HW characteristics, as specified
@@ -32081,6 +34928,14 @@
};
A_UINT32 mld_capability;
};
+ union {
+ struct {
+ A_UINT32
+ op_update_para_support:1, /* Indicates support of operation parameter update negotiation */
+ reserved3: 31;
+ };
+ A_UINT32 ext_mld_capability;
+ };
} WMI_MAC_PHY_CAPABILITIES_EXT;
typedef struct {
@@ -33398,6 +36253,7 @@
WMI_RETURN_STRING(WMI_RMC_SET_MANUAL_LEADER_CMDID);
WMI_RETURN_STRING(WMI_11D_SCAN_START_CMDID);
WMI_RETURN_STRING(WMI_11D_SCAN_STOP_CMDID);
+ WMI_RETURN_STRING(WMI_VENDOR_PDEV_CMDID);
WMI_RETURN_STRING(WMI_VENDOR_VDEV_CMDID);
WMI_RETURN_STRING(WMI_VENDOR_PEER_CMDID);
WMI_RETURN_STRING(WMI_VDEV_SET_TWT_EDCA_PARAMS_CMDID); /* XPAN TWT */
@@ -33406,6 +36262,12 @@
WMI_RETURN_STRING(WMI_HPA_CMDID);
WMI_RETURN_STRING(WMI_PDEV_SET_TGTR2P_TABLE_CMDID); /* To set target rate to power table */
WMI_RETURN_STRING(WMI_MLO_VDEV_GET_LINK_INFO_CMDID);
+ WMI_RETURN_STRING(WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID);
+ WMI_RETURN_STRING(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID);
+ WMI_RETURN_STRING(WMI_VDEV_STANDALONE_SOUND_CMDID);
+ WMI_RETURN_STRING(WMI_PDEV_SET_RF_PATH_CMDID); /* set RF path of PHY */
+ WMI_RETURN_STRING(WMI_VDEV_PAUSE_CMDID);
+ WMI_RETURN_STRING(WMI_GPIO_STATE_REQ_CMDID);
}
return (A_UINT8 *) "Invalid WMI cmd";
@@ -35241,6 +38103,7 @@
typedef enum {
WMI_DMA_RING_CONFIG_MODULE_SPECTRAL,
WMI_DMA_RING_CONFIG_MODULE_RTT,
+ WMI_DMA_RING_CONFIG_MODULE_CV_UPLOAD,
} WMI_DMA_RING_SUPPORTED_MODULE;
typedef struct {
@@ -35399,6 +38262,7 @@
/* This TLV is followed by another TLV of array of structs.
* wmi_dma_buf_release_entry entries[num_buf_release_entry];
* wmi_dma_buf_release_spectral_meta_data meta_datat[num_meta_data_entry];
+ * wmi_dma_buf_release_cv_upload_meta_data cv_meta_data[num_meta_data_entry]
*/
} wmi_dma_buf_release_fixed_param;
@@ -35750,6 +38614,12 @@
A_UINT32 timestamp;
/* Original timeout value in milli seconds when AP added to BL */
A_UINT32 original_timeout;
+ /*
+ * If disallow_linkid_bitmap is not 0, then means current entity
+ * is for MLD AP and bssid field is standing for MLD address.
+ * If all links for MLD AP is disallow, then the value shall be 0xffffffff
+ */
+ A_UINT32 disallow_linkid_bitmap;
} wmi_pdev_bssid_disallow_list_config_param;
typedef enum {
@@ -36135,6 +39005,11 @@
WMI_ROAM_FAIL_REASON_SAE_PREAUTH_FAIL, /* WPA3-SAE pre-authentication failed */
WMI_ROAM_FAIL_REASON_UNABLE_TO_START_ROAM_HO, /* Roam HO is not started due to FW internal issue */
+ /* Failure reasons to indicate no candidate and final bmiss event sent */
+ WMI_ROAM_FAIL_REASON_NO_AP_FOUND_AND_FINAL_BMISS_SENT, /* No roamable APs found during roam scan and final bmiss event sent */
+ WMI_ROAM_FAIL_REASON_NO_CAND_AP_FOUND_AND_FINAL_BMISS_SENT, /* No candidate APs found during roam scan and final bmiss event sent */
+ WMI_ROAM_FAIL_REASON_CURR_AP_STILL_OK, /* Roam scan not happen due to current network condition is fine */
+
WMI_ROAM_FAIL_REASON_UNKNOWN = 255,
} WMI_ROAM_FAIL_REASON_ID;
@@ -38611,7 +41486,20 @@
#define WMI_EHTCAP_PHY_RX4096QAMWIDERBWDLOFDMA_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 1, 1)
#define WMI_EHTCAP_PHY_RX4096QAMWIDERBWDLOFDMA_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 1, 1, value)
-/* Bits 66-71: reserved */
+/* Bit 66: 20Mhz-only limited capabilities support */
+#define WMI_EHTCAP_PHY_20MHZ_ONLY_CAPS_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 2, 1)
+#define WMI_EHTCAP_PHY_20MHZ_ONLY_CAPS_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 2, 1, value)
+
+/* Bit 67: 20Mhz-only triggered MU beamforming full BW feedback and DL MU-MIMO */
+#define WMI_EHTCAP_PHY_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 3, 1)
+#define WMI_EHTCAP_PHY_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 3, 1, value)
+
+/* Bit 68: 20Mhz-only M-RU support */
+#define WMI_EHTCAP_PHY_20MHZ_ONLY_MRU_SUPP_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 4, 1)
+#define WMI_EHTCAP_PHY_20MHZ_ONLY_MRU_SUPP_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 4, 1, value)
+
+
+/* Bits 69-71: reserved */
/****** End of 11BE EHT PHY Capabilities Information field ******/
@@ -40387,6 +43275,9 @@
#define WMI_TWT_SESSION_FLAG_TWT_PM_RESPONDER_MODE_GET(_var) WMI_GET_BITS(_var, 22, 1)
#define WMI_TWT_SESSION_FLAG_TWT_PM_RESPONDER_MODE_SET(_var, _val) WMI_SET_BITS(_var, 22, 1, _val)
+#define WMI_TWT_SESSION_FLAG_RESTRICTED_TWT_GET(_var) WMI_GET_BITS(_var, 23, 1)
+#define WMI_TWT_SESSION_FLAG_RESTRICTED_TWT_SET(_var, _val) WMI_SET_BITS(_var, 23, 1, _val)
+
typedef struct {
/** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_session_stats_info */
A_UINT32 tlv_hdr;
@@ -40430,7 +43321,7 @@
typedef struct wmi_pdev_vendor_event
{
- /* type is WMI_PDEV_VENDOR_EVENTID */
+ /* type is WMITLV_TAG_STRUC_wmi_vendor_pdev_event_fixed_param */
A_UINT32 tlv_header;
/* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */
A_UINT32 pdev_id;
@@ -40444,10 +43335,11 @@
* would change, causing backwards incompatibilities.
*/
} wmi_pdev_vendor_event_fixed_param;
+typedef wmi_pdev_vendor_event_fixed_param wmi_vendor_pdev_event_fixed_param;
typedef struct wmi_vdev_vendor_event
{
- /* type is WMI_VDEV_VENDOR_EVENTID */
+ /* type is WMITLV_TAG_STRUC_wmi_vendor_vdev_event_fixed_param */
A_UINT32 tlv_header;
/* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */
A_UINT32 pdev_id;
@@ -40463,10 +43355,11 @@
* would change, causing backwards incompatibilities.
*/
} wmi_vdev_vendor_event_fixed_param;
+typedef wmi_vdev_vendor_event_fixed_param wmi_vendor_vdev_event_fixed_param;
typedef struct wmi_peer_vendor_event
{
- /* type is WMI_PEER_VENDOR_EVENTID */
+ /* type is WMITLV_TAG_STRUC_wmi_vendor_peer_event_fixed_param */
A_UINT32 tlv_header;
/* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */
A_UINT32 pdev_id;
@@ -40484,10 +43377,11 @@
* would change, causing backwards incompatibilities.
*/
} wmi_peer_vendor_event_fixed_param;
+typedef wmi_peer_vendor_event_fixed_param wmi_vendor_peer_event_fixed_param;
typedef struct wmi_pdev_vendor_cmd
{
- /* type is WMI_PDEV_VENDOR_CMDID */
+ /* type is WMITLV_TAG_STRUC_wmi_vendor_pdev_cmd_fixed_param */
A_UINT32 tlv_header;
/* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */
A_UINT32 pdev_id;
@@ -40501,10 +43395,11 @@
* would change, causing backwards incompatibilities.
*/
} wmi_pdev_vendor_cmd_fixed_param;
+typedef wmi_pdev_vendor_cmd_fixed_param wmi_vendor_pdev_cmd_fixed_param;
typedef struct wmi_vdev_vendor_cmd
{
- /* type is WMI_VDEV_VENDOR_CMDID */
+ /* type is WMITLV_TAG_STRUC_wmi_vendor_vdev_cmd_fixed_param */
A_UINT32 tlv_header;
/* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */
A_UINT32 pdev_id;
@@ -40520,10 +43415,11 @@
* would change, causing backwards incompatibilities.
*/
} wmi_vdev_vendor_cmd_fixed_param;
+typedef wmi_vdev_vendor_cmd_fixed_param wmi_vendor_vdev_cmd_fixed_param;
typedef struct wmi_peer_vendor_cmd
{
- /* type is WMI_PEER_VENDOR_CMDID */
+ /* type is WMITLV_TAG_STRUC_wmi_vendor_peer_cmd_fixed_param */
A_UINT32 tlv_header;
/* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */
A_UINT32 pdev_id;
@@ -40541,6 +43437,7 @@
* would change, causing backwards incompatibilities.
*/
} wmi_peer_vendor_cmd_fixed_param;
+typedef wmi_peer_vendor_cmd_fixed_param wmi_vendor_peer_cmd_fixed_param;
typedef enum {
WMI_MLO_LINK_FORCE_ACTIVE = 1, /* Force specific links active */
@@ -40715,6 +43612,10 @@
#define WMI_MAX_NUM_PREFERRED_LINKS 4
+/* NOTE:
+ * wmi_peer_preferred_link_map will be deprecated and replaced
+ * by wmi_mlo_peer_link_control_param.
+ */
typedef struct {
/** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_preferred_link_map */
A_UINT32 tlv_header;
@@ -40738,6 +43639,62 @@
A_UINT32 expected_max_latency_ms[WLAN_MAX_AC];
} wmi_peer_preferred_link_map;
+#define WMI_MLO_PEER_LINK_CONTROL_PARAM_SET_TX_LINK_TUPLE_CONFIG(comp, value) \
+ WMI_SET_BITS(comp, 0, 1, value)
+#define WMI_MLO_PEER_LINK_CONTROL_PARAM_GET_TX_LINK_TUPLE_CONFIG(comp) \
+ WMI_GET_BITS(comp, 0, 1)
+
+#define WMI_MLO_PEER_LINK_CONTROL_PARAM_SET_PREFERRED_LINK_CONFIG(comp, value) \
+ WMI_SET_BITS(comp, 1, 1, value)
+#define WMI_MLO_PEER_LINK_CONTROL_PARAM_GET_PREFERRED_LINK_CONFIG(comp) \
+ WMI_GET_BITS(comp, 1, 1)
+
+#define WMI_MAX_NUM_MLO_LINKS 5
+
+typedef struct {
+ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_preferred_link_map */
+ A_UINT32 tlv_header;
+
+ /** flags:
+ * Bit0 : tx_link_tuple enable/disable.
+ * When enabled, f/w picks the links in tx_link_tuple_bitmap
+ * for TX scheduling.
+ * Bit1 : preferred_link enable/disable.
+ * When enabled, f/w schedules the data on preferred link first.
+ * If it fails to deliver within a timeout, it additionally
+ * starts attempting TX on non-preferred links.
+ * Bit2-31 : reserved
+ */
+ A_UINT32 flags;
+
+ /* num_links: number of links present in link_priority_order array below.
+ * 0 - we dont have sorted list of link priority
+ * non zero - this should be the max number of links that the peer supports.
+ */
+ A_UINT32 num_links;
+
+ /* link_priority_order:
+ * [0] - ID of highest priority link,
+ * [1] - ID of 2nd highest priority link, etc.
+ */
+ A_UINT32 link_priority_order[WMI_MAX_NUM_MLO_LINKS];
+
+ /* tx_link_tuple_bitmap:
+ * bitmap of indices within link_priority_order array that needs to be
+ * selected in the TX link tuple.
+ * FW will not attempt scheduling on a link if it is not part of the
+ * tx_link_tuple.
+ */
+ A_UINT32 tx_link_tuple_bitmap;
+
+ /* max_timeout_ms: applicable only when preferred_link is enabled
+ * 0 - max_timeout_ms to be estimated in Firmware
+ * Non 0 - value beyond which, firmware should additionally start
+ * scheduling on non preferred links
+ */
+ A_UINT32 max_timeout_ms[WLAN_MAX_AC];
+} wmi_mlo_peer_link_control_param;
+
typedef struct {
/** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_tid_to_link_map_fixed_param */
A_UINT32 tlv_header;
@@ -40753,6 +43710,8 @@
* - struct wmi_peer_preferred_link_map peer_preferred_link_map[];
* Note - TLV array of peer_preferred_link_map has either 0 or 1
* entries, not multiple entries.
+ * - struct wmi_mlo_peer_link_control_param[];
+ * Note: can have 0 or 1 entry.
*/
} wmi_peer_tid_to_link_map_fixed_param;
@@ -40820,6 +43779,9 @@
#define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_DUR_TIME_GET(_var) WMI_GET_BITS(_var, 4, 1)
#define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_DUR_TIME_SET(_var, _val) WMI_SET_BITS(_var, 4, 1, _val)
+#define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_SIZE_GET(_var) WMI_GET_BITS(_var, 5, 1)
+#define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_SIZE_SET(_var, _val) WMI_SET_BITS(_var, 5, 1, _val)
+
#define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_PRE_GET(_var) WMI_GET_BITS(_var, 8, 8)
#define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_PRE_SET(_var, _val) WMI_SET_BITS(_var, 8, 8, _val)
@@ -40900,7 +43862,12 @@
* // 0 - Expected Duration Field
* // not Present
*
- * reserved:3
+ * WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_SIZE_GET
+ * WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_SIZE_SET
+ * link_mapping_size:1 // 1 - Link Mapping Size 1 Octets
+ * // 0 - Link Mapping Size 2 Octets
+ *
+ * reserved:2
*
* WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_PRE_GET /
* WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_PRE_SET
@@ -41982,6 +44949,337 @@
A_UINT32 chan_freq; /* Channel frequency in MHz */
} wmi_mlo_vdev_link_info;
+/* Manual UL OFDMA trigger frame data structures */
+
+typedef enum {
+ WMI_UL_OFDMA_MANUAL_TRIG_TXERR_NONE,
+ WMI_UL_OFDMA_MANUAL_TRIG_TXERR_RESP, /* response timeout, mismatch,
+ * BW mismatch, mimo ctrl mismatch,
+ * CRC error.. */
+ WMI_UL_OFDMA_MANUAL_TRIG_TXERR_FILT, /* blocked by tx filtering */
+ WMI_UL_OFDMA_MANUAL_TRIG_TXERR_FIFO, /* fifo, misc errors in HW */
+ WMI_UL_OFDMA_MANUAL_TRIG_TXERR_SWABORT, /* software initiated abort
+ * (TX_ABORT) */
+
+ WMI_UL_OFDMA_MANUAL_TRIG_TXERR_MAX = 0xff,
+ WMI_UL_OFDMA_MANUAL_TRIG_TXERR_INVALID =
+ WMI_UL_OFDMA_MANUAL_TRIG_TXERR_MAX
+} wmi_ul_ofdma_manual_trig_txerr_t;
+
+typedef struct {
+ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param */
+ A_UINT32 tlv_header;
+
+ /* VDEV identifier */
+ A_UINT32 vdev_id;
+
+ /* To indicate whether feedback event is for SU (0) or MU trigger (1) */
+ A_UINT32 feedback_trig_type;
+
+ /* Feedback Params */
+ A_UINT32 curr_su_manual_trig_count;
+ A_UINT32 remaining_su_manual_trig;
+ A_UINT32 remaining_mu_trig_peers;
+ A_UINT32 manual_trig_status; /* holds a wmi_ul_ofdma_manual_trig_txerr_t */
+
+ /**
+ * This TLV is followed by TLVs below:
+ * wmi_mac_addr peer_macaddr[];
+ * Array length corresponds to the number of triggered peers
+ */
+} wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param;
+
+typedef struct {
+ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_manual_mu_trig_cmd_fixed_param */
+ A_UINT32 tlv_header;
+
+ /* VDEV identifier */
+ A_UINT32 vdev_id;
+
+ /* Configurable Parameters for manual UL OFDMA Multi-User Trigger frame */
+ A_UINT32 manual_trig_preferred_ac;
+ /**
+ * This TLV is followed by TLVs below:
+ * wmi_mac_addr peer_macaddr[];
+ * The array has one element for each peer to be included in the
+ * manually-triggered UL MU transmission.
+ */
+} wmi_vdev_set_manual_mu_trig_cmd_fixed_param;
+
+typedef struct {
+ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_manual_su_trig_cmd_fixed_param */
+ A_UINT32 tlv_header;
+
+ /* VDEV identifier */
+ A_UINT32 vdev_id;
+
+ /* Configurable Parameters for manual UL OFDMA Single-User Trigger frame */
+ wmi_mac_addr peer_macaddr;
+ A_UINT32 manual_trig_preferred_ac;
+ A_UINT32 num_su_manual_trig;
+ A_UINT32 manual_trig_length;
+ A_UINT32 manual_trig_mcs;
+ A_UINT32 manual_trig_nss;
+ A_INT32 manual_trig_target_rssi; /* units = dBm */
+} wmi_vdev_set_manual_su_trig_cmd_fixed_param;
+
+
+#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_ASNR_LENGTH(asnr_params, value) \
+ WMI_SET_BITS(asnr_params, 0, 16, value)
+#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_ASNR_LENGTH(asnr_params) \
+ WMI_GET_BITS(asnr_params, 0, 16)
+
+#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_ASNR_OFFSET(asnr_params, value) \
+ WMI_SET_BITS(asnr_params, 16, 16, value)
+#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_ASNR_OFFSET(asnr_params) \
+ WMI_GET_BITS(asnr_params, 16, 16)
+
+#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_DSNR_LENGTH(dsnr_params, value) \
+ WMI_SET_BITS(dsnr_params, 0, 16, value)
+#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_DSNR_LENGTH(dsnr_params) \
+ WMI_GET_BITS(dsnr_params, 0, 16)
+
+#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_DSNR_OFFSET(dsnr_params, value) \
+ WMI_SET_BITS(dsnr_params, 16, 16, value)
+#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_DSNR_OFFSET(dsnr_params) \
+ WMI_GET_BITS(dsnr_params, 16, 16)
+
+#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_FB_PARAMS_NC(fb_params, value) \
+ WMI_SET_BITS(fb_params, 0, 2, value)
+#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_FB_PARAMS_NC(fb_params) \
+ WMI_GET_BITS(fb_params, 0, 2)
+
+#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_FB_PARAMS_NSS_NUM(fb_params, value) \
+ WMI_SET_BITS(fb_params, 2, 2, value)
+#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_FB_PARAMS_NSS_NUM(fb_params) \
+ WMI_GET_BITS(fb_params, 2, 2)
+
+
+#define WMI_SET_STANDALONE_SOUND_PARAMS_FB_TYPE(snd_params, value) \
+ WMI_SET_BITS(snd_params, 0, 1, value)
+#define WMI_GET_STANDALONE_SOUND_PARAMS_FB_TYPE(snd_params) \
+ WMI_GET_BITS(snd_params, 0, 1)
+
+#define WMI_SET_STANDALONE_SOUND_PARAMS_NG(snd_params, value) \
+ WMI_SET_BITS(snd_params, 1, 2, value)
+#define WMI_GET_STANDALONE_SOUND_PARAMS_NG(snd_params) \
+ WMI_GET_BITS(snd_params, 1, 2)
+
+#define WMI_SET_STANDALONE_SOUND_PARAMS_CB(snd_params, value) \
+ WMI_SET_BITS(snd_params, 3, 1, value)
+#define WMI_GET_STANDALONE_SOUND_PARAMS_CB(snd_params) \
+ WMI_GET_BITS(snd_params, 3, 1)
+
+#define WMI_SET_STANDALONE_SOUND_PARAMS_BW(snd_params, value) \
+ WMI_SET_BITS(snd_params, 4, 3, value)
+#define WMI_GET_STANDALONE_SOUND_PARAMS_BW(snd_params) \
+ WMI_GET_BITS(snd_params, 4, 3)
+
+
+typedef enum _WMI_STANDALONE_SOUND_STATUS_T {
+ WMI_STANDALONE_SOUND_STATUS_OK,
+ WMI_STANDALONE_SOUND_STATUS_ERR_NUM_PEERS_EXCEEDED,
+ WMI_STANDALONE_SOUND_STATUS_ERR_NG_INVALID,
+ WMI_STANDALONE_SOUND_STATUS_ERR_NUM_REPEAT_EXCEEDED,
+ WMI_STANDALONE_SOUND_STATUS_ERR_PEER_DOESNOT_SUPPORT_BW,
+ WMI_STANDALONE_SOUND_STATUS_ERR_INVALID_PEER,
+ WMI_STANDALONE_SOUND_STATUS_ERR_INVALID_VDEV,
+ WMI_STANDALONE_SOUND_STATUS_ERR_PEER_DOES_NOT_SUPPORT_MU_FB,
+ WMI_STANDALONE_SOUND_STATUS_ERR_DMA_NOT_CONFIGURED,
+ WMI_STANDALONE_SOUND_STATUS_ERR_COMPLETE_FAILURE,
+} WMI_STANDALONE_SOUND_STATUS_T;
+
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_dma_buf_release_cv_upload_meta_data */
+ /** Set if the CV is valid */
+ A_UINT32 is_valid;
+ /** Feedback type */
+ A_UINT32 fb_type;
+ /**
+ * [15:0] ASNR length
+ * [31:16] ASNR offset
+ */
+ A_UINT32 asnr_params;
+ /**
+ * [15:0] DSNR length
+ * [31:16] DSNR offset
+ */
+ A_UINT32 dsnr_params;
+ /** Peer mac address */
+ wmi_mac_addr peer_mac_address;
+ /**
+ * [1:0] Nc
+ * [3:2] nss_num
+ */
+ A_UINT32 fb_params;
+} wmi_dma_buf_release_cv_upload_meta_data;
+
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_standalone_sounding_cmd_fixed_param */
+ /** vdev identifier */
+ A_UINT32 vdev_id;
+ /** sounding_params:
+ * [0] Feedback type
+ * [2:1] Ng
+ * [3] Codebook
+ * [6:4] BW
+ * 0 = 20 MHz
+ * 1 = 40 MHz
+ * 2 = 80 MHz
+ * 3 = 160 MHz
+ * 4 = 320 MHz
+ * [31:7] Reserved
+ */
+ A_UINT32 sounding_params;
+ /** The number of sounding repeats */
+ A_UINT32 num_sounding_repeats;
+ /**
+ * TLV (tag length value) parameters follow the
+ * structure. The TLV's are:
+ * wmi_mac_addr peer_list[num_peers];
+ */
+} wmi_standalone_sounding_cmd_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_standalone_sounding_evt_fixed_param */
+ /** vdev identifier */
+ A_UINT32 vdev_id;
+ /** status:
+ * standalone sounding command status -
+ * refer to WMI_STANDALONE_SOUND_STATUS_T
+ */
+ A_UINT32 status;
+ /** number of CV buffers uploaded */
+ A_UINT32 buffer_uploaded;
+ /** TLV (tag length value) parameters follow the
+ * structure. The TLV's are:
+ * A_UINT32 snd_failed[num_sounding_repeats];
+ * snd_failed[] array's elements hold the number of failures
+ * for each sounding.
+ */
+} wmi_standalone_sounding_evt_fixed_param;
+
+typedef struct {
+ /*
+ * TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_cmd_fixed_param
+ */
+ A_UINT32 tlv_header;
+ /* pdev_id for identifying the MAC */
+ A_UINT32 pdev_id;
+ /*
+ * rf_path :
+ * 0 - primary RF path
+ * 1 - secondary RF path
+ */
+ A_UINT32 rf_path;
+} wmi_pdev_set_rf_path_cmd_fixed_param;
+
+#define WMI_SET_RX_PEER_STATS_RESP_TYPE(rx_params, value) \
+ WMI_SET_BITS(rx_params, 0, 1, value)
+#define WMI_GET_RX_PEER_STATS_RESP_TYPE(rx_params) \
+ WMI_GET_BITS(rx_params, 0, 1)
+
+#define WMI_SET_RX_PEER_STATS_MCS(rx_params, value) \
+ WMI_SET_BITS(rx_params, 1, 5, value)
+#define WMI_GET_RX_PEER_STATS_MCS(rx_params) \
+ WMI_GET_BITS(rx_params, 1, 5)
+
+#define WMI_SET_RX_PEER_STATS_NSS(rx_params, value) \
+ WMI_SET_BITS(rx_params, 6, 4, value)
+#define WMI_GET_RX_PEER_STATS_NSS(rx_params) \
+ WMI_GET_BITS(rx_params, 6, 4)
+
+#define WMI_SET_RX_PEER_STATS_GI_LTF_TYPE(rx_params, value) \
+ WMI_SET_BITS(rx_params, 10, 4, value)
+#define WMI_GET_RX_PEER_STATS_GI_LTF_TYPE(rx_params) \
+ WMI_GET_BITS(rx_params, 10, 4)
+
+typedef enum {
+ WMI_PEER_RX_RESP_SU = 0,
+ WMI_PEER_RX_RESP_MIMO = 1,
+ WMI_PEER_RX_RESP_OFDMA = 2,
+} WMI_PEER_RX_RESP_TYPE;
+
+typedef struct {
+ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo */
+ A_UINT32 tlv_header;
+
+ /* Peer mac address */
+ wmi_mac_addr peer_macaddr;
+
+ /* Per peer RX parameters */
+ /* [0] - Flag to indicate if peer responded with QoS Data or QoS NULL.
+ * 0 -> indicates QoS NULL, 1-> indicates QoS Data response
+ * [5:1] - MCS - Peer response MCS
+ * [9:6] - NSS - Peer response NSS
+ * [13:10] - GI LTF Type - Peer response GI/LTF type
+ * 0 => gi == GI_1600 && ltf == 1x LTF
+ * 1 => gi == GI_1600 && ltf == 2x LTF
+ * 2 => gi == GI_3200 && ltf == 4x LTF
+ * [31:14] - Reserved
+ */
+ A_UINT32 rx_peer_stats;
+
+ /* Peer response per chain RSSI */
+ A_INT32 peer_per_chain_rssi[WMI_MAX_CHAINS];
+} wmi_manual_ul_ofdma_trig_rx_peer_userinfo;
+
+typedef struct {
+ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param */
+ A_UINT32 tlv_header;
+
+ A_UINT32 vdev_id; /* VDEV identifier */
+
+ /* combined_rssi:
+ * RX Combined RSSI in dBm
+ * Value indicates the average RSSI per 20MHz by averaging the total RSSI
+ * across entire BW for each OFDMA STA
+ */
+ A_INT32 combined_rssi;
+
+ /* rx_ppdu_resp_type:
+ * RX PPDU Response Type
+ * Refer WMI_PEER_RX_RESP_TYPE for possible values
+ */
+ A_UINT32 rx_ppdu_resp_type;
+
+ /* rx_resp_bw:
+ * RX response bandwidth
+ * 0 = 20 MHz
+ * 1 = 40 MHz
+ * 2 = 80 MHz
+ * 3 = 160 MHz
+ * 4 = 320 MHz
+ */
+ A_UINT32 rx_resp_bw;
+
+ /**
+ * This TLV is followed by TLVs below:
+ * wmi_manual_ul_ofdma_trig_rx_peer_userinfo rx_peer_userinfo[]
+ * TLV length specified by number of peer responses for manual
+ * UL OFDMA trigger
+ */
+} wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param;
+
+typedef enum _WMI_VDEV_PAUSE_TYPE
+{
+ WMI_VDEV_PAUSE_TYPE_UNKNOWN = 0,
+ WMI_VDEV_PAUSE_TYPE_MLO_LINK = 1,
+ WMI_VDEV_PAUSE_TYPE_TX = 2,
+} WMI_VDEV_PAUSE_TYPE;
+
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_vdev_pause_cmd_fixed_param */
+ A_UINT32 tlv_header;
+ /* VDEV identifier */
+ A_UINT32 vdev_id;
+ /** type of pause, refer to WMI_VDEV_PAUSE_TYPE */
+ A_UINT32 pause_type;
+ /** duration of pause, in unit of ms */
+ A_UINT32 pause_dur_ms;
+} wmi_vdev_pause_cmd_fixed_param;
+
/* ADD NEW DEFS HERE */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 0b593fd..f5d8720 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
#define __WMI_VER_MINOR_ 0
/** WMI revision number has to be incremented when there is a
* change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1290
+#define __WMI_REVISION_ 1319
/** The Version Namespace should not be normally changed. Only
* host and firmware of the same WMI namespace will work
diff --git a/hw/kiwi/v2/wcss_seq_hwioreg_umac.h b/hw/kiwi/v2/wcss_seq_hwioreg_umac.h
index 7c7ebed..f594c52 100644
--- a/hw/kiwi/v2/wcss_seq_hwioreg_umac.h
+++ b/hw/kiwi/v2/wcss_seq_hwioreg_umac.h
@@ -1,6 +1,5 @@
-
/*
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@@ -236,6 +235,11 @@
#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x53c)
#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x540)
#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x544)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x) ((x) + 0x558)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0
#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x55c)
#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0x8a4)
#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00
diff --git a/hw/qcn9224/v1/mon_destination_ring.h b/hw/qcn9224/v1/mon_destination_ring.h
index 98ae420..861a72a 100644
--- a/hw/qcn9224/v1/mon_destination_ring.h
+++ b/hw/qcn9224/v1/mon_destination_ring.h
@@ -1,5 +1,5 @@
-/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+/* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -32,7 +32,7 @@
struct mon_destination_ring {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+#ifndef BIG_ENDIAN_HOST
uint32_t stat_buf_virt_addr_31_0 : 32;
uint32_t stat_buf_virt_addr_63_32 : 32;
uint32_t ppdu_id : 32;
diff --git a/hw/qcn9224/v2/mon_destination_ring.h b/hw/qcn9224/v2/mon_destination_ring.h
index 98ae420..861a72a 100644
--- a/hw/qcn9224/v2/mon_destination_ring.h
+++ b/hw/qcn9224/v2/mon_destination_ring.h
@@ -1,5 +1,5 @@
-/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+/* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -32,7 +32,7 @@
struct mon_destination_ring {
-#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+#ifndef BIG_ENDIAN_HOST
uint32_t stat_buf_virt_addr_31_0 : 32;
uint32_t stat_buf_virt_addr_63_32 : 32;
uint32_t ppdu_id : 32;
diff --git a/hw/wcn6450/v1/HALcomdef.h b/hw/wcn6450/v1/HALcomdef.h
new file mode 100644
index 0000000..9e8d68a
--- /dev/null
+++ b/hw/wcn6450/v1/HALcomdef.h
@@ -0,0 +1,53 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef HAL_COMDEF_H
+#define HAL_COMDEF_H
+
+#ifndef _ARM_ASM_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "com_dtypes.h"
+
+#ifndef _BOOL32_DEFINED
+typedef unsigned long int bool32;
+#define _BOOL32_DEFINED
+#endif
+
+#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF
+
+ #define inp(port) (*((volatile byte *) (port)))
+ #define inpw(port) (*((volatile word *) (port)))
+ #define inpdw(port) (*((volatile dword *)(port)))
+
+ #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val)))
+ #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val)))
+ #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
diff --git a/hw/wcn6450/v1/HALhwio.h b/hw/wcn6450/v1/HALhwio.h
new file mode 100644
index 0000000..b3b004d
--- /dev/null
+++ b/hw/wcn6450/v1/HALhwio.h
@@ -0,0 +1,424 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef HAL_HWIO_H
+#define HAL_HWIO_H
+
+#include "HALcomdef.h"
+
+#define SEQ_WCSS_WCMN_OFFSET SEQ_WCSS_TOP_CMN_OFFSET
+#define SEQ_WCSS_PMM_OFFSET SEQ_WCSS_PMM_TOP_OFFSET
+
+#define HWIO_BASE_PTR(base) base##_BASE_PTR
+
+#ifdef __ARMCC_VERSION
+ #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base)
+#else
+ #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base)
+#endif
+
+#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym)
+#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index)
+#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2)
+#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3)
+
+#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym)
+#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index)
+#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2)
+#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym)
+#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index)
+#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2)
+#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3)
+
+#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym)
+#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index)
+#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2)
+#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym)
+#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index)
+#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2)
+#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3)
+
+#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym)
+#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index)
+#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2)
+#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3)
+
+#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask)
+#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask)
+#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask)
+#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+
+#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym)
+#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index)
+#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2)
+#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask)
+#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask)
+#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)
+#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+
+#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val)
+#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val)
+#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val)
+#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val)
+#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val)
+#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val)
+#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val)
+#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val)
+#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val)
+#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val)
+#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)
+#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)
+#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)
+#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val)
+#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val)
+#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OPT_OUTM2(hwiosym, mask1, mask2, val1, val2) { \
+ A_UINT32 reg; \
+ reg = HWIO_IN(hwiosym); \
+ reg = (reg & ~mask1) | (val1 & mask1); \
+ reg = (reg & ~mask2) | (val2 & mask2); \
+ HWIO_OUT(hwiosym, reg); \
+ }
+
+#define HWIO_OPT_OUTM3(hwiosym, mask1, mask2, mask3, val1, val2, val3) { \
+ A_UINT32 reg; \
+ reg = HWIO_IN(hwiosym); \
+ reg = (reg & ~mask1) | (val1 & mask1); \
+ reg = (reg & ~mask2) | (val2 & mask2); \
+ reg = (reg & ~mask3) | (val3 & mask3); \
+ HWIO_OUT(hwiosym, reg); \
+ }
+
+#define HWIO_OPT_OUTM4(hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
+ A_UINT32 reg; \
+ reg = HWIO_IN(hwiosym); \
+ reg = (reg & ~mask1) | (val1 & mask1); \
+ reg = (reg & ~mask2) | (val2 & mask2); \
+ reg = (reg & ~mask3) | (val3 & mask3); \
+ reg = (reg & ~mask4) | (val4 & mask4); \
+ HWIO_OUT(hwiosym, reg); \
+ }
+
+#define HWIO_OPT_OUTM5(hwiosym, mask1, mask2, mask3, mask4, mask5, val1, val2, val3, val4, val5) { \
+ A_UINT32 reg; \
+ reg = HWIO_IN(hwiosym); \
+ reg = (reg & ~mask1) | (val1 & mask1); \
+ reg = (reg & ~mask2) | (val2 & mask2); \
+ reg = (reg & ~mask3) | (val3 & mask3); \
+ reg = (reg & ~mask4) | (val4 & mask4); \
+ reg = (reg & ~mask5) | (val5 & mask5); \
+ HWIO_OUT(hwiosym, reg); \
+ }
+
+#define HWIO_OPT_OUTM6(hwiosym, mask1, mask2, mask3, mask4, mask5, mask6, val1, val2, val3, val4, val5, val6) { \
+ A_UINT32 reg; \
+ reg = HWIO_IN(hwiosym); \
+ reg = (reg & ~mask1) | (val1 & mask1); \
+ reg = (reg & ~mask2) | (val2 & mask2); \
+ reg = (reg & ~mask3) | (val3 & mask3); \
+ reg = (reg & ~mask4) | (val4 & mask4); \
+ reg = (reg & ~mask5) | (val5 & mask5); \
+ reg = (reg & ~mask6) | (val6 & mask6); \
+ HWIO_OUT(hwiosym, reg); \
+ }
+
+#define HWIO_OPT_OUT2F(io, field1, field2, val1, val2) HWIO_OPT_OUTM2(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
+#define HWIO_OPT_OUT3F(io, field1, field2, field3, val1, val2, val3) HWIO_OPT_OUTM3(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
+#define HWIO_OPT_OUT4F(io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OPT_OUTM4(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
+#define HWIO_OPT_OUT5F(io, field1, field2, field3, field4, field5, val1, val2, val3, val4, val5) HWIO_OPT_OUTM5(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5) )
+#define HWIO_OPT_OUT6F(io, field1, field2, field3, field4, field5, field6, val1, val2, val3, val4, val5, val6) HWIO_OPT_OUTM6(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), HWIO_FMSK(io, field6), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5), (uint32)(val6) << HWIO_SHFT(io, field6) )
+
+#define HWIO_OPT_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) { \
+ A_UINT32 reg; \
+ reg = HWIO_INX(base, hwiosym); \
+ reg = (reg & ~mask1) | (val1 & mask1); \
+ reg = (reg & ~mask2) | (val2 & mask2); \
+ HWIO_OUTX(base, hwiosym, reg); \
+ }
+
+#define HWIO_OPT_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \
+ A_UINT32 reg; \
+ reg = HWIO_INX(base, hwiosym); \
+ reg = (reg & ~mask1) | (val1 & mask1); \
+ reg = (reg & ~mask2) | (val2 & mask2); \
+ reg = (reg & ~mask3) | (val3 & mask3); \
+ HWIO_OUTX(base, hwiosym, reg); \
+ }
+
+#define HWIO_OPT_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
+ A_UINT32 reg; \
+ reg = HWIO_INX(base, hwiosym); \
+ reg = (reg & ~mask1) | (val1 & mask1); \
+ reg = (reg & ~mask2) | (val2 & mask2); \
+ reg = (reg & ~mask3) | (val3 & mask3); \
+ reg = (reg & ~mask4) | (val4 & mask4); \
+ HWIO_OUTX(base, hwiosym, reg); \
+ }
+
+#define HWIO_OPT_OUTXM5(base, hwiosym, mask1, mask2, mask3, mask4, mask5, val1, val2, val3, val4, val5) { \
+ A_UINT32 reg; \
+ reg = HWIO_INX(base, hwiosym); \
+ reg = (reg & ~mask1) | (val1 & mask1); \
+ reg = (reg & ~mask2) | (val2 & mask2); \
+ reg = (reg & ~mask3) | (val3 & mask3); \
+ reg = (reg & ~mask4) | (val4 & mask4); \
+ reg = (reg & ~mask5) | (val5 & mask5); \
+ HWIO_OUTX(base, hwiosym, reg); \
+ }
+
+#define HWIO_OPT_OUTXM6(base, hwiosym, mask1, mask2, mask3, mask4, mask5, mask6, val1, val2, val3, val4, val5, val6) { \
+ A_UINT32 reg; \
+ reg = HWIO_INX(base, hwiosym); \
+ reg = (reg & ~mask1) | (val1 & mask1); \
+ reg = (reg & ~mask2) | (val2 & mask2); \
+ reg = (reg & ~mask3) | (val3 & mask3); \
+ reg = (reg & ~mask4) | (val4 & mask4); \
+ reg = (reg & ~mask5) | (val5 & mask5); \
+ reg = (reg & ~mask6) | (val6 & mask6); \
+ HWIO_OUTX(base, hwiosym, reg); \
+ }
+
+#define HWIO_OPT_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OPT_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
+#define HWIO_OPT_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OPT_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
+#define HWIO_OPT_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OPT_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
+#define HWIO_OPT_OUTX5F(base, io, field1, field2, field3, field4, field5, val1, val2, val3, val4, val5) HWIO_OPT_OUTXM5(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5) )
+#define HWIO_OPT_OUTX6F(base, io, field1, field2, field3, field4, field5, field6, val1, val2, val3, val4, val5, val6) HWIO_OPT_OUTXM6(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), HWIO_FMSK(io, field6), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5), (uint32)(val6) << HWIO_SHFT(io, field6) )
+
+#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
+#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
+#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
+
+#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+
+#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym)
+#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index)
+#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym)
+#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym)
+#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym)
+#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val)
+#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+
+#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym)
+#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index)
+
+#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN
+#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index)
+#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2)
+#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3)
+#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask)
+#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask)
+#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask)
+#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask)
+#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val)
+#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val)
+#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val)
+#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val)
+#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val)
+#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val)
+#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val)
+#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val)
+#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR
+#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index)
+#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2)
+#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3)
+#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS
+#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index)
+#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2)
+#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3)
+#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS
+#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index)
+#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2)
+#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3)
+#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK
+#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index)
+#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK
+#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT
+#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT
+#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow
+#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index)
+#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL
+
+#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base)
+#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index)
+#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2)
+#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3)
+#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask)
+#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask)
+#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask)
+#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask)
+#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val)
+#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val)
+#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val)
+#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val)
+#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val)
+#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \
+ HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+ HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+ }
+#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \
+ HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+ HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+ HWIO_##hwiosym##_OUTM(base, mask3, val3); \
+ }
+#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
+ HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+ HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+ HWIO_##hwiosym##_OUTM(base, mask3, val3); \
+ HWIO_##hwiosym##_OUTM(base, mask4, val4); \
+ }
+
+#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val)
+#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val)
+#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val)
+#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base)
+#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index)
+#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2)
+#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3)
+#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base)
+#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index)
+#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2)
+#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3)
+
+#define HWIO_INTLOCK()
+#define HWIO_INTFREE()
+
+#define __inp(port) (*((volatile uint8 *) (port)))
+#define __inpw(port) (*((volatile uint16 *) (port)))
+#ifdef PLAT_MSL_REG_READ
+#ifdef __cplusplus
+extern "C" {
+#endif
+extern uint32 plat_register_read(uint32 addr);
+#ifdef __cplusplus
+}
+#endif
+
+#define __inpdw(port) plat_register_read((uint32) (port))
+#else
+#define __inpdw(port) (*((volatile uint32 *) (port)))
+#endif
+#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val)))
+#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val)))
+#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val)))
+
+#ifdef HAL_HWIO_EXTERNAL
+
+#undef __inp
+#undef __inpw
+#undef __inpdw
+#undef __outp
+#undef __outpw
+#undef __outpdw
+
+#define __inp(port) __inp_extern(port)
+#define __inpw(port) __inpw_extern(port)
+#define __inpdw(port) __inpdw_extern(port)
+#define __outp(port, val) __outp_extern(port, val)
+#define __outpw(port, val) __outpw_extern(port, val)
+#define __outpdw(port, val) __outpdw_extern(port, val)
+
+extern uint8 __inp_extern ( uint32 nAddr );
+extern uint16 __inpw_extern ( uint32 nAddr );
+extern uint32 __inpdw_extern ( uint32 nAddr );
+extern void __outp_extern ( uint32 nAddr, uint8 nData );
+extern void __outpw_extern ( uint32 nAddr, uint16 nData );
+extern void __outpdw_extern ( uint32 nAddr, uint32 nData );
+
+#endif
+
+#define in_byte(addr) (__inp(addr))
+#define in_byte_masked(addr, mask) (__inp(addr) & (mask))
+#define out_byte(addr, val) __outp(addr,val)
+#define out_byte_masked(io, mask, val, shadow) \
+ HWIO_INTLOCK(); \
+ out_byte( io, shadow); \
+ shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
+ HWIO_INTFREE()
+#define out_byte_masked_ns(io, mask, val, current_reg_content) \
+ out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \
+ ((uint16)((val) & (mask)))) )
+
+#define in_word(addr) (__inpw(addr))
+#define in_word_masked(addr, mask) (__inpw(addr) & (mask))
+#define out_word(addr, val) __outpw(addr,val)
+#define out_word_masked(io, mask, val, shadow) \
+ HWIO_INTLOCK( ); \
+ shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
+ out_word( io, shadow); \
+ HWIO_INTFREE( )
+#define out_word_masked_ns(io, mask, val, current_reg_content) \
+ out_word( io, ((current_reg_content & (uint16)(~(mask))) | \
+ ((uint16)((val) & (mask)))) )
+
+#define in_dword(addr) (__inpdw(addr))
+#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
+#define out_dword(addr, val) __outpdw(addr,val)
+#define out_dword_masked(io, mask, val, shadow) \
+ HWIO_INTLOCK(); \
+ shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \
+ out_dword( io, shadow); \
+ HWIO_INTFREE()
+#define out_dword_masked_ns(io, mask, val, current_reg_content) \
+ out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \
+ ((uint32)((val) & (mask)))) )
+
+#endif
+
diff --git a/hw/wcn6450/v1/buffer_addr_info.h b/hw/wcn6450/v1/buffer_addr_info.h
new file mode 100644
index 0000000..1c8adb5
--- /dev/null
+++ b/hw/wcn6450/v1/buffer_addr_info.h
@@ -0,0 +1,52 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _BUFFER_ADDR_INFO_H_
+#define _BUFFER_ADDR_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
+
+struct buffer_addr_info {
+ uint32_t buffer_addr_31_0 : 32;
+ uint32_t buffer_addr_39_32 : 8,
+ return_buffer_manager : 3,
+ sw_buffer_cookie : 21;
+};
+
+#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0
+#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0
+#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 8
+#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 11
+#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#endif
diff --git a/hw/wcn6450/v1/ce_src_desc.h b/hw/wcn6450/v1/ce_src_desc.h
new file mode 100644
index 0000000..6563dad
--- /dev/null
+++ b/hw/wcn6450/v1/ce_src_desc.h
@@ -0,0 +1,97 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _CE_SRC_DESC_H_
+#define _CE_SRC_DESC_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_CE_SRC_DESC 4
+
+struct ce_src_desc {
+ uint32_t src_buffer_low : 32;
+ uint32_t src_buffer_high : 8,
+ toeplitz_en : 1,
+ src_swap : 1,
+ dest_swap : 1,
+ gather : 1,
+ ce_res_0 : 4,
+ length : 16;
+ uint32_t fw_metadata : 16,
+ ce_res_1 : 16;
+ uint32_t ce_res_2 : 20,
+ ring_id : 8,
+ looping_count : 4;
+};
+
+#define CE_SRC_DESC_0_SRC_BUFFER_LOW_OFFSET 0x00000000
+#define CE_SRC_DESC_0_SRC_BUFFER_LOW_LSB 0
+#define CE_SRC_DESC_0_SRC_BUFFER_LOW_MASK 0xffffffff
+
+#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_OFFSET 0x00000004
+#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_LSB 0
+#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_MASK 0x000000ff
+
+#define CE_SRC_DESC_1_TOEPLITZ_EN_OFFSET 0x00000004
+#define CE_SRC_DESC_1_TOEPLITZ_EN_LSB 8
+#define CE_SRC_DESC_1_TOEPLITZ_EN_MASK 0x00000100
+
+#define CE_SRC_DESC_1_SRC_SWAP_OFFSET 0x00000004
+#define CE_SRC_DESC_1_SRC_SWAP_LSB 9
+#define CE_SRC_DESC_1_SRC_SWAP_MASK 0x00000200
+
+#define CE_SRC_DESC_1_DEST_SWAP_OFFSET 0x00000004
+#define CE_SRC_DESC_1_DEST_SWAP_LSB 10
+#define CE_SRC_DESC_1_DEST_SWAP_MASK 0x00000400
+
+#define CE_SRC_DESC_1_GATHER_OFFSET 0x00000004
+#define CE_SRC_DESC_1_GATHER_LSB 11
+#define CE_SRC_DESC_1_GATHER_MASK 0x00000800
+
+#define CE_SRC_DESC_1_CE_RES_0_OFFSET 0x00000004
+#define CE_SRC_DESC_1_CE_RES_0_LSB 12
+#define CE_SRC_DESC_1_CE_RES_0_MASK 0x0000f000
+
+#define CE_SRC_DESC_1_LENGTH_OFFSET 0x00000004
+#define CE_SRC_DESC_1_LENGTH_LSB 16
+#define CE_SRC_DESC_1_LENGTH_MASK 0xffff0000
+
+#define CE_SRC_DESC_2_FW_METADATA_OFFSET 0x00000008
+#define CE_SRC_DESC_2_FW_METADATA_LSB 0
+#define CE_SRC_DESC_2_FW_METADATA_MASK 0x0000ffff
+
+#define CE_SRC_DESC_2_CE_RES_1_OFFSET 0x00000008
+#define CE_SRC_DESC_2_CE_RES_1_LSB 16
+#define CE_SRC_DESC_2_CE_RES_1_MASK 0xffff0000
+
+#define CE_SRC_DESC_3_CE_RES_2_OFFSET 0x0000000c
+#define CE_SRC_DESC_3_CE_RES_2_LSB 0
+#define CE_SRC_DESC_3_CE_RES_2_MASK 0x000fffff
+
+#define CE_SRC_DESC_3_RING_ID_OFFSET 0x0000000c
+#define CE_SRC_DESC_3_RING_ID_LSB 20
+#define CE_SRC_DESC_3_RING_ID_MASK 0x0ff00000
+
+#define CE_SRC_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c
+#define CE_SRC_DESC_3_LOOPING_COUNT_LSB 28
+#define CE_SRC_DESC_3_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/hw/wcn6450/v1/ce_stat_desc.h b/hw/wcn6450/v1/ce_stat_desc.h
new file mode 100644
index 0000000..7214806
--- /dev/null
+++ b/hw/wcn6450/v1/ce_stat_desc.h
@@ -0,0 +1,97 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _CE_STAT_DESC_H_
+#define _CE_STAT_DESC_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_CE_STAT_DESC 4
+
+struct ce_stat_desc {
+ uint32_t ce_res_5 : 8,
+ toeplitz_en : 1,
+ src_swap : 1,
+ dest_swap : 1,
+ gather : 1,
+ ce_res_6 : 4,
+ length : 16;
+ uint32_t toeplitz_hash_0 : 32;
+ uint32_t toeplitz_hash_1 : 32;
+ uint32_t fw_metadata : 16,
+ ce_res_7 : 4,
+ ring_id : 8,
+ looping_count : 4;
+};
+
+#define CE_STAT_DESC_0_CE_RES_5_OFFSET 0x00000000
+#define CE_STAT_DESC_0_CE_RES_5_LSB 0
+#define CE_STAT_DESC_0_CE_RES_5_MASK 0x000000ff
+
+#define CE_STAT_DESC_0_TOEPLITZ_EN_OFFSET 0x00000000
+#define CE_STAT_DESC_0_TOEPLITZ_EN_LSB 8
+#define CE_STAT_DESC_0_TOEPLITZ_EN_MASK 0x00000100
+
+#define CE_STAT_DESC_0_SRC_SWAP_OFFSET 0x00000000
+#define CE_STAT_DESC_0_SRC_SWAP_LSB 9
+#define CE_STAT_DESC_0_SRC_SWAP_MASK 0x00000200
+
+#define CE_STAT_DESC_0_DEST_SWAP_OFFSET 0x00000000
+#define CE_STAT_DESC_0_DEST_SWAP_LSB 10
+#define CE_STAT_DESC_0_DEST_SWAP_MASK 0x00000400
+
+#define CE_STAT_DESC_0_GATHER_OFFSET 0x00000000
+#define CE_STAT_DESC_0_GATHER_LSB 11
+#define CE_STAT_DESC_0_GATHER_MASK 0x00000800
+
+#define CE_STAT_DESC_0_CE_RES_6_OFFSET 0x00000000
+#define CE_STAT_DESC_0_CE_RES_6_LSB 12
+#define CE_STAT_DESC_0_CE_RES_6_MASK 0x0000f000
+
+#define CE_STAT_DESC_0_LENGTH_OFFSET 0x00000000
+#define CE_STAT_DESC_0_LENGTH_LSB 16
+#define CE_STAT_DESC_0_LENGTH_MASK 0xffff0000
+
+#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_OFFSET 0x00000004
+#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_LSB 0
+#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_MASK 0xffffffff
+
+#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_OFFSET 0x00000008
+#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_LSB 0
+#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_MASK 0xffffffff
+
+#define CE_STAT_DESC_3_FW_METADATA_OFFSET 0x0000000c
+#define CE_STAT_DESC_3_FW_METADATA_LSB 0
+#define CE_STAT_DESC_3_FW_METADATA_MASK 0x0000ffff
+
+#define CE_STAT_DESC_3_CE_RES_7_OFFSET 0x0000000c
+#define CE_STAT_DESC_3_CE_RES_7_LSB 16
+#define CE_STAT_DESC_3_CE_RES_7_MASK 0x000f0000
+
+#define CE_STAT_DESC_3_RING_ID_OFFSET 0x0000000c
+#define CE_STAT_DESC_3_RING_ID_LSB 20
+#define CE_STAT_DESC_3_RING_ID_MASK 0x0ff00000
+
+#define CE_STAT_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c
+#define CE_STAT_DESC_3_LOOPING_COUNT_LSB 28
+#define CE_STAT_DESC_3_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/hw/wcn6450/v1/com_dtypes.h b/hw/wcn6450/v1/com_dtypes.h
new file mode 100644
index 0000000..83c89f3
--- /dev/null
+++ b/hw/wcn6450/v1/com_dtypes.h
@@ -0,0 +1,182 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef COM_DTYPES_H
+#define COM_DTYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef T_WINNT
+ #ifndef WIN32
+ #define WIN32
+ #endif
+ #include <stdlib.h>
+#endif
+
+#ifdef TRUE
+#undef TRUE
+#endif
+
+#ifdef FALSE
+#undef FALSE
+#endif
+
+#define TRUE 1
+#define FALSE 0
+
+#define ON 1
+#define OFF 0
+
+#ifndef NULL
+ #define NULL 0
+#endif
+
+#ifndef _ARM_ASM_
+#ifndef _BOOLEAN_DEFINED
+
+typedef unsigned char boolean;
+#define _BOOLEAN_DEFINED
+#endif
+
+#if defined(DALSTDDEF_H)
+#define _BOOLEAN_DEFINED
+#define _UINT32_DEFINED
+#define _UINT16_DEFINED
+#define _UINT8_DEFINED
+#define _INT32_DEFINED
+#define _INT16_DEFINED
+#define _INT8_DEFINED
+#define _UINT64_DEFINED
+#define _INT64_DEFINED
+#define _BYTE_DEFINED
+#endif
+
+#ifndef _UINT32_DEFINED
+
+typedef unsigned long int uint32;
+#define _UINT32_DEFINED
+#endif
+
+#ifndef _UINT16_DEFINED
+
+typedef unsigned short uint16;
+#define _UINT16_DEFINED
+#endif
+
+#ifndef _UINT8_DEFINED
+
+typedef unsigned char uint8;
+#define _UINT8_DEFINED
+#endif
+
+#ifndef _INT32_DEFINED
+
+typedef signed long int int32;
+#define _INT32_DEFINED
+#endif
+
+#ifndef _INT16_DEFINED
+
+typedef signed short int16;
+#define _INT16_DEFINED
+#endif
+
+#ifndef _INT8_DEFINED
+
+typedef signed char int8;
+#define _INT8_DEFINED
+#endif
+
+#ifndef _BYTE_DEFINED
+
+typedef unsigned char byte;
+#define _BYTE_DEFINED
+#endif
+
+typedef unsigned short word;
+
+typedef unsigned long dword;
+
+typedef unsigned char uint1;
+
+typedef unsigned short uint2;
+
+typedef unsigned long uint4;
+
+typedef signed char int1;
+
+typedef signed short int2;
+
+typedef long int int4;
+
+typedef signed long sint31;
+
+typedef signed short sint15;
+
+typedef signed char sint7;
+
+typedef uint16 UWord16 ;
+typedef uint32 UWord32 ;
+typedef int32 Word32 ;
+typedef int16 Word16 ;
+typedef uint8 UWord8 ;
+typedef int8 Word8 ;
+typedef int32 Vect32 ;
+
+#if (! defined T_WINNT) && (! defined __GNUC__)
+
+ #ifndef _INT64_DEFINED
+
+ typedef long long int64;
+ #define _INT64_DEFINED
+ #endif
+ #ifndef _UINT64_DEFINED
+
+ typedef unsigned long long uint64;
+ #define _UINT64_DEFINED
+ #endif
+#else
+
+ #if (defined __GNUC__)
+ #ifndef _INT64_DEFINED
+ typedef long long int64;
+ #define _INT64_DEFINED
+ #endif
+ #ifndef _UINT64_DEFINED
+ typedef unsigned long long uint64;
+ #define _UINT64_DEFINED
+ #endif
+ #else
+ typedef __int64 int64;
+ #ifndef _UINT64_DEFINED
+ typedef unsigned __int64 uint64;
+ #define _UINT64_DEFINED
+ #endif
+ #endif
+#endif
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/wcn6450/v1/he_sig_a_mu_dl_info.h b/hw/wcn6450/v1/he_sig_a_mu_dl_info.h
new file mode 100644
index 0000000..85ffe97
--- /dev/null
+++ b/hw/wcn6450/v1/he_sig_a_mu_dl_info.h
@@ -0,0 +1,137 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HE_SIG_A_MU_DL_INFO_H_
+#define _HE_SIG_A_MU_DL_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2
+
+struct he_sig_a_mu_dl_info {
+ uint32_t dl_ul_flag : 1,
+ mcs_of_sig_b : 3,
+ dcm_of_sig_b : 1,
+ bss_color_id : 6,
+ spatial_reuse : 4,
+ transmit_bw : 3,
+ num_sig_b_symbols : 4,
+ comp_mode_sig_b : 1,
+ cp_ltf_size : 2,
+ doppler_indication : 1,
+ reserved_0a : 6;
+ uint32_t txop_duration : 7,
+ reserved_1a : 1,
+ num_ltf_symbols : 3,
+ ldpc_extra_symbol : 1,
+ stbc : 1,
+ packet_extension_a_factor : 2,
+ packet_extension_pe_disambiguity: 1,
+ crc : 4,
+ tail : 6,
+ reserved_1b : 6;
+};
+
+#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_LSB 0
+#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_MASK 0x00000001
+
+#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_LSB 1
+#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_MASK 0x0000000e
+
+#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_LSB 4
+#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_MASK 0x00000010
+
+#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_LSB 5
+#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_MASK 0x000007e0
+
+#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_LSB 11
+#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_MASK 0x00007800
+
+#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_LSB 15
+#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_MASK 0x00038000
+
+#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_LSB 18
+#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
+
+#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_LSB 22
+#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_MASK 0x00400000
+
+#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_LSB 23
+#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_MASK 0x01800000
+
+#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_LSB 25
+#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_MASK 0x02000000
+
+#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_LSB 26
+#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_MASK 0xfc000000
+
+#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_LSB 0
+#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_MASK 0x0000007f
+
+#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_LSB 7
+#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_MASK 0x00000080
+
+#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_LSB 8
+#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_MASK 0x00000700
+
+#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_LSB 11
+#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000800
+
+#define HE_SIG_A_MU_DL_INFO_1_STBC_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_STBC_LSB 12
+#define HE_SIG_A_MU_DL_INFO_1_STBC_MASK 0x00001000
+
+#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_LSB 13
+#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
+
+#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
+#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
+
+#define HE_SIG_A_MU_DL_INFO_1_CRC_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_CRC_LSB 16
+#define HE_SIG_A_MU_DL_INFO_1_CRC_MASK 0x000f0000
+
+#define HE_SIG_A_MU_DL_INFO_1_TAIL_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_TAIL_LSB 20
+#define HE_SIG_A_MU_DL_INFO_1_TAIL_MASK 0x03f00000
+
+#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_LSB 26
+#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_MASK 0xfc000000
+
+#endif
diff --git a/hw/wcn6450/v1/he_sig_a_mu_ul_info.h b/hw/wcn6450/v1/he_sig_a_mu_ul_info.h
new file mode 100644
index 0000000..0e8230e
--- /dev/null
+++ b/hw/wcn6450/v1/he_sig_a_mu_ul_info.h
@@ -0,0 +1,87 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HE_SIG_A_MU_UL_INFO_H_
+#define _HE_SIG_A_MU_UL_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2
+
+struct he_sig_a_mu_ul_info {
+ uint32_t format_indication : 1,
+ bss_color_id : 6,
+ spatial_reuse : 16,
+ reserved_0a : 1,
+ transmit_bw : 2,
+ reserved_0b : 6;
+ uint32_t txop_duration : 7,
+ reserved_1a : 9,
+ crc : 4,
+ tail : 6,
+ reserved_1b : 6;
+};
+
+#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_OFFSET 0x00000000
+#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_LSB 0
+#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_MASK 0x00000001
+
+#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000
+#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_LSB 1
+#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_MASK 0x0000007e
+
+#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000
+#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_LSB 7
+#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_MASK 0x007fff80
+
+#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_OFFSET 0x00000000
+#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_LSB 23
+#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_MASK 0x00800000
+
+#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_OFFSET 0x00000000
+#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_LSB 24
+#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_MASK 0x03000000
+
+#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_OFFSET 0x00000000
+#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_LSB 26
+#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_MASK 0xfc000000
+
+#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_OFFSET 0x00000004
+#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_LSB 0
+#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_MASK 0x0000007f
+
+#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_OFFSET 0x00000004
+#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_LSB 7
+#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_MASK 0x0000ff80
+
+#define HE_SIG_A_MU_UL_INFO_1_CRC_OFFSET 0x00000004
+#define HE_SIG_A_MU_UL_INFO_1_CRC_LSB 16
+#define HE_SIG_A_MU_UL_INFO_1_CRC_MASK 0x000f0000
+
+#define HE_SIG_A_MU_UL_INFO_1_TAIL_OFFSET 0x00000004
+#define HE_SIG_A_MU_UL_INFO_1_TAIL_LSB 20
+#define HE_SIG_A_MU_UL_INFO_1_TAIL_MASK 0x03f00000
+
+#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_OFFSET 0x00000004
+#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_LSB 26
+#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_MASK 0xfc000000
+
+#endif
diff --git a/hw/wcn6450/v1/he_sig_a_su_info.h b/hw/wcn6450/v1/he_sig_a_su_info.h
new file mode 100644
index 0000000..72f6e85
--- /dev/null
+++ b/hw/wcn6450/v1/he_sig_a_su_info.h
@@ -0,0 +1,162 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HE_SIG_A_SU_INFO_H_
+#define _HE_SIG_A_SU_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2
+
+struct he_sig_a_su_info {
+ uint32_t format_indication : 1,
+ beam_change : 1,
+ dl_ul_flag : 1,
+ transmit_mcs : 4,
+ dcm : 1,
+ bss_color_id : 6,
+ reserved_0a : 1,
+ spatial_reuse : 4,
+ transmit_bw : 2,
+ cp_ltf_size : 2,
+ nsts : 3,
+ reserved_0b : 6;
+ uint32_t txop_duration : 7,
+ coding : 1,
+ ldpc_extra_symbol : 1,
+ stbc : 1,
+ txbf : 1,
+ packet_extension_a_factor : 2,
+ packet_extension_pe_disambiguity: 1,
+ reserved_1a : 1,
+ doppler_indication : 1,
+ crc : 4,
+ tail : 6,
+ dot11ax_su_extended : 1,
+ dot11ax_ext_ru_size : 4,
+ rx_ndp : 1;
+};
+
+#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_LSB 0
+#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_MASK 0x00000001
+
+#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_LSB 1
+#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_MASK 0x00000002
+
+#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_LSB 2
+#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_MASK 0x00000004
+
+#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_LSB 3
+#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_MASK 0x00000078
+
+#define HE_SIG_A_SU_INFO_0_DCM_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_DCM_LSB 7
+#define HE_SIG_A_SU_INFO_0_DCM_MASK 0x00000080
+
+#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_LSB 8
+#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_MASK 0x00003f00
+
+#define HE_SIG_A_SU_INFO_0_RESERVED_0A_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_RESERVED_0A_LSB 14
+#define HE_SIG_A_SU_INFO_0_RESERVED_0A_MASK 0x00004000
+
+#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_LSB 15
+#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_MASK 0x00078000
+
+#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_LSB 19
+#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_MASK 0x00180000
+
+#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_LSB 21
+#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_MASK 0x00600000
+
+#define HE_SIG_A_SU_INFO_0_NSTS_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_NSTS_LSB 23
+#define HE_SIG_A_SU_INFO_0_NSTS_MASK 0x03800000
+
+#define HE_SIG_A_SU_INFO_0_RESERVED_0B_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_RESERVED_0B_LSB 26
+#define HE_SIG_A_SU_INFO_0_RESERVED_0B_MASK 0xfc000000
+
+#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_LSB 0
+#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_MASK 0x0000007f
+
+#define HE_SIG_A_SU_INFO_1_CODING_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_CODING_LSB 7
+#define HE_SIG_A_SU_INFO_1_CODING_MASK 0x00000080
+
+#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_LSB 8
+#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000100
+
+#define HE_SIG_A_SU_INFO_1_STBC_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_STBC_LSB 9
+#define HE_SIG_A_SU_INFO_1_STBC_MASK 0x00000200
+
+#define HE_SIG_A_SU_INFO_1_TXBF_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_TXBF_LSB 10
+#define HE_SIG_A_SU_INFO_1_TXBF_MASK 0x00000400
+
+#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_LSB 11
+#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
+
+#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
+#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
+
+#define HE_SIG_A_SU_INFO_1_RESERVED_1A_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_RESERVED_1A_LSB 14
+#define HE_SIG_A_SU_INFO_1_RESERVED_1A_MASK 0x00004000
+
+#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_LSB 15
+#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_MASK 0x00008000
+
+#define HE_SIG_A_SU_INFO_1_CRC_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_CRC_LSB 16
+#define HE_SIG_A_SU_INFO_1_CRC_MASK 0x000f0000
+
+#define HE_SIG_A_SU_INFO_1_TAIL_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_TAIL_LSB 20
+#define HE_SIG_A_SU_INFO_1_TAIL_MASK 0x03f00000
+
+#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_LSB 26
+#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_MASK 0x04000000
+
+#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_LSB 27
+#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_MASK 0x78000000
+
+#define HE_SIG_A_SU_INFO_1_RX_NDP_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_RX_NDP_LSB 31
+#define HE_SIG_A_SU_INFO_1_RX_NDP_MASK 0x80000000
+
+#endif
diff --git a/hw/wcn6450/v1/he_sig_b1_mu_info.h b/hw/wcn6450/v1/he_sig_b1_mu_info.h
new file mode 100644
index 0000000..8a077e7
--- /dev/null
+++ b/hw/wcn6450/v1/he_sig_b1_mu_info.h
@@ -0,0 +1,42 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HE_SIG_B1_MU_INFO_H_
+#define _HE_SIG_B1_MU_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1
+
+struct he_sig_b1_mu_info {
+ uint32_t ru_allocation : 8,
+ reserved_0 : 24;
+};
+
+#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_OFFSET 0x00000000
+#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_LSB 0
+#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_MASK 0x000000ff
+
+#define HE_SIG_B1_MU_INFO_0_RESERVED_0_OFFSET 0x00000000
+#define HE_SIG_B1_MU_INFO_0_RESERVED_0_LSB 8
+#define HE_SIG_B1_MU_INFO_0_RESERVED_0_MASK 0xffffff00
+
+#endif
diff --git a/hw/wcn6450/v1/he_sig_b2_mu_info.h b/hw/wcn6450/v1/he_sig_b2_mu_info.h
new file mode 100644
index 0000000..ca97877
--- /dev/null
+++ b/hw/wcn6450/v1/he_sig_b2_mu_info.h
@@ -0,0 +1,67 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HE_SIG_B2_MU_INFO_H_
+#define _HE_SIG_B2_MU_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 1
+
+struct he_sig_b2_mu_info {
+ uint32_t sta_id : 11,
+ sta_spatial_config : 4,
+ sta_mcs : 4,
+ reserved_set_to_1 : 1,
+ sta_coding : 1,
+ reserved_0a : 8,
+ nsts : 3;
+};
+
+#define HE_SIG_B2_MU_INFO_0_STA_ID_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_0_STA_ID_LSB 0
+#define HE_SIG_B2_MU_INFO_0_STA_ID_MASK 0x000007ff
+
+#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_LSB 11
+#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_MASK 0x00007800
+
+#define HE_SIG_B2_MU_INFO_0_STA_MCS_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_0_STA_MCS_LSB 15
+#define HE_SIG_B2_MU_INFO_0_STA_MCS_MASK 0x00078000
+
+#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_LSB 19
+#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_MASK 0x00080000
+
+#define HE_SIG_B2_MU_INFO_0_STA_CODING_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_0_STA_CODING_LSB 20
+#define HE_SIG_B2_MU_INFO_0_STA_CODING_MASK 0x00100000
+
+#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_LSB 21
+#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_MASK 0x1fe00000
+
+#define HE_SIG_B2_MU_INFO_0_NSTS_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_0_NSTS_LSB 29
+#define HE_SIG_B2_MU_INFO_0_NSTS_MASK 0xe0000000
+
+#endif
diff --git a/hw/wcn6450/v1/he_sig_b2_ofdma_info.h b/hw/wcn6450/v1/he_sig_b2_ofdma_info.h
new file mode 100644
index 0000000..6f6a838
--- /dev/null
+++ b/hw/wcn6450/v1/he_sig_b2_ofdma_info.h
@@ -0,0 +1,67 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HE_SIG_B2_OFDMA_INFO_H_
+#define _HE_SIG_B2_OFDMA_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 1
+
+struct he_sig_b2_ofdma_info {
+ uint32_t sta_id : 11,
+ nsts : 3,
+ txbf : 1,
+ sta_mcs : 4,
+ sta_dcm : 1,
+ sta_coding : 1,
+ reserved_0 : 11;
+};
+
+#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_LSB 0
+#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_MASK 0x000007ff
+
+#define HE_SIG_B2_OFDMA_INFO_0_NSTS_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_NSTS_LSB 11
+#define HE_SIG_B2_OFDMA_INFO_0_NSTS_MASK 0x00003800
+
+#define HE_SIG_B2_OFDMA_INFO_0_TXBF_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_TXBF_LSB 14
+#define HE_SIG_B2_OFDMA_INFO_0_TXBF_MASK 0x00004000
+
+#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_LSB 15
+#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_MASK 0x00078000
+
+#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_LSB 19
+#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_MASK 0x00080000
+
+#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_LSB 20
+#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_MASK 0x00100000
+
+#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_LSB 21
+#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_MASK 0xffe00000
+
+#endif
diff --git a/hw/wcn6450/v1/ht_sig_info.h b/hw/wcn6450/v1/ht_sig_info.h
new file mode 100644
index 0000000..2205a0c
--- /dev/null
+++ b/hw/wcn6450/v1/ht_sig_info.h
@@ -0,0 +1,107 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HT_SIG_INFO_H_
+#define _HT_SIG_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_HT_SIG_INFO 2
+
+struct ht_sig_info {
+ uint32_t mcs : 7,
+ cbw : 1,
+ length : 16,
+ reserved_0 : 8;
+ uint32_t smoothing : 1,
+ not_sounding : 1,
+ ht_reserved : 1,
+ aggregation : 1,
+ stbc : 2,
+ fec_coding : 1,
+ short_gi : 1,
+ num_ext_sp_str : 2,
+ crc : 8,
+ signal_tail : 6,
+ reserved_1 : 8;
+};
+
+#define HT_SIG_INFO_0_MCS_OFFSET 0x00000000
+#define HT_SIG_INFO_0_MCS_LSB 0
+#define HT_SIG_INFO_0_MCS_MASK 0x0000007f
+
+#define HT_SIG_INFO_0_CBW_OFFSET 0x00000000
+#define HT_SIG_INFO_0_CBW_LSB 7
+#define HT_SIG_INFO_0_CBW_MASK 0x00000080
+
+#define HT_SIG_INFO_0_LENGTH_OFFSET 0x00000000
+#define HT_SIG_INFO_0_LENGTH_LSB 8
+#define HT_SIG_INFO_0_LENGTH_MASK 0x00ffff00
+
+#define HT_SIG_INFO_0_RESERVED_0_OFFSET 0x00000000
+#define HT_SIG_INFO_0_RESERVED_0_LSB 24
+#define HT_SIG_INFO_0_RESERVED_0_MASK 0xff000000
+
+#define HT_SIG_INFO_1_SMOOTHING_OFFSET 0x00000004
+#define HT_SIG_INFO_1_SMOOTHING_LSB 0
+#define HT_SIG_INFO_1_SMOOTHING_MASK 0x00000001
+
+#define HT_SIG_INFO_1_NOT_SOUNDING_OFFSET 0x00000004
+#define HT_SIG_INFO_1_NOT_SOUNDING_LSB 1
+#define HT_SIG_INFO_1_NOT_SOUNDING_MASK 0x00000002
+
+#define HT_SIG_INFO_1_HT_RESERVED_OFFSET 0x00000004
+#define HT_SIG_INFO_1_HT_RESERVED_LSB 2
+#define HT_SIG_INFO_1_HT_RESERVED_MASK 0x00000004
+
+#define HT_SIG_INFO_1_AGGREGATION_OFFSET 0x00000004
+#define HT_SIG_INFO_1_AGGREGATION_LSB 3
+#define HT_SIG_INFO_1_AGGREGATION_MASK 0x00000008
+
+#define HT_SIG_INFO_1_STBC_OFFSET 0x00000004
+#define HT_SIG_INFO_1_STBC_LSB 4
+#define HT_SIG_INFO_1_STBC_MASK 0x00000030
+
+#define HT_SIG_INFO_1_FEC_CODING_OFFSET 0x00000004
+#define HT_SIG_INFO_1_FEC_CODING_LSB 6
+#define HT_SIG_INFO_1_FEC_CODING_MASK 0x00000040
+
+#define HT_SIG_INFO_1_SHORT_GI_OFFSET 0x00000004
+#define HT_SIG_INFO_1_SHORT_GI_LSB 7
+#define HT_SIG_INFO_1_SHORT_GI_MASK 0x00000080
+
+#define HT_SIG_INFO_1_NUM_EXT_SP_STR_OFFSET 0x00000004
+#define HT_SIG_INFO_1_NUM_EXT_SP_STR_LSB 8
+#define HT_SIG_INFO_1_NUM_EXT_SP_STR_MASK 0x00000300
+
+#define HT_SIG_INFO_1_CRC_OFFSET 0x00000004
+#define HT_SIG_INFO_1_CRC_LSB 10
+#define HT_SIG_INFO_1_CRC_MASK 0x0003fc00
+
+#define HT_SIG_INFO_1_SIGNAL_TAIL_OFFSET 0x00000004
+#define HT_SIG_INFO_1_SIGNAL_TAIL_LSB 18
+#define HT_SIG_INFO_1_SIGNAL_TAIL_MASK 0x00fc0000
+
+#define HT_SIG_INFO_1_RESERVED_1_OFFSET 0x00000004
+#define HT_SIG_INFO_1_RESERVED_1_LSB 24
+#define HT_SIG_INFO_1_RESERVED_1_MASK 0xff000000
+
+#endif
diff --git a/hw/wcn6450/v1/hwio.h b/hw/wcn6450/v1/hwio.h
new file mode 100644
index 0000000..f2498dd
--- /dev/null
+++ b/hw/wcn6450/v1/hwio.h
@@ -0,0 +1,1322 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef __HWIO_H__
+#define __HWIO_H__
+
+#define HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_TOP_BASE + 0x00000000)
+#define HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE_SIZE 0x1000
+#define HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE_USED 0x8c
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x0)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_BASE_ADDR_LOW_BMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_BASE_ADDR_LOW_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x4)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_RMSK 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_BASE_ADDR_HIGH_BMSK 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_BASE_ADDR_HIGH_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x8)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_START_OFFSET_BMSK 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_START_OFFSET_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_SIZE_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_SIZE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0xc)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_BASE_ADDR_LOW_BMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_BASE_ADDR_LOW_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x10)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_RMSK 0x3ff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_DESC_SKIP_DWORD_BMSK 0x300
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_DESC_SKIP_DWORD_SHFT 8
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_BASE_ADDR_HIGH_BMSK 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_BASE_ADDR_HIGH_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x14)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_START_OFFSET_BMSK 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_START_OFFSET_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_SIZE_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_SIZE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x18)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_RMSK 0x1ffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_TARGET_MSI_EN_BMSK 0x1000000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_TARGET_MSI_EN_SHFT 24
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_FW_EN_BMSK 0x800000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_FW_EN_SHFT 23
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_DEST_BMSK 0x400000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_DEST_SHFT 22
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_SRC_BMSK 0x200000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_SRC_SHFT 21
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_PREFETCH_EN_BMSK 0x100000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_PREFETCH_EN_SHFT 20
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IDX_UPD_EN_BMSK 0x80000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IDX_UPD_EN_SHFT 19
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DST_RING_BYTE_SWAP_EN_BMSK 0x40000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DST_RING_BYTE_SWAP_EN_SHFT 18
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_BMSK 0x20000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SHFT 17
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_HOST_MSI_EN_BMSK 0x10000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_HOST_MSI_EN_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DEST_MAX_LENGTH_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DEST_MAX_LENGTH_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x1c)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_RMSK 0xf
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_DST_AXI_MAX_LEN_BMSK 0xc
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_DST_AXI_MAX_LEN_SHFT 2
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_SRC_AXI_MAX_LEN_BMSK 0x3
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_SRC_AXI_MAX_LEN_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x20)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_RMSK 0xf
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_STATUS_BMSK 0x8
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_STATUS_SHFT 3
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_DST_FLUSH_BMSK 0x4
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_DST_FLUSH_SHFT 2
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_SRC_FLUSH_BMSK 0x2
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_SRC_FLUSH_SHFT 1
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_BMSK 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x24)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_RMSK 0x7f
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_TIMER_BATCH_BMSK 0x40
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_TIMER_BATCH_SHFT 6
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_TIMER_BATCH_BMSK 0x20
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_TIMER_BATCH_SHFT 5
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_LOW_WATERMARK_BMSK 0x10
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_LOW_WATERMARK_SHFT 4
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_HIGH_WATERMARK_SHFT 3
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_LOW_WATERMARK_SHFT 2
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_HIGH_WATERMARK_SHFT 1
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_COPY_COMPLETE_BMSK 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_COPY_COMPLETE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x28)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_RMSK 0x7f
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_TIMER_BATCH_BMSK 0x40
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_TIMER_BATCH_SHFT 6
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_TIMER_BATCH_BMSK 0x20
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_TIMER_BATCH_SHFT 5
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_LOW_WATERMARK_BMSK 0x10
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_LOW_WATERMARK_SHFT 4
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_HIGH_WATERMARK_SHFT 3
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_LOW_WATERMARK_SHFT 2
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_HIGH_WATERMARK_SHFT 1
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_COPY_COMPLETE_BMSK 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_COPY_COMPLETE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x2c)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_RMSK 0x7f
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_TIMER_BATCH_BMSK 0x40
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_TIMER_BATCH_SHFT 6
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_TIMER_BATCH_BMSK 0x20
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_TIMER_BATCH_SHFT 5
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_LOW_WATERMARK_BMSK 0x10
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_LOW_WATERMARK_SHFT 4
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_HIGH_WATERMARK_SHFT 3
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_LOW_WATERMARK_SHFT 2
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_HIGH_WATERMARK_SHFT 1
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_COPY_COMPLETE_BMSK 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_COPY_COMPLETE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x30)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_RMSK 0x7f
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_TIMER_BATCH_BMSK 0x40
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_TIMER_BATCH_SHFT 6
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_TIMER_BATCH_BMSK 0x20
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_TIMER_BATCH_SHFT 5
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_LOW_WATERMARK_BMSK 0x10
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_LOW_WATERMARK_SHFT 4
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_HIGH_WATERMARK_SHFT 3
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_LOW_WATERMARK_SHFT 2
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_HIGH_WATERMARK_SHFT 1
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_COPY_COMPLETE_BMSK 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_COPY_COMPLETE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x34)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_RMSK 0xfffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_PARSER_INT_BMSK 0xfc000
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_PARSER_INT_SHFT 14
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_RD_BMSK 0x2000
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_RD_SHFT 13
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_WR_BMSK 0x1000
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_WR_SHFT 12
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_RO_WR_BMSK 0x800
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_RO_WR_SHFT 11
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_TIMEOUT_ERR_BMSK 0x400
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_TIMEOUT_ERR_SHFT 10
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_ERR_BMSK 0x200
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_ERR_SHFT 9
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_LEN_ERR_BMSK 0x100
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_LEN_ERR_SHFT 8
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_MAX_LEN_VIO_BMSK 0x80
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_MAX_LEN_VIO_SHFT 7
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_OVERFLOW_BMSK 0x40
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_OVERFLOW_SHFT 6
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_OVERFLOW_BMSK 0x20
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_OVERFLOW_SHFT 5
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_LOW_WATERMARK_BMSK 0x10
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_LOW_WATERMARK_SHFT 4
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_HIGH_WATERMARK_SHFT 3
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_LOW_WATERMARK_SHFT 2
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_HIGH_WATERMARK_SHFT 1
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_COPY_COMPLETE_BMSK 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_COPY_COMPLETE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x38)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_RMSK 0xfffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_PARSER_INT_BMSK 0xfc000
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_PARSER_INT_SHFT 14
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_RD_BMSK 0x2000
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_RD_SHFT 13
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_WR_BMSK 0x1000
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_WR_SHFT 12
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_RO_WR_BMSK 0x800
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_RO_WR_SHFT 11
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_TIMEOUT_ERR_BMSK 0x400
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_TIMEOUT_ERR_SHFT 10
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_BUS_ERR_BMSK 0x200
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_BUS_ERR_SHFT 9
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_LEN_ERR_BMSK 0x100
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_LEN_ERR_SHFT 8
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_MAX_LEN_VIO_BMSK 0x80
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_MAX_LEN_VIO_SHFT 7
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_OVERFLOW_BMSK 0x40
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_OVERFLOW_SHFT 6
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_OVERFLOW_BMSK 0x20
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_OVERFLOW_SHFT 5
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_LOW_WATERMARK_BMSK 0x10
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_LOW_WATERMARK_SHFT 4
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_HIGH_WATERMARK_SHFT 3
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_LOW_WATERMARK_SHFT 2
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_HIGH_WATERMARK_SHFT 1
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_COPY_COMPLETE_BMSK 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_COPY_COMPLETE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x3c)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_RMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_SRC_WR_INDEX_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_SRC_WR_INDEX_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x40)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_RMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_DST_WR_INDEX_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_DST_WR_INDEX_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x44)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_RMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_CURRENT_SRRI_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_CURRENT_SRRI_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x48)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_RMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_CURRENT_DRRI_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_CURRENT_DRRI_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x4c)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_BMSK 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x50)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_BMSK 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x54)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_RMSK 0x7
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_BMSK 0x4
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_SHFT 2
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_BMSK 0x2
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_SHFT 1
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_PRIORITY_BMSK 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_PRIORITY_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x58)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x5c)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_RMSK 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x60)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_MSI_DATA_BMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_MSI_DATA_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x64)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_RMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x68)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_RMSK 0x3
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_BMSK 0x2
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_SHFT 1
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_BMSK 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x6c)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_STATUS_BMSK 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_STATUS_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_LIMIT_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_LIMIT_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x70)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_VALUE_BMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_VALUE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x74)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x78)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x7c)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x80)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x84)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x88)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_RMSK 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x8c)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_MSI_DATA_BMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_MSI_DATA_SHFT 0
+
+#define HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_TOP_BASE + 0x00001000)
+#define HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE_SIZE 0x1000
+#define HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE_USED 0x8c
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x0)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_BASE_ADDR_LOW_BMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_BASE_ADDR_LOW_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x4)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_RMSK 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_BASE_ADDR_HIGH_BMSK 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_BASE_ADDR_HIGH_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x8)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_START_OFFSET_BMSK 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_START_OFFSET_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_SIZE_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_SIZE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0xc)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_BASE_ADDR_LOW_BMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_BASE_ADDR_LOW_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x10)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_RMSK 0x3ff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_DESC_SKIP_DWORD_BMSK 0x300
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_DESC_SKIP_DWORD_SHFT 8
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_BASE_ADDR_HIGH_BMSK 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_BASE_ADDR_HIGH_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x14)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_START_OFFSET_BMSK 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_START_OFFSET_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_SIZE_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_SIZE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x18)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_RMSK 0x1ffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_TARGET_MSI_EN_BMSK 0x1000000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_TARGET_MSI_EN_SHFT 24
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_FW_EN_BMSK 0x800000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_FW_EN_SHFT 23
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_DEST_BMSK 0x400000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_DEST_SHFT 22
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_SRC_BMSK 0x200000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_SRC_SHFT 21
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_PREFETCH_EN_BMSK 0x100000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_PREFETCH_EN_SHFT 20
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IDX_UPD_EN_BMSK 0x80000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IDX_UPD_EN_SHFT 19
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DST_RING_BYTE_SWAP_EN_BMSK 0x40000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DST_RING_BYTE_SWAP_EN_SHFT 18
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_BMSK 0x20000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SHFT 17
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_HOST_MSI_EN_BMSK 0x10000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_HOST_MSI_EN_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DEST_MAX_LENGTH_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DEST_MAX_LENGTH_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x1c)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_RMSK 0xf
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_DST_AXI_MAX_LEN_BMSK 0xc
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_DST_AXI_MAX_LEN_SHFT 2
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_SRC_AXI_MAX_LEN_BMSK 0x3
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_SRC_AXI_MAX_LEN_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x20)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_RMSK 0xf
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_STATUS_BMSK 0x8
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_STATUS_SHFT 3
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_DST_FLUSH_BMSK 0x4
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_DST_FLUSH_SHFT 2
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_SRC_FLUSH_BMSK 0x2
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_SRC_FLUSH_SHFT 1
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_BMSK 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x24)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_RMSK 0x7f
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_TIMER_BATCH_BMSK 0x40
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_TIMER_BATCH_SHFT 6
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_TIMER_BATCH_BMSK 0x20
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_TIMER_BATCH_SHFT 5
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_LOW_WATERMARK_BMSK 0x10
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_LOW_WATERMARK_SHFT 4
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_HIGH_WATERMARK_SHFT 3
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_LOW_WATERMARK_SHFT 2
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_HIGH_WATERMARK_SHFT 1
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_COPY_COMPLETE_BMSK 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_COPY_COMPLETE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x28)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_RMSK 0x7f
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_TIMER_BATCH_BMSK 0x40
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_TIMER_BATCH_SHFT 6
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_TIMER_BATCH_BMSK 0x20
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_TIMER_BATCH_SHFT 5
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_LOW_WATERMARK_BMSK 0x10
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_LOW_WATERMARK_SHFT 4
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_HIGH_WATERMARK_SHFT 3
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_LOW_WATERMARK_SHFT 2
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_HIGH_WATERMARK_SHFT 1
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_COPY_COMPLETE_BMSK 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_COPY_COMPLETE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x2c)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_RMSK 0x7f
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_TIMER_BATCH_BMSK 0x40
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_TIMER_BATCH_SHFT 6
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_TIMER_BATCH_BMSK 0x20
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_TIMER_BATCH_SHFT 5
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_LOW_WATERMARK_BMSK 0x10
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_LOW_WATERMARK_SHFT 4
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_HIGH_WATERMARK_SHFT 3
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_LOW_WATERMARK_SHFT 2
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_HIGH_WATERMARK_SHFT 1
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_COPY_COMPLETE_BMSK 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_COPY_COMPLETE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x30)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_RMSK 0x7f
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_TIMER_BATCH_BMSK 0x40
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_TIMER_BATCH_SHFT 6
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_TIMER_BATCH_BMSK 0x20
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_TIMER_BATCH_SHFT 5
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_LOW_WATERMARK_BMSK 0x10
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_LOW_WATERMARK_SHFT 4
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_HIGH_WATERMARK_SHFT 3
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_LOW_WATERMARK_SHFT 2
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_HIGH_WATERMARK_SHFT 1
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_COPY_COMPLETE_BMSK 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_COPY_COMPLETE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x34)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_RMSK 0xfffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_PARSER_INT_BMSK 0xfc000
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_PARSER_INT_SHFT 14
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_RD_BMSK 0x2000
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_RD_SHFT 13
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_WR_BMSK 0x1000
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_WR_SHFT 12
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_RO_WR_BMSK 0x800
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_RO_WR_SHFT 11
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_TIMEOUT_ERR_BMSK 0x400
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_TIMEOUT_ERR_SHFT 10
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_ERR_BMSK 0x200
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_ERR_SHFT 9
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_LEN_ERR_BMSK 0x100
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_LEN_ERR_SHFT 8
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_MAX_LEN_VIO_BMSK 0x80
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_MAX_LEN_VIO_SHFT 7
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_OVERFLOW_BMSK 0x40
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_OVERFLOW_SHFT 6
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_OVERFLOW_BMSK 0x20
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_OVERFLOW_SHFT 5
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_LOW_WATERMARK_BMSK 0x10
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_LOW_WATERMARK_SHFT 4
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_HIGH_WATERMARK_SHFT 3
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_LOW_WATERMARK_SHFT 2
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_HIGH_WATERMARK_SHFT 1
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_COPY_COMPLETE_BMSK 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_COPY_COMPLETE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x38)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_RMSK 0xfffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_PARSER_INT_BMSK 0xfc000
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_PARSER_INT_SHFT 14
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_RD_BMSK 0x2000
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_RD_SHFT 13
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_WR_BMSK 0x1000
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_WR_SHFT 12
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_RO_WR_BMSK 0x800
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_RO_WR_SHFT 11
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_TIMEOUT_ERR_BMSK 0x400
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_TIMEOUT_ERR_SHFT 10
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_BUS_ERR_BMSK 0x200
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_BUS_ERR_SHFT 9
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_LEN_ERR_BMSK 0x100
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_LEN_ERR_SHFT 8
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_MAX_LEN_VIO_BMSK 0x80
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_MAX_LEN_VIO_SHFT 7
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_OVERFLOW_BMSK 0x40
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_OVERFLOW_SHFT 6
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_OVERFLOW_BMSK 0x20
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_OVERFLOW_SHFT 5
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_LOW_WATERMARK_BMSK 0x10
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_LOW_WATERMARK_SHFT 4
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_HIGH_WATERMARK_SHFT 3
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_LOW_WATERMARK_SHFT 2
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_HIGH_WATERMARK_SHFT 1
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_COPY_COMPLETE_BMSK 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_COPY_COMPLETE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x3c)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_RMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_SRC_WR_INDEX_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_SRC_WR_INDEX_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x40)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_RMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_DST_WR_INDEX_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_DST_WR_INDEX_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x44)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_RMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_CURRENT_SRRI_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_CURRENT_SRRI_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x48)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_RMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_CURRENT_DRRI_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_CURRENT_DRRI_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x4c)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_BMSK 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x50)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_BMSK 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x54)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_RMSK 0x7
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_BMSK 0x4
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_SHFT 2
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_BMSK 0x2
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_SHFT 1
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_PRIORITY_BMSK 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_PRIORITY_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x58)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x5c)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_RMSK 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x60)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_MSI_DATA_BMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_MSI_DATA_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x64)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_RMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x68)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_RMSK 0x3
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_BMSK 0x2
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_SHFT 1
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_BMSK 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x6c)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_STATUS_BMSK 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_STATUS_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_LIMIT_BMSK 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_LIMIT_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x70)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_VALUE_BMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_VALUE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x74)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x78)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x7c)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x80)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x84)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x88)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_RMSK 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x8c)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_MSI_DATA_BMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_MSI_DATA_SHFT 0
+
+#define HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE (HOST_SOC_WFSS_CE_REG_TOP_BASE + 0x00010000)
+#define HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE_SIZE 0x1000
+#define HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE_USED 0x10
+
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0x0)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_RMSK 0xfff000
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_HOST_BMSK 0xfff000
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_HOST_SHFT 12
+
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0x4)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_VAL_BMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_VAL_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0x8)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_RMSK 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_VAL_BMSK 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_VAL_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0xc)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_RMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_VAL_BMSK 0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_VAL_SHFT 0
+
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0x10)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_RMSK 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_IN \
+ in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_INM(m) \
+ in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_OUT(v) \
+ out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_VAL_BMSK 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_VAL_SHFT 0
+
+#endif
diff --git a/hw/wcn6450/v1/l_sig_a_info.h b/hw/wcn6450/v1/l_sig_a_info.h
new file mode 100644
index 0000000..c55cb46
--- /dev/null
+++ b/hw/wcn6450/v1/l_sig_a_info.h
@@ -0,0 +1,72 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _L_SIG_A_INFO_H_
+#define _L_SIG_A_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_L_SIG_A_INFO 1
+
+struct l_sig_a_info {
+ uint32_t rate : 4,
+ lsig_reserved : 1,
+ length : 12,
+ parity : 1,
+ tail : 6,
+ pkt_type : 4,
+ captured_implicit_sounding : 1,
+ reserved : 3;
+};
+
+#define L_SIG_A_INFO_0_RATE_OFFSET 0x00000000
+#define L_SIG_A_INFO_0_RATE_LSB 0
+#define L_SIG_A_INFO_0_RATE_MASK 0x0000000f
+
+#define L_SIG_A_INFO_0_LSIG_RESERVED_OFFSET 0x00000000
+#define L_SIG_A_INFO_0_LSIG_RESERVED_LSB 4
+#define L_SIG_A_INFO_0_LSIG_RESERVED_MASK 0x00000010
+
+#define L_SIG_A_INFO_0_LENGTH_OFFSET 0x00000000
+#define L_SIG_A_INFO_0_LENGTH_LSB 5
+#define L_SIG_A_INFO_0_LENGTH_MASK 0x0001ffe0
+
+#define L_SIG_A_INFO_0_PARITY_OFFSET 0x00000000
+#define L_SIG_A_INFO_0_PARITY_LSB 17
+#define L_SIG_A_INFO_0_PARITY_MASK 0x00020000
+
+#define L_SIG_A_INFO_0_TAIL_OFFSET 0x00000000
+#define L_SIG_A_INFO_0_TAIL_LSB 18
+#define L_SIG_A_INFO_0_TAIL_MASK 0x00fc0000
+
+#define L_SIG_A_INFO_0_PKT_TYPE_OFFSET 0x00000000
+#define L_SIG_A_INFO_0_PKT_TYPE_LSB 24
+#define L_SIG_A_INFO_0_PKT_TYPE_MASK 0x0f000000
+
+#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000
+#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_LSB 28
+#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000
+
+#define L_SIG_A_INFO_0_RESERVED_OFFSET 0x00000000
+#define L_SIG_A_INFO_0_RESERVED_LSB 29
+#define L_SIG_A_INFO_0_RESERVED_MASK 0xe0000000
+
+#endif
diff --git a/hw/wcn6450/v1/l_sig_b_info.h b/hw/wcn6450/v1/l_sig_b_info.h
new file mode 100644
index 0000000..13d8420
--- /dev/null
+++ b/hw/wcn6450/v1/l_sig_b_info.h
@@ -0,0 +1,47 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _L_SIG_B_INFO_H_
+#define _L_SIG_B_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_L_SIG_B_INFO 1
+
+struct l_sig_b_info {
+ uint32_t rate : 4,
+ length : 12,
+ reserved : 16;
+};
+
+#define L_SIG_B_INFO_0_RATE_OFFSET 0x00000000
+#define L_SIG_B_INFO_0_RATE_LSB 0
+#define L_SIG_B_INFO_0_RATE_MASK 0x0000000f
+
+#define L_SIG_B_INFO_0_LENGTH_OFFSET 0x00000000
+#define L_SIG_B_INFO_0_LENGTH_LSB 4
+#define L_SIG_B_INFO_0_LENGTH_MASK 0x0000fff0
+
+#define L_SIG_B_INFO_0_RESERVED_OFFSET 0x00000000
+#define L_SIG_B_INFO_0_RESERVED_LSB 16
+#define L_SIG_B_INFO_0_RESERVED_MASK 0xffff0000
+
+#endif
diff --git a/hw/wcn6450/v1/macrx_abort_request_info.h b/hw/wcn6450/v1/macrx_abort_request_info.h
new file mode 100644
index 0000000..d9b7185
--- /dev/null
+++ b/hw/wcn6450/v1/macrx_abort_request_info.h
@@ -0,0 +1,42 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _MACRX_ABORT_REQUEST_INFO_H_
+#define _MACRX_ABORT_REQUEST_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1
+
+struct macrx_abort_request_info {
+ uint16_t macrx_abort_reason : 8,
+ reserved_0 : 8;
+};
+
+#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_OFFSET 0x00000000
+#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_LSB 0
+#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_MASK 0x000000ff
+
+#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_OFFSET 0x00000000
+#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_LSB 8
+#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_MASK 0x0000ff00
+
+#endif
diff --git a/hw/wcn6450/v1/msmhwiobase.h b/hw/wcn6450/v1/msmhwiobase.h
new file mode 100644
index 0000000..5561998
--- /dev/null
+++ b/hw/wcn6450/v1/msmhwiobase.h
@@ -0,0 +1,27 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __MSMHWIOBASE_H__
+#define __MSMHWIOBASE_H__
+
+#define HOST_SOC_WFSS_CE_REG_TOP_BASE 0x1b80000
+#define HOST_SOC_WFSS_CE_REG_TOP_BASE_SIZE 0x0001c000
+#define HOST_SOC_WFSS_CE_REG_TOP_BASE_PHYS 0x01b80000
+
+#endif
diff --git a/hw/wcn6450/v1/phyrx_abort_request_info.h b/hw/wcn6450/v1/phyrx_abort_request_info.h
new file mode 100644
index 0000000..bf0cad1
--- /dev/null
+++ b/hw/wcn6450/v1/phyrx_abort_request_info.h
@@ -0,0 +1,57 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_ABORT_REQUEST_INFO_H_
+#define _PHYRX_ABORT_REQUEST_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1
+
+struct phyrx_abort_request_info {
+ uint32_t phyrx_abort_reason : 8,
+ phy_enters_nap_state : 1,
+ phy_enters_defer_state : 1,
+ reserved_0 : 6,
+ receive_duration : 16;
+};
+
+#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_LSB 0
+#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_MASK 0x000000ff
+
+#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_LSB 8
+#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_MASK 0x00000100
+
+#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_LSB 9
+#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_MASK 0x00000200
+
+#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_LSB 10
+#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_MASK 0x0000fc00
+
+#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_LSB 16
+#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_MASK 0xffff0000
+
+#endif
diff --git a/hw/wcn6450/v1/phyrx_common_user_info.h b/hw/wcn6450/v1/phyrx_common_user_info.h
new file mode 100644
index 0000000..ca0e568
--- /dev/null
+++ b/hw/wcn6450/v1/phyrx_common_user_info.h
@@ -0,0 +1,42 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_COMMON_USER_INFO_H_
+#define _PHYRX_COMMON_USER_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 1
+
+struct phyrx_common_user_info {
+ uint32_t receive_duration : 16,
+ reserved_0a : 16;
+};
+
+#define PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION_OFFSET 0x00000000
+#define PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION_LSB 0
+#define PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION_MASK 0x0000ffff
+
+#define PHYRX_COMMON_USER_INFO_0_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_COMMON_USER_INFO_0_RESERVED_0A_LSB 16
+#define PHYRX_COMMON_USER_INFO_0_RESERVED_0A_MASK 0xffff0000
+
+#endif
diff --git a/hw/wcn6450/v1/phyrx_he_sig_a_mu_dl.h b/hw/wcn6450/v1/phyrx_he_sig_a_mu_dl.h
new file mode 100644
index 0000000..e41b29a
--- /dev/null
+++ b/hw/wcn6450/v1/phyrx_he_sig_a_mu_dl.h
@@ -0,0 +1,119 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_HE_SIG_A_MU_DL_H_
+#define _PHYRX_HE_SIG_A_MU_DL_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "he_sig_a_mu_dl_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2
+
+struct phyrx_he_sig_a_mu_dl {
+ struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details;
+};
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000001
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x0000000e
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x00000010
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000007e0
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00007800
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x00038000
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x01800000
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0xfc000000
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 0
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 7
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x00000080
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 8
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 12
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x00001000
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 16
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f0000
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 20
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 26
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0xfc000000
+
+#endif
diff --git a/hw/wcn6450/v1/phyrx_he_sig_a_mu_ul.h b/hw/wcn6450/v1/phyrx_he_sig_a_mu_ul.h
new file mode 100644
index 0000000..98bae63
--- /dev/null
+++ b/hw/wcn6450/v1/phyrx_he_sig_a_mu_ul.h
@@ -0,0 +1,79 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_HE_SIG_A_MU_UL_H_
+#define _PHYRX_HE_SIG_A_MU_UL_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "he_sig_a_mu_ul_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2
+
+struct phyrx_he_sig_a_mu_ul {
+ struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details;
+};
+
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
+
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e
+
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80
+
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000
+
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000
+
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000
+
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
+
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80
+
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000
+
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0xfc000000
+
+#endif
diff --git a/hw/wcn6450/v1/phyrx_he_sig_a_su.h b/hw/wcn6450/v1/phyrx_he_sig_a_su.h
new file mode 100644
index 0000000..97ec727
--- /dev/null
+++ b/hw/wcn6450/v1/phyrx_he_sig_a_su.h
@@ -0,0 +1,139 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_HE_SIG_A_SU_H_
+#define _PHYRX_HE_SIG_A_SU_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "he_sig_a_su_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2
+
+struct phyrx_he_sig_a_su {
+ struct he_sig_a_su_info phyrx_he_sig_a_su_info_details;
+};
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x00000002
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000004
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x00000078
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x00000080
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00003f00
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x00004000
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00078000
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00180000
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x00600000
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x03800000
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 0
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 7
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x00000080
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 8
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000100
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 9
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x00000200
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 10
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x00000400
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 14
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x00004000
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 15
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x00008000
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 16
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f0000
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 20
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 27
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x78000000
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 31
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x80000000
+
+#endif
diff --git a/hw/wcn6450/v1/phyrx_he_sig_b1_mu.h b/hw/wcn6450/v1/phyrx_he_sig_b1_mu.h
new file mode 100644
index 0000000..6b4c32f
--- /dev/null
+++ b/hw/wcn6450/v1/phyrx_he_sig_b1_mu.h
@@ -0,0 +1,43 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_HE_SIG_B1_MU_H_
+#define _PHYRX_HE_SIG_B1_MU_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "he_sig_b1_mu_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 1
+
+struct phyrx_he_sig_b1_mu {
+ struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details;
+};
+
+#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0
+#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x000000ff
+
+#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8
+#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0xffffff00
+
+#endif
diff --git a/hw/wcn6450/v1/phyrx_he_sig_b2_mu.h b/hw/wcn6450/v1/phyrx_he_sig_b2_mu.h
new file mode 100644
index 0000000..c641efc
--- /dev/null
+++ b/hw/wcn6450/v1/phyrx_he_sig_b2_mu.h
@@ -0,0 +1,63 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_HE_SIG_B2_MU_H_
+#define _PHYRX_HE_SIG_B2_MU_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "he_sig_b2_mu_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 1
+
+struct phyrx_he_sig_b2_mu {
+ struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details;
+};
+
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x000007ff
+
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00007800
+
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x00078000
+
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x00080000
+
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x00100000
+
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x1fe00000
+
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 29
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0xe0000000
+
+#endif
diff --git a/hw/wcn6450/v1/phyrx_he_sig_b2_ofdma.h b/hw/wcn6450/v1/phyrx_he_sig_b2_ofdma.h
new file mode 100644
index 0000000..08b9f51
--- /dev/null
+++ b/hw/wcn6450/v1/phyrx_he_sig_b2_ofdma.h
@@ -0,0 +1,63 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_
+#define _PHYRX_HE_SIG_B2_OFDMA_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "he_sig_b2_ofdma_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 1
+
+struct phyrx_he_sig_b2_ofdma {
+ struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details;
+};
+
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff
+
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x00003800
+
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x00004000
+
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00078000
+
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x00080000
+
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00100000
+
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0xffe00000
+
+#endif
diff --git a/hw/wcn6450/v1/phyrx_ht_sig.h b/hw/wcn6450/v1/phyrx_ht_sig.h
new file mode 100644
index 0000000..2677b0b
--- /dev/null
+++ b/hw/wcn6450/v1/phyrx_ht_sig.h
@@ -0,0 +1,95 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_HT_SIG_H_
+#define _PHYRX_HT_SIG_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "ht_sig_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_HT_SIG 2
+
+struct phyrx_ht_sig {
+ struct ht_sig_info phyrx_ht_sig_info_details;
+};
+
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x00000000
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x0000007f
+
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x00000000
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x00000080
+
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x00ffff00
+
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0xff000000
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 0
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x00000001
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 1
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x00000002
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 2
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x00000004
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 3
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x00000008
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 4
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x00000030
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 6
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x00000040
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 7
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x00000080
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 8
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x00000300
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 10
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc00
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 18
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc0000
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 24
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0xff000000
+
+#endif
diff --git a/hw/wcn6450/v1/phyrx_l_sig_a.h b/hw/wcn6450/v1/phyrx_l_sig_a.h
new file mode 100644
index 0000000..568c80c
--- /dev/null
+++ b/hw/wcn6450/v1/phyrx_l_sig_a.h
@@ -0,0 +1,67 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_L_SIG_A_H_
+#define _PHYRX_L_SIG_A_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "l_sig_a_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_L_SIG_A 1
+
+struct phyrx_l_sig_a {
+ struct l_sig_a_info phyrx_l_sig_a_info_details;
+};
+
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x0000000f
+
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x00000010
+
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x0001ffe0
+
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x00020000
+
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000
+
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000
+
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000
+
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0xe0000000
+
+#endif
diff --git a/hw/wcn6450/v1/phyrx_l_sig_b.h b/hw/wcn6450/v1/phyrx_l_sig_b.h
new file mode 100644
index 0000000..37e0e4b
--- /dev/null
+++ b/hw/wcn6450/v1/phyrx_l_sig_b.h
@@ -0,0 +1,47 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_L_SIG_B_H_
+#define _PHYRX_L_SIG_B_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "l_sig_b_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_L_SIG_B 1
+
+struct phyrx_l_sig_b {
+ struct l_sig_b_info phyrx_l_sig_b_info_details;
+};
+
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x00000000
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x0000000f
+
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x0000fff0
+
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x00000000
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0xffff0000
+
+#endif
diff --git a/hw/wcn6450/v1/phyrx_other_receive_info_ru_details.h b/hw/wcn6450/v1/phyrx_other_receive_info_ru_details.h
new file mode 100644
index 0000000..54a54dd
--- /dev/null
+++ b/hw/wcn6450/v1/phyrx_other_receive_info_ru_details.h
@@ -0,0 +1,47 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
+#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 3
+
+struct phyrx_other_receive_info_ru_details {
+ uint32_t ru_details_channel_0 : 32;
+ uint32_t ru_details_channel_1 : 32;
+ uint32_t spare : 32;
+};
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0_OFFSET 0x00000000
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0_MASK 0xffffffff
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1_OFFSET 0x00000004
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1_MASK 0xffffffff
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE_OFFSET 0x00000008
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/phyrx_pkt_end.h b/hw/wcn6450/v1/phyrx_pkt_end.h
new file mode 100644
index 0000000..1a86068
--- /dev/null
+++ b/hw/wcn6450/v1/phyrx_pkt_end.h
@@ -0,0 +1,503 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_PKT_END_H_
+#define _PHYRX_PKT_END_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "phyrx_pkt_end_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_PKT_END 33
+
+struct phyrx_pkt_end {
+ struct phyrx_pkt_end_info rx_pkt_end_details;
+};
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x00000002
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x00000004
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x00000008
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_LSB 4
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_LSB 6
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x00000fc0
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_LSB 12
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_MASK 0x00001000
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_LSB 13
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_LSB 20
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_MASK 0x07f00000
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_LSB 27
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0xf8000000
+
+#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004
+#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0
+#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008
+#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0
+#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c
+#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0
+#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010
+#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0
+#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014
+#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0
+#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff
+
+#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014
+#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16
+#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000
+
+#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018
+#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0
+#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff
+
+#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018
+#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16
+#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000
+
+#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024
+#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0
+#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff
+
+#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028
+#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0
+#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff
+
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff
+
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000
+
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000
+
+#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030
+#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
+#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff
+
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000
+
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000
+
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000
+
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000
+
+#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038
+#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0
+#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
+
+#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038
+#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12
+#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000
+
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff
+
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000
+
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff
+
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000
+
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff
+
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000
+
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff
+
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000
+
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff
+
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000
+
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff
+
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000
+
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff
+
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000
+
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff
+
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000
+
+#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000007c
+#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0
+#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0xffffffff
+
+#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x00000080
+#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 0
+#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/phyrx_pkt_end_info.h b/hw/wcn6450/v1/phyrx_pkt_end_info.h
new file mode 100644
index 0000000..d71467a
--- /dev/null
+++ b/hw/wcn6450/v1/phyrx_pkt_end_info.h
@@ -0,0 +1,524 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_PKT_END_INFO_H_
+#define _PHYRX_PKT_END_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_location_info.h"
+#include "rx_timing_offset_info.h"
+#include "receive_rssi_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 33
+
+struct phyrx_pkt_end_info {
+ uint32_t __reserved_g_0001 : 1,
+ location_info_valid : 1,
+ timing_info_valid : 1,
+ rssi_info_valid : 1,
+ rx_frame_correction_needed : 1,
+ frameless_frame_received : 1,
+ reserved_0a : 6,
+ dl_ofdma_info_valid : 1,
+ dl_ofdma_ru_start_index : 7,
+ dl_ofdma_ru_width : 7,
+ reserved_0b : 5;
+ uint32_t phy_timestamp_1_lower_32 : 32;
+ uint32_t phy_timestamp_1_upper_32 : 32;
+ uint32_t phy_timestamp_2_lower_32 : 32;
+ uint32_t phy_timestamp_2_upper_32 : 32;
+ struct rx_location_info rx_location_info_details;
+ struct rx_timing_offset_info rx_timing_offset_info_details;
+ struct receive_rssi_info post_rssi_info_details;
+ uint32_t phy_sw_status_31_0 : 32;
+ uint32_t phy_sw_status_63_32 : 32;
+};
+
+#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_LSB 1
+#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_MASK 0x00000002
+
+#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_LSB 2
+#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_MASK 0x00000004
+
+#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_LSB 3
+#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_MASK 0x00000008
+
+#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_LSB 4
+#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010
+
+#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_LSB 5
+#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020
+
+#define PHYRX_PKT_END_INFO_0_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_RESERVED_0A_LSB 6
+#define PHYRX_PKT_END_INFO_0_RESERVED_0A_MASK 0x00000fc0
+
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_LSB 12
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_MASK 0x00001000
+
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_LSB 13
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000
+
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_LSB 20
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_MASK 0x07f00000
+
+#define PHYRX_PKT_END_INFO_0_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_RESERVED_0B_LSB 27
+#define PHYRX_PKT_END_INFO_0_RESERVED_0B_MASK 0xf8000000
+
+#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004
+#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_LSB 0
+#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008
+#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_LSB 0
+#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c
+#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_LSB 0
+#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010
+#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_LSB 0
+#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff
+
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000
+
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff
+
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000
+
+#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024
+#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0
+#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff
+
+#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028
+#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0
+#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff
+
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff
+
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000
+
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030
+#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
+#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff
+
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000
+
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000
+
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000
+
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000
+
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
+
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000
+
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_OFFSET 0x0000007c
+#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_LSB 0
+#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_MASK 0xffffffff
+
+#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_OFFSET 0x00000080
+#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_LSB 0
+#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/phyrx_rssi_legacy.h b/hw/wcn6450/v1/phyrx_rssi_legacy.h
new file mode 100644
index 0000000..f9732e3
--- /dev/null
+++ b/hw/wcn6450/v1/phyrx_rssi_legacy.h
@@ -0,0 +1,628 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_RSSI_LEGACY_H_
+#define _PHYRX_RSSI_LEGACY_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "receive_rssi_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 37
+
+struct phyrx_rssi_legacy {
+ uint32_t reception_type : 4,
+ rx_chain_mask_type : 1,
+ reserved_0 : 1,
+ receive_bandwidth : 2,
+ rx_chain_mask : 8,
+ phy_ppdu_id : 16;
+ uint32_t sw_phy_meta_data : 32;
+ uint32_t ppdu_start_timestamp : 32;
+ struct receive_rssi_info pre_rssi_info_details;
+ struct receive_rssi_info preamble_rssi_info_details;
+ uint32_t pre_rssi_comb : 8,
+ rssi_comb : 8,
+ normalized_pre_rssi_comb : 8,
+ normalized_rssi_comb : 8;
+ uint32_t rssi_comb_ppdu : 8,
+ rssi_db_to_dbm_offset : 8,
+ rssi_for_spatial_reuse : 8,
+ rssi_for_trigger_resp : 8;
+};
+
+#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_OFFSET 0x00000000
+#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_LSB 0
+#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_MASK 0x0000000f
+
+#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000
+#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_LSB 4
+#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_MASK 0x00000010
+
+#define PHYRX_RSSI_LEGACY_0_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_RSSI_LEGACY_0_RESERVED_0_LSB 5
+#define PHYRX_RSSI_LEGACY_0_RESERVED_0_MASK 0x00000020
+
+#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_OFFSET 0x00000000
+#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_LSB 6
+#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_MASK 0x000000c0
+
+#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_OFFSET 0x00000000
+#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_LSB 8
+#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_OFFSET 0x00000000
+#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_LSB 16
+#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_MASK 0xffff0000
+
+#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_OFFSET 0x00000004
+#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_LSB 0
+#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_MASK 0xffffffff
+
+#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_OFFSET 0x00000008
+#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_LSB 0
+#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_MASK 0xffffffff
+
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000c
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000c
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000c
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000c
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000010
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000010
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000010
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000010
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000014
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000014
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000014
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000014
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000018
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000018
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000018
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000018
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000001c
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000001c
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000001c
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000001c
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000020
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000020
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000020
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000020
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000024
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000024
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000024
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000024
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000028
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000028
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000028
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000028
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000002c
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000002c
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000002c
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000002c
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000030
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000030
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000030
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000030
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000034
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000034
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000034
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000034
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000038
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000038
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000038
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000038
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000003c
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000003c
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000003c
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000003c
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000040
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000040
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000040
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000040
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000044
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000044
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000044
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000044
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000048
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000048
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000048
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000048
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000004c
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000004c
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000004c
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000004c
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000050
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000050
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000050
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000050
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000054
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000054
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000054
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000054
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000058
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000058
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000058
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000058
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000005c
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000005c
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000005c
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000005c
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000060
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000060
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000060
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000060
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000068
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000068
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000068
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000068
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000006c
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000006c
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000006c
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000006c
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000070
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000070
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000070
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000070
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000078
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000078
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000078
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000078
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000007c
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000007c
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000007c
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000007c
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000080
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000080
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000080
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000080
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000088
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000088
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000088
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000088
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_OFFSET 0x0000008c
+#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_LSB 0
+#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_OFFSET 0x0000008c
+#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_LSB 8
+#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000008c
+#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_LSB 16
+#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_OFFSET 0x0000008c
+#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_LSB 24
+#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_OFFSET 0x00000090
+#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_LSB 0
+#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000090
+#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_LSB 8
+#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000090
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_LSB 16
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000090
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_LSB 24
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_MASK 0xff000000
+
+#endif
diff --git a/hw/wcn6450/v1/phyrx_user_info.h b/hw/wcn6450/v1/phyrx_user_info.h
new file mode 100644
index 0000000..2724759
--- /dev/null
+++ b/hw/wcn6450/v1/phyrx_user_info.h
@@ -0,0 +1,95 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_USER_INFO_H_
+#define _PHYRX_USER_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "receive_user_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_USER_INFO 3
+
+struct phyrx_user_info {
+ struct receive_user_info receive_user_info_details;
+};
+
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff
+
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000
+
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000
+
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000
+
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000
+
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f
+
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030
+
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 6
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000c0
+
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00
+
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_OFFSET 0x00000004
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_LSB 16
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_MASK 0x00ff0000
+
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_OFFSET 0x00000004
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_LSB 24
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_MASK 0x7f000000
+
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_LSB 31
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_MASK 0x80000000
+
+#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008
+#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 0
+#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00000001
+
+#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_OFFSET 0x00000008
+#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_LSB 1
+#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_MASK 0x000000fe
+
+#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008
+#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 8
+#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0xffffff00
+
+#endif
diff --git a/hw/wcn6450/v1/phyrx_vht_sig_a.h b/hw/wcn6450/v1/phyrx_vht_sig_a.h
new file mode 100644
index 0000000..b949024
--- /dev/null
+++ b/hw/wcn6450/v1/phyrx_vht_sig_a.h
@@ -0,0 +1,103 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_VHT_SIG_A_H_
+#define _PHYRX_VHT_SIG_A_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "vht_sig_a_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2
+
+struct phyrx_vht_sig_a {
+ struct vht_sig_a_info phyrx_vht_sig_a_info_details;
+};
+
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x00000003
+
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x00000004
+
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x00000008
+
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x000003f0
+
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x003ffc00
+
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x00400000
+
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x00800000
+
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0xff000000
+
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 0
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x00000003
+
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 2
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x00000004
+
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 3
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000008
+
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 4
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f0
+
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 8
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x00000100
+
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 9
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x00000200
+
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 10
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc00
+
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 18
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000
+
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 24
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0xff000000
+
+#endif
diff --git a/hw/wcn6450/v1/receive_rssi_info.h b/hw/wcn6450/v1/receive_rssi_info.h
new file mode 100644
index 0000000..3d3133b
--- /dev/null
+++ b/hw/wcn6450/v1/receive_rssi_info.h
@@ -0,0 +1,352 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RECEIVE_RSSI_INFO_H_
+#define _RECEIVE_RSSI_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16
+
+struct receive_rssi_info {
+ uint32_t rssi_pri20_chain0 : 8,
+ rssi_ext20_chain0 : 8,
+ rssi_ext40_low20_chain0 : 8,
+ rssi_ext40_high20_chain0 : 8;
+ uint32_t rssi_ext80_low20_chain0 : 8,
+ rssi_ext80_low_high20_chain0 : 8,
+ rssi_ext80_high_low20_chain0 : 8,
+ rssi_ext80_high20_chain0 : 8;
+ uint32_t rssi_pri20_chain1 : 8,
+ rssi_ext20_chain1 : 8,
+ rssi_ext40_low20_chain1 : 8,
+ rssi_ext40_high20_chain1 : 8;
+ uint32_t rssi_ext80_low20_chain1 : 8,
+ rssi_ext80_low_high20_chain1 : 8,
+ rssi_ext80_high_low20_chain1 : 8,
+ rssi_ext80_high20_chain1 : 8;
+ uint32_t rssi_pri20_chain2 : 8,
+ rssi_ext20_chain2 : 8,
+ rssi_ext40_low20_chain2 : 8,
+ rssi_ext40_high20_chain2 : 8;
+ uint32_t rssi_ext80_low20_chain2 : 8,
+ rssi_ext80_low_high20_chain2 : 8,
+ rssi_ext80_high_low20_chain2 : 8,
+ rssi_ext80_high20_chain2 : 8;
+ uint32_t rssi_pri20_chain3 : 8,
+ rssi_ext20_chain3 : 8,
+ rssi_ext40_low20_chain3 : 8,
+ rssi_ext40_high20_chain3 : 8;
+ uint32_t rssi_ext80_low20_chain3 : 8,
+ rssi_ext80_low_high20_chain3 : 8,
+ rssi_ext80_high_low20_chain3 : 8,
+ rssi_ext80_high20_chain3 : 8;
+ uint32_t rssi_pri20_chain4 : 8,
+ rssi_ext20_chain4 : 8,
+ rssi_ext40_low20_chain4 : 8,
+ rssi_ext40_high20_chain4 : 8;
+ uint32_t rssi_ext80_low20_chain4 : 8,
+ rssi_ext80_low_high20_chain4 : 8,
+ rssi_ext80_high_low20_chain4 : 8,
+ rssi_ext80_high20_chain4 : 8;
+ uint32_t rssi_pri20_chain5 : 8,
+ rssi_ext20_chain5 : 8,
+ rssi_ext40_low20_chain5 : 8,
+ rssi_ext40_high20_chain5 : 8;
+ uint32_t rssi_ext80_low20_chain5 : 8,
+ rssi_ext80_low_high20_chain5 : 8,
+ rssi_ext80_high_low20_chain5 : 8,
+ rssi_ext80_high20_chain5 : 8;
+ uint32_t rssi_pri20_chain6 : 8,
+ rssi_ext20_chain6 : 8,
+ rssi_ext40_low20_chain6 : 8,
+ rssi_ext40_high20_chain6 : 8;
+ uint32_t rssi_ext80_low20_chain6 : 8,
+ rssi_ext80_low_high20_chain6 : 8,
+ rssi_ext80_high_low20_chain6 : 8,
+ rssi_ext80_high20_chain6 : 8;
+ uint32_t rssi_pri20_chain7 : 8,
+ rssi_ext20_chain7 : 8,
+ rssi_ext40_low20_chain7 : 8,
+ rssi_ext40_high20_chain7 : 8;
+ uint32_t rssi_ext80_low20_chain7 : 8,
+ rssi_ext80_low_high20_chain7 : 8,
+ rssi_ext80_high_low20_chain7 : 8,
+ rssi_ext80_high20_chain7 : 8;
+};
+
+#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_OFFSET 0x00000000
+#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_LSB 0
+#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_OFFSET 0x00000000
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_LSB 8
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_OFFSET 0x00000008
+#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_LSB 0
+#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_OFFSET 0x00000008
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_LSB 8
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000008
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000008
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000c
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000c
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000c
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000c
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_OFFSET 0x00000010
+#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_LSB 0
+#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_OFFSET 0x00000010
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_LSB 8
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000010
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000010
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000014
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000014
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000014
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000014
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_OFFSET 0x00000018
+#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_LSB 0
+#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_OFFSET 0x00000018
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_LSB 8
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000018
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000018
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000001c
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000001c
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000001c
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000001c
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_OFFSET 0x00000020
+#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_LSB 0
+#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_OFFSET 0x00000020
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_LSB 8
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x00000020
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_LSB 16
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x00000020
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_LSB 24
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000024
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_LSB 0
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000024
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000024
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000024
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_LSB 24
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_OFFSET 0x00000028
+#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_LSB 0
+#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_OFFSET 0x00000028
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_LSB 8
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000028
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_LSB 16
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000028
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_LSB 24
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x0000002c
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_LSB 0
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x0000002c
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x0000002c
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x0000002c
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_LSB 24
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_OFFSET 0x00000030
+#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_LSB 0
+#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_OFFSET 0x00000030
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_LSB 8
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x00000030
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_LSB 16
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x00000030
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_LSB 24
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000034
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_LSB 0
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000034
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000034
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000034
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_LSB 24
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_OFFSET 0x00000038
+#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_LSB 0
+#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_OFFSET 0x00000038
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_LSB 8
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000038
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_LSB 16
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000038
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_LSB 24
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x0000003c
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_LSB 0
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x0000003c
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x0000003c
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x0000003c
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_LSB 24
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000
+
+#endif
diff --git a/hw/wcn6450/v1/receive_user_info.h b/hw/wcn6450/v1/receive_user_info.h
new file mode 100644
index 0000000..9b2eb60
--- /dev/null
+++ b/hw/wcn6450/v1/receive_user_info.h
@@ -0,0 +1,107 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RECEIVE_USER_INFO_H_
+#define _RECEIVE_USER_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RECEIVE_USER_INFO 3
+
+struct receive_user_info {
+ uint32_t phy_ppdu_id : 16,
+ user_rssi : 8,
+ pkt_type : 4,
+ stbc : 1,
+ reception_type : 3;
+ uint32_t rate_mcs : 4,
+ sgi : 2,
+ receive_bandwidth : 2,
+ mimo_ss_bitmap : 8,
+ ofdma_ru_allocation : 8,
+ ofdma_user_index : 7,
+ ofdma_content_channel : 1;
+ uint32_t ldpc : 1,
+ ru_width : 7,
+ reserved_2a : 24;
+};
+
+#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_OFFSET 0x00000000
+#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_LSB 0
+#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_MASK 0x0000ffff
+
+#define RECEIVE_USER_INFO_0_USER_RSSI_OFFSET 0x00000000
+#define RECEIVE_USER_INFO_0_USER_RSSI_LSB 16
+#define RECEIVE_USER_INFO_0_USER_RSSI_MASK 0x00ff0000
+
+#define RECEIVE_USER_INFO_0_PKT_TYPE_OFFSET 0x00000000
+#define RECEIVE_USER_INFO_0_PKT_TYPE_LSB 24
+#define RECEIVE_USER_INFO_0_PKT_TYPE_MASK 0x0f000000
+
+#define RECEIVE_USER_INFO_0_STBC_OFFSET 0x00000000
+#define RECEIVE_USER_INFO_0_STBC_LSB 28
+#define RECEIVE_USER_INFO_0_STBC_MASK 0x10000000
+
+#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_OFFSET 0x00000000
+#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_LSB 29
+#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_MASK 0xe0000000
+
+#define RECEIVE_USER_INFO_1_RATE_MCS_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_1_RATE_MCS_LSB 0
+#define RECEIVE_USER_INFO_1_RATE_MCS_MASK 0x0000000f
+
+#define RECEIVE_USER_INFO_1_SGI_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_1_SGI_LSB 4
+#define RECEIVE_USER_INFO_1_SGI_MASK 0x00000030
+
+#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_LSB 6
+#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_MASK 0x000000c0
+
+#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_LSB 8
+#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_MASK 0x0000ff00
+
+#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_LSB 16
+#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_MASK 0x00ff0000
+
+#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_LSB 24
+#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_MASK 0x7f000000
+
+#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_LSB 31
+#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_MASK 0x80000000
+
+#define RECEIVE_USER_INFO_2_LDPC_OFFSET 0x00000008
+#define RECEIVE_USER_INFO_2_LDPC_LSB 0
+#define RECEIVE_USER_INFO_2_LDPC_MASK 0x00000001
+
+#define RECEIVE_USER_INFO_2_RU_WIDTH_OFFSET 0x00000008
+#define RECEIVE_USER_INFO_2_RU_WIDTH_LSB 1
+#define RECEIVE_USER_INFO_2_RU_WIDTH_MASK 0x000000fe
+
+#define RECEIVE_USER_INFO_2_RESERVED_2A_OFFSET 0x00000008
+#define RECEIVE_USER_INFO_2_RESERVED_2A_LSB 8
+#define RECEIVE_USER_INFO_2_RESERVED_2A_MASK 0xffffff00
+
+#endif
diff --git a/hw/wcn6450/v1/reo_descriptor_threshold_reached_status.h b/hw/wcn6450/v1/reo_descriptor_threshold_reached_status.h
new file mode 100644
index 0000000..27f7972
--- /dev/null
+++ b/hw/wcn6450/v1/reo_descriptor_threshold_reached_status.h
@@ -0,0 +1,200 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
+#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 25
+
+struct reo_descriptor_threshold_reached_status {
+ struct uniform_reo_status_header status_header;
+ uint32_t threshold_index : 2,
+ reserved_2 : 30;
+ uint32_t link_descriptor_counter0 : 24,
+ reserved_3 : 8;
+ uint32_t link_descriptor_counter1 : 24,
+ reserved_4 : 8;
+ uint32_t link_descriptor_counter2 : 24,
+ reserved_5 : 8;
+ uint32_t link_descriptor_counter_sum : 26,
+ reserved_6 : 6;
+ uint32_t reserved_7 : 32;
+ uint32_t reserved_8 : 32;
+ uint32_t reserved_9a : 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15a : 32;
+ uint32_t reserved_16a : 32;
+ uint32_t reserved_17a : 32;
+ uint32_t reserved_18a : 32;
+ uint32_t reserved_19a : 32;
+ uint32_t reserved_20a : 32;
+ uint32_t reserved_21a : 32;
+ uint32_t reserved_22a : 32;
+ uint32_t reserved_23a : 32;
+ uint32_t reserved_24a : 28,
+ looping_count : 4;
+};
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_OFFSET 0x00000008
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_MASK 0x00000003
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_OFFSET 0x00000008
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_LSB 2
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_MASK 0xfffffffc
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_OFFSET 0x0000000c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_LSB 24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_MASK 0xff000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000010
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_OFFSET 0x00000010
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_LSB 24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_MASK 0xff000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000014
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_OFFSET 0x00000014
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_LSB 24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_MASK 0xff000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x00000018
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_OFFSET 0x00000018
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_LSB 26
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_MASK 0xfc000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_OFFSET 0x0000001c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_OFFSET 0x00000020
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_OFFSET 0x00000024
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_OFFSET 0x00000028
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_OFFSET 0x00000030
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_OFFSET 0x00000034
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_OFFSET 0x00000038
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_OFFSET 0x00000040
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_OFFSET 0x00000044
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_OFFSET 0x00000048
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_OFFSET 0x00000050
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_OFFSET 0x00000054
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_OFFSET 0x00000058
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_OFFSET 0x00000060
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_MASK 0x0fffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_LSB 28
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/hw/wcn6450/v1/reo_destination_ring.h b/hw/wcn6450/v1/reo_destination_ring.h
new file mode 100644
index 0000000..361b405
--- /dev/null
+++ b/hw/wcn6450/v1/reo_destination_ring.h
@@ -0,0 +1,301 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_DESTINATION_RING_H_
+#define _REO_DESTINATION_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+#include "rx_mpdu_desc_info.h"
+#include "rx_msdu_desc_info.h"
+
+#define NUM_OF_DWORDS_REO_DESTINATION_RING 16
+
+struct reo_destination_ring {
+ struct buffer_addr_info buf_or_link_desc_addr_info;
+ struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
+ struct rx_msdu_desc_info rx_msdu_desc_info_details;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32;
+ uint32_t rx_reo_queue_desc_addr_39_32 : 8,
+ reo_dest_buffer_type : 1,
+ reo_push_reason : 2,
+ reo_error_code : 5,
+ receive_queue_number : 16;
+ uint32_t soft_reorder_info_valid : 1,
+ reorder_opcode : 4,
+ reorder_slot_index : 8,
+ mpdu_fragment_number : 4,
+ captured_msdu_data_size : 4,
+ sw_exception : 1,
+ reserved_8a : 10;
+ uint32_t reo_destination_struct_signature: 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15 : 20,
+ ring_id : 8,
+ looping_count : 4;
+};
+
+#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000
+
+#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
+#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000014
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000014
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000
+
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000
+
+#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000018
+#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB 8
+#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK 0x00000100
+
+#define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB 9
+#define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK 0x00000600
+
+#define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB 11
+#define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK 0x0000f800
+
+#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB 16
+#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000
+
+#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET 0x00000020
+#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB 0
+#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK 0x00000001
+
+#define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET 0x00000020
+#define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB 1
+#define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK 0x0000001e
+
+#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET 0x00000020
+#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB 5
+#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK 0x00001fe0
+
+#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020
+#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_LSB 13
+#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_MASK 0x0001e000
+
+#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x00000020
+#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_LSB 17
+#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_MASK 0x001e0000
+
+#define REO_DESTINATION_RING_8_SW_EXCEPTION_OFFSET 0x00000020
+#define REO_DESTINATION_RING_8_SW_EXCEPTION_LSB 21
+#define REO_DESTINATION_RING_8_SW_EXCEPTION_MASK 0x00200000
+
+#define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_DESTINATION_RING_8_RESERVED_8A_LSB 22
+#define REO_DESTINATION_RING_8_RESERVED_8A_MASK 0xffc00000
+
+#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x00000024
+#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_LSB 0
+#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET 0x00000028
+#define REO_DESTINATION_RING_10_RESERVED_10A_LSB 0
+#define REO_DESTINATION_RING_10_RESERVED_10A_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET 0x0000002c
+#define REO_DESTINATION_RING_11_RESERVED_11A_LSB 0
+#define REO_DESTINATION_RING_11_RESERVED_11A_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET 0x00000030
+#define REO_DESTINATION_RING_12_RESERVED_12A_LSB 0
+#define REO_DESTINATION_RING_12_RESERVED_12A_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET 0x00000034
+#define REO_DESTINATION_RING_13_RESERVED_13A_LSB 0
+#define REO_DESTINATION_RING_13_RESERVED_13A_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET 0x00000038
+#define REO_DESTINATION_RING_14_RESERVED_14A_LSB 0
+#define REO_DESTINATION_RING_14_RESERVED_14A_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_15_RESERVED_15_OFFSET 0x0000003c
+#define REO_DESTINATION_RING_15_RESERVED_15_LSB 0
+#define REO_DESTINATION_RING_15_RESERVED_15_MASK 0x000fffff
+
+#define REO_DESTINATION_RING_15_RING_ID_OFFSET 0x0000003c
+#define REO_DESTINATION_RING_15_RING_ID_LSB 20
+#define REO_DESTINATION_RING_15_RING_ID_MASK 0x0ff00000
+
+#define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET 0x0000003c
+#define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 28
+#define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/hw/wcn6450/v1/reo_entrance_ring.h b/hw/wcn6450/v1/reo_entrance_ring.h
new file mode 100644
index 0000000..65bf3e4
--- /dev/null
+++ b/hw/wcn6450/v1/reo_entrance_ring.h
@@ -0,0 +1,201 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_ENTRANCE_RING_H_
+#define _REO_ENTRANCE_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_mpdu_details.h"
+
+#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
+
+struct reo_entrance_ring {
+ struct rx_mpdu_details reo_level_mpdu_frame_info;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32;
+ uint32_t rx_reo_queue_desc_addr_39_32 : 8,
+ rounded_mpdu_byte_count : 14,
+ reo_destination_indication : 5,
+ frameless_bar : 1,
+ reserved_5a : 4;
+ uint32_t rxdma_push_reason : 2,
+ rxdma_error_code : 5,
+ mpdu_fragment_number : 4,
+ sw_exception : 1,
+ sw_exception_mpdu_delink : 1,
+ sw_exception_destination_ring_valid: 1,
+ sw_exception_destination_ring : 5,
+ reserved_6a : 13;
+ uint32_t phy_ppdu_id : 16,
+ reserved_7a : 4,
+ ring_id : 8,
+ looping_count : 4;
+};
+
+#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000
+
+#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
+#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB 8
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00
+
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB 22
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK 0x07c00000
+
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB 27
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK 0x08000000
+
+#define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_5_RESERVED_5A_LSB 28
+#define REO_ENTRANCE_RING_5_RESERVED_5A_MASK 0xf0000000
+
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB 0
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003
+
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB 2
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c
+
+#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_LSB 7
+#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_MASK 0x00000780
+
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_LSB 11
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MASK 0x00000800
+
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_LSB 12
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000
+
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000
+
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_LSB 14
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000
+
+#define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_RESERVED_6A_LSB 19
+#define REO_ENTRANCE_RING_6_RESERVED_6A_MASK 0xfff80000
+
+#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_OFFSET 0x0000001c
+#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_LSB 0
+#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_MASK 0x0000ffff
+
+#define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_ENTRANCE_RING_7_RESERVED_7A_LSB 16
+#define REO_ENTRANCE_RING_7_RESERVED_7A_MASK 0x000f0000
+
+#define REO_ENTRANCE_RING_7_RING_ID_OFFSET 0x0000001c
+#define REO_ENTRANCE_RING_7_RING_ID_LSB 20
+#define REO_ENTRANCE_RING_7_RING_ID_MASK 0x0ff00000
+
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB 28
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/hw/wcn6450/v1/reo_flush_cache.h b/hw/wcn6450/v1/reo_flush_cache.h
new file mode 100644
index 0000000..56304c8
--- /dev/null
+++ b/hw/wcn6450/v1/reo_flush_cache.h
@@ -0,0 +1,122 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_FLUSH_CACHE_H_
+#define _REO_FLUSH_CACHE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+#define NUM_OF_DWORDS_REO_FLUSH_CACHE 9
+
+struct reo_flush_cache {
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t flush_addr_31_0 : 32;
+ uint32_t flush_addr_39_32 : 8,
+ forward_all_mpdus_in_queue : 1,
+ release_cache_block_index : 1,
+ cache_block_resource_index : 2,
+ flush_without_invalidate : 1,
+ block_cache_usage_after_flush : 1,
+ flush_entire_cache : 1,
+ reserved_2b : 17;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+};
+
+#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_LSB 17
+#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET 0x00000004
+#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB 0
+#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB 0
+#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK 0x000000ff
+
+#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8
+#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100
+
+#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB 9
+#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200
+
+#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB 10
+#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00
+
+#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB 12
+#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000
+
+#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13
+#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000
+
+#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB 14
+#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK 0x00004000
+
+#define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_2_RESERVED_2B_LSB 15
+#define REO_FLUSH_CACHE_2_RESERVED_2B_MASK 0xffff8000
+
+#define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET 0x0000000c
+#define REO_FLUSH_CACHE_3_RESERVED_3A_LSB 0
+#define REO_FLUSH_CACHE_3_RESERVED_3A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_FLUSH_CACHE_4_RESERVED_4A_LSB 0
+#define REO_FLUSH_CACHE_4_RESERVED_4A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_FLUSH_CACHE_5_RESERVED_5A_LSB 0
+#define REO_FLUSH_CACHE_5_RESERVED_5A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_FLUSH_CACHE_6_RESERVED_6A_LSB 0
+#define REO_FLUSH_CACHE_6_RESERVED_6A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_FLUSH_CACHE_7_RESERVED_7A_LSB 0
+#define REO_FLUSH_CACHE_7_RESERVED_7A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_FLUSH_CACHE_8_RESERVED_8A_LSB 0
+#define REO_FLUSH_CACHE_8_RESERVED_8A_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/reo_flush_cache_status.h b/hw/wcn6450/v1/reo_flush_cache_status.h
new file mode 100644
index 0000000..2030075
--- /dev/null
+++ b/hw/wcn6450/v1/reo_flush_cache_status.h
@@ -0,0 +1,215 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_FLUSH_CACHE_STATUS_H_
+#define _REO_FLUSH_CACHE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 25
+
+struct reo_flush_cache_status {
+ struct uniform_reo_status_header status_header;
+ uint32_t error_detected : 1,
+ block_error_details : 2,
+ reserved_2a : 5,
+ cache_controller_flush_status_hit: 1,
+ cache_controller_flush_status_desc_type: 3,
+ cache_controller_flush_status_client_id: 4,
+ cache_controller_flush_status_error: 2,
+ cache_controller_flush_count : 8,
+ reserved_2b : 6;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+ uint32_t reserved_9a : 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15a : 32;
+ uint32_t reserved_16a : 32;
+ uint32_t reserved_17a : 32;
+ uint32_t reserved_18a : 32;
+ uint32_t reserved_19a : 32;
+ uint32_t reserved_20a : 32;
+ uint32_t reserved_21a : 32;
+ uint32_t reserved_22a : 32;
+ uint32_t reserved_23a : 32;
+ uint32_t reserved_24a : 28,
+ looping_count : 4;
+};
+
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
+#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_LSB 0
+#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001
+
+#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_LSB 1
+#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_MASK 0x00000006
+
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_LSB 3
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_MASK 0x000000f8
+
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x00000100
+
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x00000e00
+
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x0000f000
+
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x00030000
+
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x03fc0000
+
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_LSB 26
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_MASK 0xfc000000
+
+#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
+#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
+#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
+#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
+#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
+#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
+#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
+#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
+#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
+#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
+#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
+#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
+#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
+#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
+#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
+#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
+#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
+#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
+
+#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
+#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_LSB 28
+#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/hw/wcn6450/v1/reo_flush_queue.h b/hw/wcn6450/v1/reo_flush_queue.h
new file mode 100644
index 0000000..9dbfc74
--- /dev/null
+++ b/hw/wcn6450/v1/reo_flush_queue.h
@@ -0,0 +1,107 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_FLUSH_QUEUE_H_
+#define _REO_FLUSH_QUEUE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9
+
+struct reo_flush_queue {
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t flush_desc_addr_31_0 : 32;
+ uint32_t flush_desc_addr_39_32 : 8,
+ block_desc_addr_usage_after_flush: 1,
+ block_resource_index : 2,
+ invalidate_queue_and_flush : 1,
+ reserved_2a : 20;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+};
+
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB 17
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004
+#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB 0
+#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB 0
+#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff
+
+#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8
+#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100
+
+#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB 9
+#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK 0x00000600
+
+#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_LSB 11
+#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_MASK 0x00000800
+
+#define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB 12
+#define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK 0xfffff000
+
+#define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c
+#define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB 0
+#define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB 0
+#define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB 0
+#define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB 0
+#define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB 0
+#define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB 0
+#define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/reo_flush_queue_status.h b/hw/wcn6450/v1/reo_flush_queue_status.h
new file mode 100644
index 0000000..612b138
--- /dev/null
+++ b/hw/wcn6450/v1/reo_flush_queue_status.h
@@ -0,0 +1,180 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_FLUSH_QUEUE_STATUS_H_
+#define _REO_FLUSH_QUEUE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 25
+
+struct reo_flush_queue_status {
+ struct uniform_reo_status_header status_header;
+ uint32_t error_detected : 1,
+ reserved_2a : 31;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+ uint32_t reserved_9a : 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15a : 32;
+ uint32_t reserved_16a : 32;
+ uint32_t reserved_17a : 32;
+ uint32_t reserved_18a : 32;
+ uint32_t reserved_19a : 32;
+ uint32_t reserved_20a : 32;
+ uint32_t reserved_21a : 32;
+ uint32_t reserved_22a : 32;
+ uint32_t reserved_23a : 32;
+ uint32_t reserved_24a : 28,
+ looping_count : 4;
+};
+
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
+#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_MASK 0x00000001
+
+#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_LSB 1
+#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_MASK 0xfffffffe
+
+#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
+#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
+#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
+#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
+#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
+#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
+#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
+#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
+#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
+#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
+#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
+#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
+#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
+#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
+#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
+#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
+#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
+#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
+
+#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
+#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28
+#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/hw/wcn6450/v1/reo_flush_timeout_list.h b/hw/wcn6450/v1/reo_flush_timeout_list.h
new file mode 100644
index 0000000..87acea7
--- /dev/null
+++ b/hw/wcn6450/v1/reo_flush_timeout_list.h
@@ -0,0 +1,97 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_FLUSH_TIMEOUT_LIST_H_
+#define _REO_FLUSH_TIMEOUT_LIST_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 9
+
+struct reo_flush_timeout_list {
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t ac_timout_list : 2,
+ reserved_1 : 30;
+ uint32_t minimum_release_desc_count : 16,
+ minimum_forward_buf_count : 16;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+};
+
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_LSB 17
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_OFFSET 0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_MASK 0x00000003
+
+#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_OFFSET 0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_LSB 2
+#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_MASK 0xfffffffc
+
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_MASK 0x0000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_LSB 16
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_MASK 0xffff0000
+
+#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_OFFSET 0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/reo_flush_timeout_list_status.h b/hw/wcn6450/v1/reo_flush_timeout_list_status.h
new file mode 100644
index 0000000..edea895
--- /dev/null
+++ b/hw/wcn6450/v1/reo_flush_timeout_list_status.h
@@ -0,0 +1,190 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
+#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 25
+
+struct reo_flush_timeout_list_status {
+ struct uniform_reo_status_header status_header;
+ uint32_t error_detected : 1,
+ timout_list_empty : 1,
+ reserved_2a : 30;
+ uint32_t release_desc_count : 16,
+ forward_buf_count : 16;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+ uint32_t reserved_9a : 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15a : 32;
+ uint32_t reserved_16a : 32;
+ uint32_t reserved_17a : 32;
+ uint32_t reserved_18a : 32;
+ uint32_t reserved_19a : 32;
+ uint32_t reserved_20a : 32;
+ uint32_t reserved_21a : 32;
+ uint32_t reserved_22a : 32;
+ uint32_t reserved_23a : 32;
+ uint32_t reserved_24a : 28,
+ looping_count : 4;
+};
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_MASK 0x00000001
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_OFFSET 0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_LSB 1
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_MASK 0x00000002
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_OFFSET 0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_LSB 2
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_MASK 0xfffffffc
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_OFFSET 0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_MASK 0x0000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_OFFSET 0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_LSB 16
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_MASK 0xffff0000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_OFFSET 0x00000024
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_OFFSET 0x00000028
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_OFFSET 0x00000030
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_OFFSET 0x00000034
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_OFFSET 0x00000038
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_OFFSET 0x00000040
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_OFFSET 0x00000044
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_OFFSET 0x00000048
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_OFFSET 0x00000050
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_OFFSET 0x00000054
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_OFFSET 0x00000058
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_OFFSET 0x00000060
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_MASK 0x0fffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_LSB 28
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/hw/wcn6450/v1/reo_get_queue_stats.h b/hw/wcn6450/v1/reo_get_queue_stats.h
new file mode 100644
index 0000000..cda805b
--- /dev/null
+++ b/hw/wcn6450/v1/reo_get_queue_stats.h
@@ -0,0 +1,97 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_GET_QUEUE_STATS_H_
+#define _REO_GET_QUEUE_STATS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9
+
+struct reo_get_queue_stats {
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32;
+ uint32_t rx_reo_queue_desc_addr_39_32 : 8,
+ clear_stats : 1,
+ reserved_2a : 23;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+};
+
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_LSB 17
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004
+#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008
+#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_OFFSET 0x00000008
+#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_LSB 8
+#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_MASK 0x00000100
+
+#define REO_GET_QUEUE_STATS_2_RESERVED_2A_OFFSET 0x00000008
+#define REO_GET_QUEUE_STATS_2_RESERVED_2A_LSB 9
+#define REO_GET_QUEUE_STATS_2_RESERVED_2A_MASK 0xfffffe00
+
+#define REO_GET_QUEUE_STATS_3_RESERVED_3A_OFFSET 0x0000000c
+#define REO_GET_QUEUE_STATS_3_RESERVED_3A_LSB 0
+#define REO_GET_QUEUE_STATS_3_RESERVED_3A_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_GET_QUEUE_STATS_4_RESERVED_4A_LSB 0
+#define REO_GET_QUEUE_STATS_4_RESERVED_4A_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_GET_QUEUE_STATS_5_RESERVED_5A_LSB 0
+#define REO_GET_QUEUE_STATS_5_RESERVED_5A_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_GET_QUEUE_STATS_6_RESERVED_6A_LSB 0
+#define REO_GET_QUEUE_STATS_6_RESERVED_6A_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_GET_QUEUE_STATS_7_RESERVED_7A_LSB 0
+#define REO_GET_QUEUE_STATS_7_RESERVED_7A_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_GET_QUEUE_STATS_8_RESERVED_8A_LSB 0
+#define REO_GET_QUEUE_STATS_8_RESERVED_8A_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/reo_get_queue_stats_status.h b/hw/wcn6450/v1/reo_get_queue_stats_status.h
new file mode 100644
index 0000000..02f1e74
--- /dev/null
+++ b/hw/wcn6450/v1/reo_get_queue_stats_status.h
@@ -0,0 +1,220 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_GET_QUEUE_STATS_STATUS_H_
+#define _REO_GET_QUEUE_STATS_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 25
+
+struct reo_get_queue_stats_status {
+ struct uniform_reo_status_header status_header;
+ uint32_t ssn : 12,
+ current_index : 8,
+ reserved_2 : 12;
+ uint32_t pn_31_0 : 32;
+ uint32_t pn_63_32 : 32;
+ uint32_t pn_95_64 : 32;
+ uint32_t pn_127_96 : 32;
+ uint32_t last_rx_enqueue_timestamp : 32;
+ uint32_t last_rx_dequeue_timestamp : 32;
+ uint32_t rx_bitmap_31_0 : 32;
+ uint32_t rx_bitmap_63_32 : 32;
+ uint32_t rx_bitmap_95_64 : 32;
+ uint32_t rx_bitmap_127_96 : 32;
+ uint32_t rx_bitmap_159_128 : 32;
+ uint32_t rx_bitmap_191_160 : 32;
+ uint32_t rx_bitmap_223_192 : 32;
+ uint32_t rx_bitmap_255_224 : 32;
+ uint32_t current_mpdu_count : 7,
+ current_msdu_count : 25;
+ uint32_t reserved_18 : 4,
+ timeout_count : 6,
+ forward_due_to_bar_count : 6,
+ duplicate_count : 16;
+ uint32_t frames_in_order_count : 24,
+ bar_received_count : 8;
+ uint32_t mpdu_frames_processed_count : 32;
+ uint32_t msdu_frames_processed_count : 32;
+ uint32_t total_processed_byte_count : 32;
+ uint32_t late_receive_mpdu_count : 12,
+ window_jump_2k : 4,
+ hole_count : 16;
+ uint32_t reserved_24a : 28,
+ looping_count : 4;
+};
+
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
+#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_2_SSN_OFFSET 0x00000008
+#define REO_GET_QUEUE_STATS_STATUS_2_SSN_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_2_SSN_MASK 0x00000fff
+
+#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_OFFSET 0x00000008
+#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_LSB 12
+#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_MASK 0x000ff000
+
+#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_OFFSET 0x00000008
+#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_LSB 20
+#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_MASK 0xfff00000
+
+#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_OFFSET 0x0000000c
+#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_OFFSET 0x00000010
+#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_OFFSET 0x00000014
+#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_OFFSET 0x00000018
+#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000001c
+#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000020
+#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_OFFSET 0x00000024
+#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_OFFSET 0x00000028
+#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_OFFSET 0x0000002c
+#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_OFFSET 0x00000030
+#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_OFFSET 0x00000034
+#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_OFFSET 0x00000038
+#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_OFFSET 0x0000003c
+#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_OFFSET 0x00000040
+#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_OFFSET 0x00000044
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_MASK 0x0000007f
+
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_OFFSET 0x00000044
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_LSB 7
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_MASK 0xffffff80
+
+#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_OFFSET 0x00000048
+#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_MASK 0x0000000f
+
+#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_OFFSET 0x00000048
+#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_LSB 4
+#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_MASK 0x000003f0
+
+#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000048
+#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_LSB 10
+#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00
+
+#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_OFFSET 0x00000048
+#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_LSB 16
+#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_MASK 0xffff0000
+
+#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_OFFSET 0x0000004c
+#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_OFFSET 0x0000004c
+#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_LSB 24
+#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_MASK 0xff000000
+
+#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000050
+#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000054
+#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000058
+#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000005c
+#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff
+
+#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_OFFSET 0x0000005c
+#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_LSB 12
+#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_MASK 0x0000f000
+
+#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_OFFSET 0x0000005c
+#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_LSB 16
+#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_MASK 0xffff0000
+
+#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_OFFSET 0x00000060
+#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_MASK 0x0fffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
+#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_LSB 28
+#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/hw/wcn6450/v1/reo_unblock_cache.h b/hw/wcn6450/v1/reo_unblock_cache.h
new file mode 100644
index 0000000..bff80e5
--- /dev/null
+++ b/hw/wcn6450/v1/reo_unblock_cache.h
@@ -0,0 +1,97 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_UNBLOCK_CACHE_H_
+#define _REO_UNBLOCK_CACHE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 9
+
+struct reo_unblock_cache {
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t unblock_type : 1,
+ cache_block_resource_index : 2,
+ reserved_1a : 29;
+ uint32_t reserved_2a : 32;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+};
+
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_LSB 17
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_OFFSET 0x00000004
+#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_LSB 0
+#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_MASK 0x00000001
+
+#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000004
+#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_LSB 1
+#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000006
+
+#define REO_UNBLOCK_CACHE_1_RESERVED_1A_OFFSET 0x00000004
+#define REO_UNBLOCK_CACHE_1_RESERVED_1A_LSB 3
+#define REO_UNBLOCK_CACHE_1_RESERVED_1A_MASK 0xfffffff8
+
+#define REO_UNBLOCK_CACHE_2_RESERVED_2A_OFFSET 0x00000008
+#define REO_UNBLOCK_CACHE_2_RESERVED_2A_LSB 0
+#define REO_UNBLOCK_CACHE_2_RESERVED_2A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_3_RESERVED_3A_OFFSET 0x0000000c
+#define REO_UNBLOCK_CACHE_3_RESERVED_3A_LSB 0
+#define REO_UNBLOCK_CACHE_3_RESERVED_3A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_UNBLOCK_CACHE_4_RESERVED_4A_LSB 0
+#define REO_UNBLOCK_CACHE_4_RESERVED_4A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_UNBLOCK_CACHE_5_RESERVED_5A_LSB 0
+#define REO_UNBLOCK_CACHE_5_RESERVED_5A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_UNBLOCK_CACHE_6_RESERVED_6A_LSB 0
+#define REO_UNBLOCK_CACHE_6_RESERVED_6A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_UNBLOCK_CACHE_7_RESERVED_7A_LSB 0
+#define REO_UNBLOCK_CACHE_7_RESERVED_7A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_UNBLOCK_CACHE_8_RESERVED_8A_LSB 0
+#define REO_UNBLOCK_CACHE_8_RESERVED_8A_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/reo_unblock_cache_status.h b/hw/wcn6450/v1/reo_unblock_cache_status.h
new file mode 100644
index 0000000..cd59f3a
--- /dev/null
+++ b/hw/wcn6450/v1/reo_unblock_cache_status.h
@@ -0,0 +1,185 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_UNBLOCK_CACHE_STATUS_H_
+#define _REO_UNBLOCK_CACHE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 25
+
+struct reo_unblock_cache_status {
+ struct uniform_reo_status_header status_header;
+ uint32_t error_detected : 1,
+ unblock_type : 1,
+ reserved_2a : 30;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+ uint32_t reserved_9a : 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15a : 32;
+ uint32_t reserved_16a : 32;
+ uint32_t reserved_17a : 32;
+ uint32_t reserved_18a : 32;
+ uint32_t reserved_19a : 32;
+ uint32_t reserved_20a : 32;
+ uint32_t reserved_21a : 32;
+ uint32_t reserved_22a : 32;
+ uint32_t reserved_23a : 32;
+ uint32_t reserved_24a : 28,
+ looping_count : 4;
+};
+
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
+#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
+#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001
+
+#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_OFFSET 0x00000008
+#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_LSB 1
+#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_MASK 0x00000002
+
+#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
+#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_LSB 2
+#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_MASK 0xfffffffc
+
+#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
+#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
+#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
+#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
+#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
+#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
+#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
+#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
+#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
+#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
+#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
+#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
+#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
+#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
+#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
+#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
+#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
+#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
+#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_LSB 28
+#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/hw/wcn6450/v1/reo_update_rx_reo_queue.h b/hw/wcn6450/v1/reo_update_rx_reo_queue.h
new file mode 100644
index 0000000..86f8b35
--- /dev/null
+++ b/hw/wcn6450/v1/reo_update_rx_reo_queue.h
@@ -0,0 +1,317 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_UPDATE_RX_REO_QUEUE_H_
+#define _REO_UPDATE_RX_REO_QUEUE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 9
+
+struct reo_update_rx_reo_queue {
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32;
+ uint32_t rx_reo_queue_desc_addr_39_32 : 8,
+ update_receive_queue_number : 1,
+ update_vld : 1,
+ update_associated_link_descriptor_counter: 1,
+ update_disable_duplicate_detection: 1,
+ update_soft_reorder_enable : 1,
+ update_ac : 1,
+ update_bar : 1,
+ update_rty : 1,
+ update_chk_2k_mode : 1,
+ update_oor_mode : 1,
+ update_ba_window_size : 1,
+ update_pn_check_needed : 1,
+ update_pn_shall_be_even : 1,
+ update_pn_shall_be_uneven : 1,
+ update_pn_handling_enable : 1,
+ update_pn_size : 1,
+ update_ignore_ampdu_flag : 1,
+ update_svld : 1,
+ update_ssn : 1,
+ update_seq_2k_error_detected_flag: 1,
+ update_pn_error_detected_flag : 1,
+ update_pn_valid : 1,
+ update_pn : 1,
+ clear_stat_counters : 1;
+ uint32_t receive_queue_number : 16,
+ vld : 1,
+ associated_link_descriptor_counter: 2,
+ disable_duplicate_detection : 1,
+ soft_reorder_enable : 1,
+ ac : 2,
+ bar : 1,
+ rty : 1,
+ chk_2k_mode : 1,
+ oor_mode : 1,
+ pn_check_needed : 1,
+ pn_shall_be_even : 1,
+ pn_shall_be_uneven : 1,
+ pn_handling_enable : 1,
+ ignore_ampdu_flag : 1;
+ uint32_t ba_window_size : 8,
+ pn_size : 2,
+ svld : 1,
+ ssn : 12,
+ seq_2k_error_detected_flag : 1,
+ pn_error_detected_flag : 1,
+ pn_valid : 1,
+ flush_from_cache : 1,
+ reserved_4a : 5;
+ uint32_t pn_31_0 : 32;
+ uint32_t pn_63_32 : 32;
+ uint32_t pn_95_64 : 32;
+ uint32_t pn_127_96 : 32;
+};
+
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB 17
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x00000100
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_LSB 9
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_MASK 0x00000200
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000400
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000800
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_LSB 12
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_MASK 0x00001000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_LSB 13
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_MASK 0x00002000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_LSB 14
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_MASK 0x00004000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_LSB 15
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_MASK 0x00008000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_LSB 16
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_MASK 0x00010000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_LSB 17
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_MASK 0x00020000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_LSB 18
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_MASK 0x00040000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_LSB 19
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_MASK 0x00080000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_LSB 20
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_MASK 0x00100000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x00200000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_LSB 22
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_MASK 0x00400000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_LSB 23
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_MASK 0x00800000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_LSB 24
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x01000000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_LSB 25
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_MASK 0x02000000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_LSB 26
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_MASK 0x04000000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x08000000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x10000000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_LSB 29
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_MASK 0x20000000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_LSB 30
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_MASK 0x40000000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_LSB 31
+#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_MASK 0x80000000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff
+
+#define REO_UPDATE_RX_REO_QUEUE_3_VLD_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_VLD_LSB 16
+#define REO_UPDATE_RX_REO_QUEUE_3_VLD_MASK 0x00010000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 17
+#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00060000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_LSB 19
+#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_MASK 0x00080000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_LSB 20
+#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_MASK 0x00100000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_AC_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_AC_LSB 21
+#define REO_UPDATE_RX_REO_QUEUE_3_AC_MASK 0x00600000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_BAR_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_BAR_LSB 23
+#define REO_UPDATE_RX_REO_QUEUE_3_BAR_MASK 0x00800000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_RTY_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_RTY_LSB 24
+#define REO_UPDATE_RX_REO_QUEUE_3_RTY_MASK 0x01000000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_LSB 25
+#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_MASK 0x02000000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_LSB 26
+#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_MASK 0x04000000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_LSB 27
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_MASK 0x08000000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_LSB 28
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_MASK 0x10000000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_LSB 29
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_MASK 0x20000000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_LSB 30
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_MASK 0x40000000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_LSB 31
+#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_MASK 0x80000000
+
+#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_MASK 0x000000ff
+
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_LSB 8
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_MASK 0x00000300
+
+#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_LSB 10
+#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_MASK 0x00000400
+
+#define REO_UPDATE_RX_REO_QUEUE_4_SSN_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_SSN_LSB 11
+#define REO_UPDATE_RX_REO_QUEUE_4_SSN_MASK 0x007ff800
+
+#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23
+#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000
+
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_LSB 24
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_MASK 0x01000000
+
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_LSB 25
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_MASK 0x02000000
+
+#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_LSB 26
+#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_MASK 0x04000000
+
+#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_LSB 27
+#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_MASK 0xf8000000
+
+#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_OFFSET 0x00000014
+#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_OFFSET 0x00000018
+#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_OFFSET 0x0000001c
+#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_OFFSET 0x00000020
+#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/reo_update_rx_reo_queue_status.h b/hw/wcn6450/v1/reo_update_rx_reo_queue_status.h
new file mode 100644
index 0000000..35afee0
--- /dev/null
+++ b/hw/wcn6450/v1/reo_update_rx_reo_queue_status.h
@@ -0,0 +1,175 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
+#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 25
+
+struct reo_update_rx_reo_queue_status {
+ struct uniform_reo_status_header status_header;
+ uint32_t reserved_2a : 32;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+ uint32_t reserved_9a : 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15a : 32;
+ uint32_t reserved_16a : 32;
+ uint32_t reserved_17a : 32;
+ uint32_t reserved_18a : 32;
+ uint32_t reserved_19a : 32;
+ uint32_t reserved_20a : 32;
+ uint32_t reserved_21a : 32;
+ uint32_t reserved_22a : 32;
+ uint32_t reserved_23a : 32;
+ uint32_t reserved_24a : 28,
+ looping_count : 4;
+};
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/hw/wcn6450/v1/rx_attention.h b/hw/wcn6450/v1/rx_attention.h
new file mode 100644
index 0000000..28f64d6
--- /dev/null
+++ b/hw/wcn6450/v1/rx_attention.h
@@ -0,0 +1,282 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_ATTENTION_H_
+#define _RX_ATTENTION_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_ATTENTION 3
+
+struct rx_attention {
+ uint32_t rxpcu_mpdu_filter_in_category : 2,
+ sw_frame_group_id : 7,
+ reserved_0 : 7,
+ phy_ppdu_id : 16;
+ uint32_t first_mpdu : 1,
+ reserved_1a : 1,
+ mcast_bcast : 1,
+ ast_index_not_found : 1,
+ ast_index_timeout : 1,
+ power_mgmt : 1,
+ non_qos : 1,
+ null_data : 1,
+ mgmt_type : 1,
+ ctrl_type : 1,
+ more_data : 1,
+ eosp : 1,
+ a_msdu_error : 1,
+ fragment_flag : 1,
+ order : 1,
+ cce_match : 1,
+ overflow_err : 1,
+ msdu_length_err : 1,
+ tcp_udp_chksum_fail : 1,
+ ip_chksum_fail : 1,
+ sa_idx_invalid : 1,
+ da_idx_invalid : 1,
+ reserved_1b : 1,
+ rx_in_tx_decrypt_byp : 1,
+ encrypt_required : 1,
+ directed : 1,
+ buffer_fragment : 1,
+ mpdu_length_err : 1,
+ tkip_mic_err : 1,
+ decrypt_err : 1,
+ unencrypted_frame_err : 1,
+ fcs_err : 1;
+ uint32_t flow_idx_timeout : 1,
+ flow_idx_invalid : 1,
+ wifi_parser_error : 1,
+ amsdu_parser_error : 1,
+ sa_idx_timeout : 1,
+ da_idx_timeout : 1,
+ msdu_limit_error : 1,
+ da_is_valid : 1,
+ da_is_mcbc : 1,
+ sa_is_valid : 1,
+ decrypt_status_code : 3,
+ rx_bitmap_not_updated : 1,
+ reserved_2 : 17,
+ msdu_done : 1;
+};
+
+#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000
+#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000
+#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_LSB 2
+#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+#define RX_ATTENTION_0_RESERVED_0_OFFSET 0x00000000
+#define RX_ATTENTION_0_RESERVED_0_LSB 9
+#define RX_ATTENTION_0_RESERVED_0_MASK 0x0000fe00
+
+#define RX_ATTENTION_0_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_ATTENTION_0_PHY_PPDU_ID_LSB 16
+#define RX_ATTENTION_0_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RX_ATTENTION_1_FIRST_MPDU_OFFSET 0x00000004
+#define RX_ATTENTION_1_FIRST_MPDU_LSB 0
+#define RX_ATTENTION_1_FIRST_MPDU_MASK 0x00000001
+
+#define RX_ATTENTION_1_RESERVED_1A_OFFSET 0x00000004
+#define RX_ATTENTION_1_RESERVED_1A_LSB 1
+#define RX_ATTENTION_1_RESERVED_1A_MASK 0x00000002
+
+#define RX_ATTENTION_1_MCAST_BCAST_OFFSET 0x00000004
+#define RX_ATTENTION_1_MCAST_BCAST_LSB 2
+#define RX_ATTENTION_1_MCAST_BCAST_MASK 0x00000004
+
+#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_OFFSET 0x00000004
+#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_LSB 3
+#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_MASK 0x00000008
+
+#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_OFFSET 0x00000004
+#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_LSB 4
+#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_MASK 0x00000010
+
+#define RX_ATTENTION_1_POWER_MGMT_OFFSET 0x00000004
+#define RX_ATTENTION_1_POWER_MGMT_LSB 5
+#define RX_ATTENTION_1_POWER_MGMT_MASK 0x00000020
+
+#define RX_ATTENTION_1_NON_QOS_OFFSET 0x00000004
+#define RX_ATTENTION_1_NON_QOS_LSB 6
+#define RX_ATTENTION_1_NON_QOS_MASK 0x00000040
+
+#define RX_ATTENTION_1_NULL_DATA_OFFSET 0x00000004
+#define RX_ATTENTION_1_NULL_DATA_LSB 7
+#define RX_ATTENTION_1_NULL_DATA_MASK 0x00000080
+
+#define RX_ATTENTION_1_MGMT_TYPE_OFFSET 0x00000004
+#define RX_ATTENTION_1_MGMT_TYPE_LSB 8
+#define RX_ATTENTION_1_MGMT_TYPE_MASK 0x00000100
+
+#define RX_ATTENTION_1_CTRL_TYPE_OFFSET 0x00000004
+#define RX_ATTENTION_1_CTRL_TYPE_LSB 9
+#define RX_ATTENTION_1_CTRL_TYPE_MASK 0x00000200
+
+#define RX_ATTENTION_1_MORE_DATA_OFFSET 0x00000004
+#define RX_ATTENTION_1_MORE_DATA_LSB 10
+#define RX_ATTENTION_1_MORE_DATA_MASK 0x00000400
+
+#define RX_ATTENTION_1_EOSP_OFFSET 0x00000004
+#define RX_ATTENTION_1_EOSP_LSB 11
+#define RX_ATTENTION_1_EOSP_MASK 0x00000800
+
+#define RX_ATTENTION_1_A_MSDU_ERROR_OFFSET 0x00000004
+#define RX_ATTENTION_1_A_MSDU_ERROR_LSB 12
+#define RX_ATTENTION_1_A_MSDU_ERROR_MASK 0x00001000
+
+#define RX_ATTENTION_1_FRAGMENT_FLAG_OFFSET 0x00000004
+#define RX_ATTENTION_1_FRAGMENT_FLAG_LSB 13
+#define RX_ATTENTION_1_FRAGMENT_FLAG_MASK 0x00002000
+
+#define RX_ATTENTION_1_ORDER_OFFSET 0x00000004
+#define RX_ATTENTION_1_ORDER_LSB 14
+#define RX_ATTENTION_1_ORDER_MASK 0x00004000
+
+#define RX_ATTENTION_1_CCE_MATCH_OFFSET 0x00000004
+#define RX_ATTENTION_1_CCE_MATCH_LSB 15
+#define RX_ATTENTION_1_CCE_MATCH_MASK 0x00008000
+
+#define RX_ATTENTION_1_OVERFLOW_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_1_OVERFLOW_ERR_LSB 16
+#define RX_ATTENTION_1_OVERFLOW_ERR_MASK 0x00010000
+
+#define RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB 17
+#define RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK 0x00020000
+
+#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000004
+#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB 18
+#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000
+
+#define RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET 0x00000004
+#define RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB 19
+#define RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK 0x00080000
+
+#define RX_ATTENTION_1_SA_IDX_INVALID_OFFSET 0x00000004
+#define RX_ATTENTION_1_SA_IDX_INVALID_LSB 20
+#define RX_ATTENTION_1_SA_IDX_INVALID_MASK 0x00100000
+
+#define RX_ATTENTION_1_DA_IDX_INVALID_OFFSET 0x00000004
+#define RX_ATTENTION_1_DA_IDX_INVALID_LSB 21
+#define RX_ATTENTION_1_DA_IDX_INVALID_MASK 0x00200000
+
+#define RX_ATTENTION_1_RESERVED_1B_OFFSET 0x00000004
+#define RX_ATTENTION_1_RESERVED_1B_LSB 22
+#define RX_ATTENTION_1_RESERVED_1B_MASK 0x00400000
+
+#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004
+#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_LSB 23
+#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000
+
+#define RX_ATTENTION_1_ENCRYPT_REQUIRED_OFFSET 0x00000004
+#define RX_ATTENTION_1_ENCRYPT_REQUIRED_LSB 24
+#define RX_ATTENTION_1_ENCRYPT_REQUIRED_MASK 0x01000000
+
+#define RX_ATTENTION_1_DIRECTED_OFFSET 0x00000004
+#define RX_ATTENTION_1_DIRECTED_LSB 25
+#define RX_ATTENTION_1_DIRECTED_MASK 0x02000000
+
+#define RX_ATTENTION_1_BUFFER_FRAGMENT_OFFSET 0x00000004
+#define RX_ATTENTION_1_BUFFER_FRAGMENT_LSB 26
+#define RX_ATTENTION_1_BUFFER_FRAGMENT_MASK 0x04000000
+
+#define RX_ATTENTION_1_MPDU_LENGTH_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_1_MPDU_LENGTH_ERR_LSB 27
+#define RX_ATTENTION_1_MPDU_LENGTH_ERR_MASK 0x08000000
+
+#define RX_ATTENTION_1_TKIP_MIC_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_1_TKIP_MIC_ERR_LSB 28
+#define RX_ATTENTION_1_TKIP_MIC_ERR_MASK 0x10000000
+
+#define RX_ATTENTION_1_DECRYPT_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_1_DECRYPT_ERR_LSB 29
+#define RX_ATTENTION_1_DECRYPT_ERR_MASK 0x20000000
+
+#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_LSB 30
+#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_MASK 0x40000000
+
+#define RX_ATTENTION_1_FCS_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_1_FCS_ERR_LSB 31
+#define RX_ATTENTION_1_FCS_ERR_MASK 0x80000000
+
+#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_LSB 0
+#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_MASK 0x00000001
+
+#define RX_ATTENTION_2_FLOW_IDX_INVALID_OFFSET 0x00000008
+#define RX_ATTENTION_2_FLOW_IDX_INVALID_LSB 1
+#define RX_ATTENTION_2_FLOW_IDX_INVALID_MASK 0x00000002
+
+#define RX_ATTENTION_2_WIFI_PARSER_ERROR_OFFSET 0x00000008
+#define RX_ATTENTION_2_WIFI_PARSER_ERROR_LSB 2
+#define RX_ATTENTION_2_WIFI_PARSER_ERROR_MASK 0x00000004
+
+#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_OFFSET 0x00000008
+#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_LSB 3
+#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_MASK 0x00000008
+
+#define RX_ATTENTION_2_SA_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_ATTENTION_2_SA_IDX_TIMEOUT_LSB 4
+#define RX_ATTENTION_2_SA_IDX_TIMEOUT_MASK 0x00000010
+
+#define RX_ATTENTION_2_DA_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_ATTENTION_2_DA_IDX_TIMEOUT_LSB 5
+#define RX_ATTENTION_2_DA_IDX_TIMEOUT_MASK 0x00000020
+
+#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_OFFSET 0x00000008
+#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_LSB 6
+#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_MASK 0x00000040
+
+#define RX_ATTENTION_2_DA_IS_VALID_OFFSET 0x00000008
+#define RX_ATTENTION_2_DA_IS_VALID_LSB 7
+#define RX_ATTENTION_2_DA_IS_VALID_MASK 0x00000080
+
+#define RX_ATTENTION_2_DA_IS_MCBC_OFFSET 0x00000008
+#define RX_ATTENTION_2_DA_IS_MCBC_LSB 8
+#define RX_ATTENTION_2_DA_IS_MCBC_MASK 0x00000100
+
+#define RX_ATTENTION_2_SA_IS_VALID_OFFSET 0x00000008
+#define RX_ATTENTION_2_SA_IS_VALID_LSB 9
+#define RX_ATTENTION_2_SA_IS_VALID_MASK 0x00000200
+
+#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET 0x00000008
+#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB 10
+#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK 0x00001c00
+
+#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000008
+#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_LSB 13
+#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_MASK 0x00002000
+
+#define RX_ATTENTION_2_RESERVED_2_OFFSET 0x00000008
+#define RX_ATTENTION_2_RESERVED_2_LSB 14
+#define RX_ATTENTION_2_RESERVED_2_MASK 0x7fffc000
+
+#define RX_ATTENTION_2_MSDU_DONE_OFFSET 0x00000008
+#define RX_ATTENTION_2_MSDU_DONE_LSB 31
+#define RX_ATTENTION_2_MSDU_DONE_MASK 0x80000000
+
+#endif
diff --git a/hw/wcn6450/v1/rx_flow_search_entry.h b/hw/wcn6450/v1/rx_flow_search_entry.h
new file mode 100644
index 0000000..fea3afa
--- /dev/null
+++ b/hw/wcn6450/v1/rx_flow_search_entry.h
@@ -0,0 +1,157 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_FLOW_SEARCH_ENTRY_H_
+#define _RX_FLOW_SEARCH_ENTRY_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16
+
+struct rx_flow_search_entry {
+ uint32_t src_ip_127_96 : 32;
+ uint32_t src_ip_95_64 : 32;
+ uint32_t src_ip_63_32 : 32;
+ uint32_t src_ip_31_0 : 32;
+ uint32_t dest_ip_127_96 : 32;
+ uint32_t dest_ip_95_64 : 32;
+ uint32_t dest_ip_63_32 : 32;
+ uint32_t dest_ip_31_0 : 32;
+ uint32_t src_port : 16,
+ dest_port : 16;
+ uint32_t l4_protocol : 8,
+ valid : 1,
+ reserved_9 : 15,
+ reo_destination_indication : 5,
+ msdu_drop : 1,
+ reo_destination_handler : 2;
+ uint32_t metadata : 32;
+ uint32_t aggregation_count : 7,
+ lro_eligible : 1,
+ msdu_count : 24;
+ uint32_t msdu_byte_count : 32;
+ uint32_t timestamp : 32;
+ uint32_t cumulative_l4_checksum : 16,
+ cumulative_ip_length : 16;
+ uint32_t tcp_sequence_number : 32;
+};
+
+#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_OFFSET 0x00000000
+#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_OFFSET 0x00000004
+#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_OFFSET 0x00000008
+#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_OFFSET 0x0000000c
+#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_OFFSET 0x00000010
+#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_OFFSET 0x00000014
+#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_OFFSET 0x00000018
+#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_OFFSET 0x0000001c
+#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_OFFSET 0x00000020
+#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_MASK 0x0000ffff
+
+#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_OFFSET 0x00000020
+#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_LSB 16
+#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_MASK 0xffff0000
+
+#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_MASK 0x000000ff
+
+#define RX_FLOW_SEARCH_ENTRY_9_VALID_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_VALID_LSB 8
+#define RX_FLOW_SEARCH_ENTRY_9_VALID_MASK 0x00000100
+
+#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_LSB 9
+#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_MASK 0x00fffe00
+
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_LSB 24
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_MASK 0x1f000000
+
+#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_LSB 29
+#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_MASK 0x20000000
+
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_LSB 30
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_MASK 0xc0000000
+
+#define RX_FLOW_SEARCH_ENTRY_10_METADATA_OFFSET 0x00000028
+#define RX_FLOW_SEARCH_ENTRY_10_METADATA_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_10_METADATA_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_OFFSET 0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_MASK 0x0000007f
+
+#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_OFFSET 0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_LSB 7
+#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_MASK 0x00000080
+
+#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_OFFSET 0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_LSB 8
+#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_MASK 0xffffff00
+
+#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_OFFSET 0x00000030
+#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_OFFSET 0x00000034
+#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000038
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff
+
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_LSB 16
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_MASK 0xffff0000
+
+#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c
+#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/rx_location_info.h b/hw/wcn6450/v1/rx_location_info.h
new file mode 100644
index 0000000..49a9851
--- /dev/null
+++ b/hw/wcn6450/v1/rx_location_info.h
@@ -0,0 +1,207 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_LOCATION_INFO_H_
+#define _RX_LOCATION_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_LOCATION_INFO 9
+
+struct rx_location_info {
+ uint32_t rtt_fac_legacy : 16,
+ rtt_fac_legacy_ext80 : 16;
+ uint32_t rtt_fac_vht : 16,
+ rtt_fac_vht_ext80 : 16;
+ uint32_t rtt_fac_legacy_status : 1,
+ rtt_fac_legacy_ext80_status : 1,
+ rtt_fac_vht_status : 1,
+ rtt_fac_vht_ext80_status : 1,
+ rtt_fac_sifs : 12,
+ rtt_fac_sifs_status : 2,
+ rtt_cfr_status : 1,
+ rtt_cir_status : 1,
+ rtt_channel_dump_size : 11,
+ rtt_hw_ifft_mode : 1;
+ uint32_t rtt_btcf_status : 1,
+ rtt_preamble_type : 5,
+ rtt_pkt_bw_leg : 2,
+ rtt_pkt_bw_vht : 2,
+ rtt_gi_type : 2,
+ rtt_mcs_rate : 5,
+ rtt_strongest_chain : 3,
+ rtt_strongest_chain_ext80 : 3,
+ rtt_rx_chain_mask : 8,
+ reserved_3 : 1;
+ uint32_t rx_start_ts : 32;
+ uint32_t rx_end_ts : 32;
+ uint32_t sfo_phase_pkt_start : 12,
+ sfo_phase_pkt_end : 12,
+ rtt_che_buffer_pointer_high8 : 8;
+ uint32_t rtt_che_buffer_pointer_low32 : 32;
+ uint32_t rtt_cfo_measurement : 14,
+ rtt_chan_spread : 8,
+ rtt_timing_backoff_sel : 2,
+ reserved_8 : 7,
+ rx_location_info_valid : 1;
+};
+
+#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_OFFSET 0x00000000
+#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_LSB 0
+#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000000
+#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_LSB 16
+#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_1_RTT_FAC_VHT_OFFSET 0x00000004
+#define RX_LOCATION_INFO_1_RTT_FAC_VHT_LSB 0
+#define RX_LOCATION_INFO_1_RTT_FAC_VHT_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_OFFSET 0x00000004
+#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_LSB 16
+#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_LSB 0
+#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_MASK 0x00000001
+
+#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1
+#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002
+
+#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_LSB 2
+#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_MASK 0x00000004
+
+#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_LSB 3
+#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008
+
+#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_LSB 4
+#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_MASK 0x0000fff0
+
+#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_LSB 16
+#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_MASK 0x00030000
+
+#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_LSB 18
+#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_MASK 0x00040000
+
+#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_LSB 19
+#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_MASK 0x00080000
+
+#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_LSB 20
+#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000
+
+#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_LSB 31
+#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_MASK 0x80000000
+
+#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_LSB 0
+#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_MASK 0x00000001
+
+#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_LSB 1
+#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_MASK 0x0000003e
+
+#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_LSB 6
+#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_MASK 0x000000c0
+
+#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_LSB 8
+#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_MASK 0x00000300
+
+#define RX_LOCATION_INFO_3_RTT_GI_TYPE_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RTT_GI_TYPE_LSB 10
+#define RX_LOCATION_INFO_3_RTT_GI_TYPE_MASK 0x00000c00
+
+#define RX_LOCATION_INFO_3_RTT_MCS_RATE_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RTT_MCS_RATE_LSB 12
+#define RX_LOCATION_INFO_3_RTT_MCS_RATE_MASK 0x0001f000
+
+#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_LSB 17
+#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_MASK 0x000e0000
+
+#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_LSB 20
+#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000
+
+#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_LSB 23
+#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_MASK 0x7f800000
+
+#define RX_LOCATION_INFO_3_RESERVED_3_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RESERVED_3_LSB 31
+#define RX_LOCATION_INFO_3_RESERVED_3_MASK 0x80000000
+
+#define RX_LOCATION_INFO_4_RX_START_TS_OFFSET 0x00000010
+#define RX_LOCATION_INFO_4_RX_START_TS_LSB 0
+#define RX_LOCATION_INFO_4_RX_START_TS_MASK 0xffffffff
+
+#define RX_LOCATION_INFO_5_RX_END_TS_OFFSET 0x00000014
+#define RX_LOCATION_INFO_5_RX_END_TS_LSB 0
+#define RX_LOCATION_INFO_5_RX_END_TS_MASK 0xffffffff
+
+#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_OFFSET 0x00000018
+#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_LSB 0
+#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_MASK 0x00000fff
+
+#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_OFFSET 0x00000018
+#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_LSB 12
+#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_MASK 0x00fff000
+
+#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x00000018
+#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24
+#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000
+
+#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000001c
+#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
+#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff
+
+#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_OFFSET 0x00000020
+#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_LSB 0
+#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_MASK 0x00003fff
+
+#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_OFFSET 0x00000020
+#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_LSB 14
+#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_MASK 0x003fc000
+
+#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000020
+#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_LSB 22
+#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000
+
+#define RX_LOCATION_INFO_8_RESERVED_8_OFFSET 0x00000020
+#define RX_LOCATION_INFO_8_RESERVED_8_LSB 24
+#define RX_LOCATION_INFO_8_RESERVED_8_MASK 0x7f000000
+
+#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_OFFSET 0x00000020
+#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_LSB 31
+#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_MASK 0x80000000
+
+#endif
diff --git a/hw/wcn6450/v1/rx_mpdu_desc_info.h b/hw/wcn6450/v1/rx_mpdu_desc_info.h
new file mode 100644
index 0000000..3bca315
--- /dev/null
+++ b/hw/wcn6450/v1/rx_mpdu_desc_info.h
@@ -0,0 +1,107 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MPDU_DESC_INFO_H_
+#define _RX_MPDU_DESC_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2
+
+struct rx_mpdu_desc_info {
+ uint32_t msdu_count : 8,
+ mpdu_sequence_number : 12,
+ fragment_flag : 1,
+ mpdu_retry_bit : 1,
+ ampdu_flag : 1,
+ bar_frame : 1,
+ pn_fields_contain_valid_info : 1,
+ sa_is_valid : 1,
+ sa_idx_timeout : 1,
+ da_is_valid : 1,
+ da_is_mcbc : 1,
+ da_idx_timeout : 1,
+ raw_mpdu : 1,
+ more_fragment_flag : 1;
+ uint32_t peer_meta_data : 32;
+};
+
+#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB 0
+#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK 0x000000ff
+
+#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB 8
+#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
+
+#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_LSB 20
+#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK 0x00100000
+
+#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_LSB 21
+#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK 0x00200000
+
+#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_LSB 22
+#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK 0x00400000
+
+#define RX_MPDU_DESC_INFO_0_BAR_FRAME_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_BAR_FRAME_LSB 23
+#define RX_MPDU_DESC_INFO_0_BAR_FRAME_MASK 0x00800000
+
+#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
+#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
+
+#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_LSB 25
+#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_MASK 0x02000000
+
+#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 26
+#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x04000000
+
+#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_LSB 27
+#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_MASK 0x08000000
+
+#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_LSB 28
+#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x10000000
+
+#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 29
+#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x20000000
+
+#define RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_RAW_MPDU_LSB 30
+#define RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK 0x40000000
+
+#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_LSB 31
+#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_MASK 0x80000000
+
+#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET 0x00000004
+#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB 0
+#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/rx_mpdu_details.h b/hw/wcn6450/v1/rx_mpdu_details.h
new file mode 100644
index 0000000..36216b3
--- /dev/null
+++ b/hw/wcn6450/v1/rx_mpdu_details.h
@@ -0,0 +1,113 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MPDU_DETAILS_H_
+#define _RX_MPDU_DETAILS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+#include "rx_mpdu_desc_info.h"
+
+#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4
+
+struct rx_mpdu_details {
+ struct buffer_addr_info msdu_link_desc_addr_info;
+ struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
+};
+
+#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000
+
+#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
+#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/rx_mpdu_end.h b/hw/wcn6450/v1/rx_mpdu_end.h
new file mode 100644
index 0000000..8a22fcb
--- /dev/null
+++ b/hw/wcn6450/v1/rx_mpdu_end.h
@@ -0,0 +1,132 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MPDU_END_H_
+#define _RX_MPDU_END_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_MPDU_END 2
+
+struct rx_mpdu_end {
+ uint32_t rxpcu_mpdu_filter_in_category : 2,
+ sw_frame_group_id : 7,
+ reserved_0 : 7,
+ phy_ppdu_id : 16;
+ uint32_t reserved_1a : 11,
+ unsup_ktype_short_frame : 1,
+ rx_in_tx_decrypt_byp : 1,
+ overflow_err : 1,
+ mpdu_length_err : 1,
+ tkip_mic_err : 1,
+ decrypt_err : 1,
+ unencrypted_frame_err : 1,
+ pn_fields_contain_valid_info : 1,
+ fcs_err : 1,
+ msdu_length_err : 1,
+ rxdma0_destination_ring : 2,
+ rxdma1_destination_ring : 2,
+ decrypt_status_code : 3,
+ rx_bitmap_not_updated : 1,
+ reserved_1b : 3;
+};
+
+#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000
+#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000
+#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB 2
+#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+#define RX_MPDU_END_0_RESERVED_0_OFFSET 0x00000000
+#define RX_MPDU_END_0_RESERVED_0_LSB 9
+#define RX_MPDU_END_0_RESERVED_0_MASK 0x0000fe00
+
+#define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_MPDU_END_0_PHY_PPDU_ID_LSB 16
+#define RX_MPDU_END_0_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RX_MPDU_END_1_RESERVED_1A_OFFSET 0x00000004
+#define RX_MPDU_END_1_RESERVED_1A_LSB 0
+#define RX_MPDU_END_1_RESERVED_1A_MASK 0x000007ff
+
+#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004
+#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB 11
+#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800
+
+#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004
+#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB 12
+#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000
+
+#define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_1_OVERFLOW_ERR_LSB 13
+#define RX_MPDU_END_1_OVERFLOW_ERR_MASK 0x00002000
+
+#define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB 14
+#define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK 0x00004000
+
+#define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_1_TKIP_MIC_ERR_LSB 15
+#define RX_MPDU_END_1_TKIP_MIC_ERR_MASK 0x00008000
+
+#define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_1_DECRYPT_ERR_LSB 16
+#define RX_MPDU_END_1_DECRYPT_ERR_MASK 0x00010000
+
+#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB 17
+#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK 0x00020000
+
+#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004
+#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18
+#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000
+
+#define RX_MPDU_END_1_FCS_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_1_FCS_ERR_LSB 19
+#define RX_MPDU_END_1_FCS_ERR_MASK 0x00080000
+
+#define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB 20
+#define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK 0x00100000
+
+#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET 0x00000004
+#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB 21
+#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK 0x00600000
+
+#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET 0x00000004
+#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB 23
+#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK 0x01800000
+
+#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET 0x00000004
+#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB 25
+#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK 0x0e000000
+
+#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004
+#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB 28
+#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK 0x10000000
+
+#define RX_MPDU_END_1_RESERVED_1B_OFFSET 0x00000004
+#define RX_MPDU_END_1_RESERVED_1B_LSB 29
+#define RX_MPDU_END_1_RESERVED_1B_MASK 0xe0000000
+
+#endif
diff --git a/hw/wcn6450/v1/rx_mpdu_info.h b/hw/wcn6450/v1/rx_mpdu_info.h
new file mode 100644
index 0000000..c95fde7
--- /dev/null
+++ b/hw/wcn6450/v1/rx_mpdu_info.h
@@ -0,0 +1,537 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MPDU_INFO_H_
+#define _RX_MPDU_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rxpt_classify_info.h"
+
+#define NUM_OF_DWORDS_RX_MPDU_INFO 23
+
+struct rx_mpdu_info {
+ struct rxpt_classify_info rxpt_classify_info_details;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32;
+ uint32_t rx_reo_queue_desc_addr_39_32 : 8,
+ receive_queue_number : 16,
+ pre_delim_err_warning : 1,
+ first_delim_err : 1,
+ reserved_2a : 6;
+ uint32_t pn_31_0 : 32;
+ uint32_t pn_63_32 : 32;
+ uint32_t pn_95_64 : 32;
+ uint32_t pn_127_96 : 32;
+ uint32_t epd_en : 1,
+ all_frames_shall_be_encrypted : 1,
+ encrypt_type : 4,
+ wep_key_width_for_variable_key : 2,
+ __reserved_g_0003 : 2,
+ bssid_hit : 1,
+ bssid_number : 4,
+ tid : 4,
+ reserved_7a : 13;
+ uint32_t peer_meta_data : 32;
+ uint32_t rxpcu_mpdu_filter_in_category : 2,
+ sw_frame_group_id : 7,
+ ndp_frame : 1,
+ phy_err : 1,
+ phy_err_during_mpdu_header : 1,
+ protocol_version_err : 1,
+ ast_based_lookup_valid : 1,
+ reserved_9a : 2,
+ phy_ppdu_id : 16;
+ uint32_t ast_index : 16,
+ sw_peer_id : 16;
+ uint32_t mpdu_frame_control_valid : 1,
+ mpdu_duration_valid : 1,
+ mac_addr_ad1_valid : 1,
+ mac_addr_ad2_valid : 1,
+ mac_addr_ad3_valid : 1,
+ mac_addr_ad4_valid : 1,
+ mpdu_sequence_control_valid : 1,
+ mpdu_qos_control_valid : 1,
+ mpdu_ht_control_valid : 1,
+ frame_encryption_info_valid : 1,
+ mpdu_fragment_number : 4,
+ more_fragment_flag : 1,
+ reserved_11a : 1,
+ fr_ds : 1,
+ to_ds : 1,
+ encrypted : 1,
+ mpdu_retry : 1,
+ mpdu_sequence_number : 12;
+ uint32_t key_id_octet : 8,
+ new_peer_entry : 1,
+ decrypt_needed : 1,
+ decap_type : 2,
+ rx_insert_vlan_c_tag_padding : 1,
+ rx_insert_vlan_s_tag_padding : 1,
+ strip_vlan_c_tag_decap : 1,
+ strip_vlan_s_tag_decap : 1,
+ pre_delim_count : 12,
+ ampdu_flag : 1,
+ bar_frame : 1,
+ raw_mpdu : 1,
+ reserved_12 : 1;
+ uint32_t mpdu_length : 14,
+ first_mpdu : 1,
+ mcast_bcast : 1,
+ ast_index_not_found : 1,
+ ast_index_timeout : 1,
+ power_mgmt : 1,
+ non_qos : 1,
+ null_data : 1,
+ mgmt_type : 1,
+ ctrl_type : 1,
+ more_data : 1,
+ eosp : 1,
+ fragment_flag : 1,
+ order : 1,
+ u_apsd_trigger : 1,
+ encrypt_required : 1,
+ directed : 1,
+ amsdu_present : 1,
+ reserved_13 : 1;
+ uint32_t mpdu_frame_control_field : 16,
+ mpdu_duration_field : 16;
+ uint32_t mac_addr_ad1_31_0 : 32;
+ uint32_t mac_addr_ad1_47_32 : 16,
+ mac_addr_ad2_15_0 : 16;
+ uint32_t mac_addr_ad2_47_16 : 32;
+ uint32_t mac_addr_ad3_31_0 : 32;
+ uint32_t mac_addr_ad3_47_32 : 16,
+ mpdu_sequence_control_field : 16;
+ uint32_t mac_addr_ad4_31_0 : 32;
+ uint32_t mac_addr_ad4_47_32 : 16,
+ mpdu_qos_control_field : 16;
+ uint32_t mpdu_ht_control_field : 32;
+};
+
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060
+
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080
+
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100
+
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200
+
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400
+
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800
+
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000
+
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000
+
+#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004
+#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008
+#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008
+#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_LSB 8
+#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00
+
+#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008
+#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_LSB 24
+#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_MASK 0x01000000
+
+#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_OFFSET 0x00000008
+#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_LSB 25
+#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_MASK 0x02000000
+
+#define RX_MPDU_INFO_2_RESERVED_2A_OFFSET 0x00000008
+#define RX_MPDU_INFO_2_RESERVED_2A_LSB 26
+#define RX_MPDU_INFO_2_RESERVED_2A_MASK 0xfc000000
+
+#define RX_MPDU_INFO_3_PN_31_0_OFFSET 0x0000000c
+#define RX_MPDU_INFO_3_PN_31_0_LSB 0
+#define RX_MPDU_INFO_3_PN_31_0_MASK 0xffffffff
+
+#define RX_MPDU_INFO_4_PN_63_32_OFFSET 0x00000010
+#define RX_MPDU_INFO_4_PN_63_32_LSB 0
+#define RX_MPDU_INFO_4_PN_63_32_MASK 0xffffffff
+
+#define RX_MPDU_INFO_5_PN_95_64_OFFSET 0x00000014
+#define RX_MPDU_INFO_5_PN_95_64_LSB 0
+#define RX_MPDU_INFO_5_PN_95_64_MASK 0xffffffff
+
+#define RX_MPDU_INFO_6_PN_127_96_OFFSET 0x00000018
+#define RX_MPDU_INFO_6_PN_127_96_LSB 0
+#define RX_MPDU_INFO_6_PN_127_96_MASK 0xffffffff
+
+#define RX_MPDU_INFO_7_EPD_EN_OFFSET 0x0000001c
+#define RX_MPDU_INFO_7_EPD_EN_LSB 0
+#define RX_MPDU_INFO_7_EPD_EN_MASK 0x00000001
+
+#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c
+#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1
+#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002
+
+#define RX_MPDU_INFO_7_ENCRYPT_TYPE_OFFSET 0x0000001c
+#define RX_MPDU_INFO_7_ENCRYPT_TYPE_LSB 2
+#define RX_MPDU_INFO_7_ENCRYPT_TYPE_MASK 0x0000003c
+
+#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c
+#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6
+#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0
+
+#define RX_MPDU_INFO_7_BSSID_HIT_OFFSET 0x0000001c
+#define RX_MPDU_INFO_7_BSSID_HIT_LSB 10
+#define RX_MPDU_INFO_7_BSSID_HIT_MASK 0x00000400
+
+#define RX_MPDU_INFO_7_BSSID_NUMBER_OFFSET 0x0000001c
+#define RX_MPDU_INFO_7_BSSID_NUMBER_LSB 11
+#define RX_MPDU_INFO_7_BSSID_NUMBER_MASK 0x00007800
+
+#define RX_MPDU_INFO_7_TID_OFFSET 0x0000001c
+#define RX_MPDU_INFO_7_TID_LSB 15
+#define RX_MPDU_INFO_7_TID_MASK 0x00078000
+
+#define RX_MPDU_INFO_7_RESERVED_7A_OFFSET 0x0000001c
+#define RX_MPDU_INFO_7_RESERVED_7A_LSB 19
+#define RX_MPDU_INFO_7_RESERVED_7A_MASK 0xfff80000
+
+#define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET 0x00000020
+#define RX_MPDU_INFO_8_PEER_META_DATA_LSB 0
+#define RX_MPDU_INFO_8_PEER_META_DATA_MASK 0xffffffff
+
+#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB 2
+#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+#define RX_MPDU_INFO_9_NDP_FRAME_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_NDP_FRAME_LSB 9
+#define RX_MPDU_INFO_9_NDP_FRAME_MASK 0x00000200
+
+#define RX_MPDU_INFO_9_PHY_ERR_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_PHY_ERR_LSB 10
+#define RX_MPDU_INFO_9_PHY_ERR_MASK 0x00000400
+
+#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_LSB 11
+#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800
+
+#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_LSB 12
+#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_MASK 0x00001000
+
+#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_LSB 13
+#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_MASK 0x00002000
+
+#define RX_MPDU_INFO_9_RESERVED_9A_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_RESERVED_9A_LSB 14
+#define RX_MPDU_INFO_9_RESERVED_9A_MASK 0x0000c000
+
+#define RX_MPDU_INFO_9_PHY_PPDU_ID_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_PHY_PPDU_ID_LSB 16
+#define RX_MPDU_INFO_9_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RX_MPDU_INFO_10_AST_INDEX_OFFSET 0x00000028
+#define RX_MPDU_INFO_10_AST_INDEX_LSB 0
+#define RX_MPDU_INFO_10_AST_INDEX_MASK 0x0000ffff
+
+#define RX_MPDU_INFO_10_SW_PEER_ID_OFFSET 0x00000028
+#define RX_MPDU_INFO_10_SW_PEER_ID_LSB 16
+#define RX_MPDU_INFO_10_SW_PEER_ID_MASK 0xffff0000
+
+#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB 0
+#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001
+
+#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_LSB 1
+#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_MASK 0x00000002
+
+#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB 2
+#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK 0x00000004
+
+#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB 3
+#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK 0x00000008
+
+#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB 4
+#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK 0x00000010
+
+#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB 5
+#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK 0x00000020
+
+#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB 6
+#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040
+
+#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB 7
+#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK 0x00000080
+
+#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_LSB 8
+#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_MASK 0x00000100
+
+#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB 9
+#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200
+
+#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_LSB 10
+#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00
+
+#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_LSB 14
+#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define RX_MPDU_INFO_11_RESERVED_11A_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_RESERVED_11A_LSB 15
+#define RX_MPDU_INFO_11_RESERVED_11A_MASK 0x00008000
+
+#define RX_MPDU_INFO_11_FR_DS_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_FR_DS_LSB 16
+#define RX_MPDU_INFO_11_FR_DS_MASK 0x00010000
+
+#define RX_MPDU_INFO_11_TO_DS_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_TO_DS_LSB 17
+#define RX_MPDU_INFO_11_TO_DS_MASK 0x00020000
+
+#define RX_MPDU_INFO_11_ENCRYPTED_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_ENCRYPTED_LSB 18
+#define RX_MPDU_INFO_11_ENCRYPTED_MASK 0x00040000
+
+#define RX_MPDU_INFO_11_MPDU_RETRY_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MPDU_RETRY_LSB 19
+#define RX_MPDU_INFO_11_MPDU_RETRY_MASK 0x00080000
+
+#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB 20
+#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000
+
+#define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB 0
+#define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK 0x000000ff
+
+#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB 8
+#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK 0x00000100
+
+#define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB 9
+#define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK 0x00000200
+
+#define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_DECAP_TYPE_LSB 10
+#define RX_MPDU_INFO_12_DECAP_TYPE_MASK 0x00000c00
+
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000
+
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000
+
+#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB 14
+#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000
+
+#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB 15
+#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000
+
+#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB 16
+#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK 0x0fff0000
+
+#define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_AMPDU_FLAG_LSB 28
+#define RX_MPDU_INFO_12_AMPDU_FLAG_MASK 0x10000000
+
+#define RX_MPDU_INFO_12_BAR_FRAME_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_BAR_FRAME_LSB 29
+#define RX_MPDU_INFO_12_BAR_FRAME_MASK 0x20000000
+
+#define RX_MPDU_INFO_12_RAW_MPDU_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_RAW_MPDU_LSB 30
+#define RX_MPDU_INFO_12_RAW_MPDU_MASK 0x40000000
+
+#define RX_MPDU_INFO_12_RESERVED_12_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_RESERVED_12_LSB 31
+#define RX_MPDU_INFO_12_RESERVED_12_MASK 0x80000000
+
+#define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_MPDU_LENGTH_LSB 0
+#define RX_MPDU_INFO_13_MPDU_LENGTH_MASK 0x00003fff
+
+#define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_FIRST_MPDU_LSB 14
+#define RX_MPDU_INFO_13_FIRST_MPDU_MASK 0x00004000
+
+#define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_MCAST_BCAST_LSB 15
+#define RX_MPDU_INFO_13_MCAST_BCAST_MASK 0x00008000
+
+#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB 16
+#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK 0x00010000
+
+#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB 17
+#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK 0x00020000
+
+#define RX_MPDU_INFO_13_POWER_MGMT_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_POWER_MGMT_LSB 18
+#define RX_MPDU_INFO_13_POWER_MGMT_MASK 0x00040000
+
+#define RX_MPDU_INFO_13_NON_QOS_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_NON_QOS_LSB 19
+#define RX_MPDU_INFO_13_NON_QOS_MASK 0x00080000
+
+#define RX_MPDU_INFO_13_NULL_DATA_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_NULL_DATA_LSB 20
+#define RX_MPDU_INFO_13_NULL_DATA_MASK 0x00100000
+
+#define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_MGMT_TYPE_LSB 21
+#define RX_MPDU_INFO_13_MGMT_TYPE_MASK 0x00200000
+
+#define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_CTRL_TYPE_LSB 22
+#define RX_MPDU_INFO_13_CTRL_TYPE_MASK 0x00400000
+
+#define RX_MPDU_INFO_13_MORE_DATA_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_MORE_DATA_LSB 23
+#define RX_MPDU_INFO_13_MORE_DATA_MASK 0x00800000
+
+#define RX_MPDU_INFO_13_EOSP_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_EOSP_LSB 24
+#define RX_MPDU_INFO_13_EOSP_MASK 0x01000000
+
+#define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB 25
+#define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK 0x02000000
+
+#define RX_MPDU_INFO_13_ORDER_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_ORDER_LSB 26
+#define RX_MPDU_INFO_13_ORDER_MASK 0x04000000
+
+#define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB 27
+#define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK 0x08000000
+
+#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB 28
+#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK 0x10000000
+
+#define RX_MPDU_INFO_13_DIRECTED_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_DIRECTED_LSB 29
+#define RX_MPDU_INFO_13_DIRECTED_MASK 0x20000000
+
+#define RX_MPDU_INFO_13_AMSDU_PRESENT_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_AMSDU_PRESENT_LSB 30
+#define RX_MPDU_INFO_13_AMSDU_PRESENT_MASK 0x40000000
+
+#define RX_MPDU_INFO_13_RESERVED_13_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_RESERVED_13_LSB 31
+#define RX_MPDU_INFO_13_RESERVED_13_MASK 0x80000000
+
+#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038
+#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB 0
+#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff
+
+#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET 0x00000038
+#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB 16
+#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK 0xffff0000
+
+#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c
+#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB 0
+#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK 0xffffffff
+
+#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET 0x00000040
+#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB 0
+#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK 0x0000ffff
+
+#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET 0x00000040
+#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB 16
+#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK 0xffff0000
+
+#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET 0x00000044
+#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB 0
+#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK 0xffffffff
+
+#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET 0x00000048
+#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB 0
+#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK 0xffffffff
+
+#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c
+#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB 0
+#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK 0x0000ffff
+
+#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c
+#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16
+#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000
+
+#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET 0x00000050
+#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB 0
+#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK 0xffffffff
+
+#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET 0x00000054
+#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB 0
+#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK 0x0000ffff
+
+#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054
+#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB 16
+#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000
+
+#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058
+#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB 0
+#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/rx_mpdu_link_ptr.h b/hw/wcn6450/v1/rx_mpdu_link_ptr.h
new file mode 100644
index 0000000..2abf815
--- /dev/null
+++ b/hw/wcn6450/v1/rx_mpdu_link_ptr.h
@@ -0,0 +1,51 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MPDU_LINK_PTR_H_
+#define _RX_MPDU_LINK_PTR_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+
+#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2
+
+struct rx_mpdu_link_ptr {
+ struct buffer_addr_info mpdu_link_desc_addr_info;
+};
+
+#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#endif
diff --git a/hw/wcn6450/v1/rx_mpdu_start.h b/hw/wcn6450/v1/rx_mpdu_start.h
new file mode 100644
index 0000000..6ba62e2
--- /dev/null
+++ b/hw/wcn6450/v1/rx_mpdu_start.h
@@ -0,0 +1,443 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MPDU_START_H_
+#define _RX_MPDU_START_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_mpdu_info.h"
+
+#define NUM_OF_DWORDS_RX_MPDU_START 23
+
+struct rx_mpdu_start {
+ struct rx_mpdu_info rx_mpdu_info_details;
+};
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000
+
+#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004
+#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00
+
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x01000000
+
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x00000008
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x02000000
+
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0xfc000000
+
+#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000c
+#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0
+#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff
+
+#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x00000010
+#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0
+#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff
+
+#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x00000014
+#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0
+#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff
+
+#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x00000018
+#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0
+#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff
+
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 0
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x00000001
+
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002
+
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 2
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c
+
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0
+
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 10
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x00000400
+
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 11
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x00007800
+
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_LSB 15
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_MASK 0x00078000
+
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 19
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff80000
+
+#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000020
+#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 2
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 9
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x00000200
+
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 10
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x00000400
+
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 11
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800
+
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 12
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x00001000
+
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 13
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x00002000
+
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 14
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x0000c000
+
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 16
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x00000028
+#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0
+#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x0000ffff
+
+#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x00000028
+#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16
+#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0xffff0000
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x00000002
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x00000004
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x00000008
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x00000010
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x00000020
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x00000080
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x00000100
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 15
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x00008000
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x00010000
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x00020000
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x00040000
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x00080000
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x000000ff
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x00000100
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x00000200
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x00000c00
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x0fff0000
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x10000000
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x20000000
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x40000000
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x80000000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 0
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 14
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x00004000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 15
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x00008000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 16
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x00010000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 17
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x00020000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 18
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x00040000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 19
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x00080000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 20
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x00100000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 21
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x00200000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 22
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x00400000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 23
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x00800000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_LSB 24
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x01000000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 25
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x02000000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_LSB 26
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x04000000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 27
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x08000000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 28
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x10000000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 29
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x20000000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 30
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x40000000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 31
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x80000000
+
+#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038
+#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0
+#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff
+
+#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x00000038
+#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16
+#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0xffff0000
+
+#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c
+#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 0
+#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff
+
+#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x00000040
+#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0
+#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x0000ffff
+
+#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x00000040
+#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16
+#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0xffff0000
+
+#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x00000044
+#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 0
+#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff
+
+#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x00000048
+#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0
+#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0xffffffff
+
+#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c
+#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 0
+#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff
+
+#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c
+#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16
+#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000
+
+#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x00000050
+#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0
+#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0xffffffff
+
+#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x00000054
+#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 0
+#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff
+
+#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054
+#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 16
+#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000
+
+#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058
+#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0
+#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/rx_msdu_desc_info.h b/hw/wcn6450/v1/rx_msdu_desc_info.h
new file mode 100644
index 0000000..085d111
--- /dev/null
+++ b/hw/wcn6450/v1/rx_msdu_desc_info.h
@@ -0,0 +1,127 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MSDU_DESC_INFO_H_
+#define _RX_MSDU_DESC_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 2
+
+struct rx_msdu_desc_info {
+ uint32_t first_msdu_in_mpdu_flag : 1,
+ last_msdu_in_mpdu_flag : 1,
+ msdu_continuation : 1,
+ msdu_length : 14,
+ reo_destination_indication : 5,
+ msdu_drop : 1,
+ sa_is_valid : 1,
+ sa_idx_timeout : 1,
+ da_is_valid : 1,
+ da_is_mcbc : 1,
+ da_idx_timeout : 1,
+ l3_header_padding_msb : 1,
+ tcp_udp_chksum_fail : 1,
+ ip_chksum_fail : 1,
+ raw_mpdu : 1;
+ uint32_t sa_idx_or_sw_peer_id_14_0 : 15,
+ mpdu_ast_idx_or_sw_peer_id_14_0 : 15,
+ fr_ds : 1,
+ to_ds : 1;
+};
+
+#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB 3
+#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+#define RX_MSDU_DESC_INFO_0_MSDU_DROP_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_MSDU_DROP_LSB 22
+#define RX_MSDU_DESC_INFO_0_MSDU_DROP_MASK 0x00400000
+
+#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_LSB 23
+#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK 0x00800000
+
+#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x01000000
+
+#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_LSB 25
+#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK 0x02000000
+
+#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_LSB 26
+#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x04000000
+
+#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x08000000
+
+#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_MASK 0x40000000
+
+#define RX_MSDU_DESC_INFO_0_RAW_MPDU_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_RAW_MPDU_LSB 31
+#define RX_MSDU_DESC_INFO_0_RAW_MPDU_MASK 0x80000000
+
+#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000004
+#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000004
+#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+#define RX_MSDU_DESC_INFO_1_FR_DS_OFFSET 0x00000004
+#define RX_MSDU_DESC_INFO_1_FR_DS_LSB 30
+#define RX_MSDU_DESC_INFO_1_FR_DS_MASK 0x40000000
+
+#define RX_MSDU_DESC_INFO_1_TO_DS_OFFSET 0x00000004
+#define RX_MSDU_DESC_INFO_1_TO_DS_LSB 31
+#define RX_MSDU_DESC_INFO_1_TO_DS_MASK 0x80000000
+
+#endif
diff --git a/hw/wcn6450/v1/rx_msdu_details.h b/hw/wcn6450/v1/rx_msdu_details.h
new file mode 100644
index 0000000..70f0aa0
--- /dev/null
+++ b/hw/wcn6450/v1/rx_msdu_details.h
@@ -0,0 +1,129 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MSDU_DETAILS_H_
+#define _RX_MSDU_DETAILS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+#include "rx_msdu_desc_info.h"
+
+#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4
+
+struct rx_msdu_details {
+ struct buffer_addr_info buffer_addr_info_details;
+ struct rx_msdu_desc_info rx_msdu_desc_info_details;
+};
+
+#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000
+
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000
+
+#endif
diff --git a/hw/wcn6450/v1/rx_msdu_end.h b/hw/wcn6450/v1/rx_msdu_end.h
new file mode 100644
index 0000000..03f1714
--- /dev/null
+++ b/hw/wcn6450/v1/rx_msdu_end.h
@@ -0,0 +1,322 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MSDU_END_H_
+#define _RX_MSDU_END_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_MSDU_END 17
+
+struct rx_msdu_end {
+ uint32_t rxpcu_mpdu_filter_in_category : 2,
+ sw_frame_group_id : 7,
+ reserved_0 : 7,
+ phy_ppdu_id : 16;
+ uint32_t ip_hdr_chksum : 16,
+ reported_mpdu_length : 14,
+ reserved_1a : 2;
+ uint32_t key_id_octet : 8,
+ cce_super_rule : 6,
+ cce_classify_not_done_truncate : 1,
+ cce_classify_not_done_cce_dis : 1,
+ cumulative_l3_checksum : 16;
+ uint32_t rule_indication_31_0 : 32;
+ uint32_t rule_indication_63_32 : 32;
+ uint32_t da_offset : 6,
+ sa_offset : 6,
+ da_offset_valid : 1,
+ sa_offset_valid : 1,
+ reserved_5a : 2,
+ l3_type : 16;
+ uint32_t ipv6_options_crc : 32;
+ uint32_t tcp_seq_number : 32;
+ uint32_t tcp_ack_number : 32;
+ uint32_t tcp_flag : 9,
+ lro_eligible : 1,
+ reserved_9a : 6,
+ window_size : 16;
+ uint32_t tcp_udp_chksum : 16,
+ sa_idx_timeout : 1,
+ da_idx_timeout : 1,
+ msdu_limit_error : 1,
+ flow_idx_timeout : 1,
+ flow_idx_invalid : 1,
+ wifi_parser_error : 1,
+ amsdu_parser_error : 1,
+ sa_is_valid : 1,
+ da_is_valid : 1,
+ da_is_mcbc : 1,
+ l3_header_padding : 2,
+ first_msdu : 1,
+ last_msdu : 1,
+ tcp_udp_chksum_fail : 1,
+ ip_chksum_fail : 1;
+ uint32_t sa_idx : 16,
+ da_idx_or_sw_peer_id : 16;
+ uint32_t msdu_drop : 1,
+ reo_destination_indication : 5,
+ flow_idx : 20,
+ reserved_12a : 6;
+ uint32_t fse_metadata : 32;
+ uint32_t cce_metadata : 16,
+ sa_sw_peer_id : 16;
+ uint32_t aggregation_count : 8,
+ flow_aggregation_continuation : 1,
+ fisa_timeout : 1,
+ reserved_15a : 22;
+ uint32_t cumulative_l4_checksum : 16,
+ cumulative_ip_length : 16;
+};
+
+#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000
+#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000
+#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB 2
+#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+#define RX_MSDU_END_0_RESERVED_0_OFFSET 0x00000000
+#define RX_MSDU_END_0_RESERVED_0_LSB 9
+#define RX_MSDU_END_0_RESERVED_0_MASK 0x0000fe00
+
+#define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_MSDU_END_0_PHY_PPDU_ID_LSB 16
+#define RX_MSDU_END_0_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET 0x00000004
+#define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB 0
+#define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK 0x0000ffff
+
+#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_OFFSET 0x00000004
+#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_LSB 16
+#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_MASK 0x3fff0000
+
+#define RX_MSDU_END_1_RESERVED_1A_OFFSET 0x00000004
+#define RX_MSDU_END_1_RESERVED_1A_LSB 30
+#define RX_MSDU_END_1_RESERVED_1A_MASK 0xc0000000
+
+#define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET 0x00000008
+#define RX_MSDU_END_2_KEY_ID_OCTET_LSB 0
+#define RX_MSDU_END_2_KEY_ID_OCTET_MASK 0x000000ff
+
+#define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET 0x00000008
+#define RX_MSDU_END_2_CCE_SUPER_RULE_LSB 8
+#define RX_MSDU_END_2_CCE_SUPER_RULE_MASK 0x00003f00
+
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000
+
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000
+
+#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_OFFSET 0x00000008
+#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_LSB 16
+#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_MASK 0xffff0000
+
+#define RX_MSDU_END_3_RULE_INDICATION_31_0_OFFSET 0x0000000c
+#define RX_MSDU_END_3_RULE_INDICATION_31_0_LSB 0
+#define RX_MSDU_END_3_RULE_INDICATION_31_0_MASK 0xffffffff
+
+#define RX_MSDU_END_4_RULE_INDICATION_63_32_OFFSET 0x00000010
+#define RX_MSDU_END_4_RULE_INDICATION_63_32_LSB 0
+#define RX_MSDU_END_4_RULE_INDICATION_63_32_MASK 0xffffffff
+
+#define RX_MSDU_END_5_DA_OFFSET_OFFSET 0x00000014
+#define RX_MSDU_END_5_DA_OFFSET_LSB 0
+#define RX_MSDU_END_5_DA_OFFSET_MASK 0x0000003f
+
+#define RX_MSDU_END_5_SA_OFFSET_OFFSET 0x00000014
+#define RX_MSDU_END_5_SA_OFFSET_LSB 6
+#define RX_MSDU_END_5_SA_OFFSET_MASK 0x00000fc0
+
+#define RX_MSDU_END_5_DA_OFFSET_VALID_OFFSET 0x00000014
+#define RX_MSDU_END_5_DA_OFFSET_VALID_LSB 12
+#define RX_MSDU_END_5_DA_OFFSET_VALID_MASK 0x00001000
+
+#define RX_MSDU_END_5_SA_OFFSET_VALID_OFFSET 0x00000014
+#define RX_MSDU_END_5_SA_OFFSET_VALID_LSB 13
+#define RX_MSDU_END_5_SA_OFFSET_VALID_MASK 0x00002000
+
+#define RX_MSDU_END_5_RESERVED_5A_OFFSET 0x00000014
+#define RX_MSDU_END_5_RESERVED_5A_LSB 14
+#define RX_MSDU_END_5_RESERVED_5A_MASK 0x0000c000
+
+#define RX_MSDU_END_5_L3_TYPE_OFFSET 0x00000014
+#define RX_MSDU_END_5_L3_TYPE_LSB 16
+#define RX_MSDU_END_5_L3_TYPE_MASK 0xffff0000
+
+#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET 0x00000018
+#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB 0
+#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK 0xffffffff
+
+#define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET 0x0000001c
+#define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB 0
+#define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK 0xffffffff
+
+#define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET 0x00000020
+#define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB 0
+#define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK 0xffffffff
+
+#define RX_MSDU_END_9_TCP_FLAG_OFFSET 0x00000024
+#define RX_MSDU_END_9_TCP_FLAG_LSB 0
+#define RX_MSDU_END_9_TCP_FLAG_MASK 0x000001ff
+
+#define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET 0x00000024
+#define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9
+#define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200
+
+#define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024
+#define RX_MSDU_END_9_RESERVED_9A_LSB 10
+#define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000fc00
+
+#define RX_MSDU_END_9_WINDOW_SIZE_OFFSET 0x00000024
+#define RX_MSDU_END_9_WINDOW_SIZE_LSB 16
+#define RX_MSDU_END_9_WINDOW_SIZE_MASK 0xffff0000
+
+#define RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET 0x00000028
+#define RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB 0
+#define RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK 0x0000ffff
+
+#define RX_MSDU_END_10_SA_IDX_TIMEOUT_OFFSET 0x00000028
+#define RX_MSDU_END_10_SA_IDX_TIMEOUT_LSB 16
+#define RX_MSDU_END_10_SA_IDX_TIMEOUT_MASK 0x00010000
+
+#define RX_MSDU_END_10_DA_IDX_TIMEOUT_OFFSET 0x00000028
+#define RX_MSDU_END_10_DA_IDX_TIMEOUT_LSB 17
+#define RX_MSDU_END_10_DA_IDX_TIMEOUT_MASK 0x00020000
+
+#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_OFFSET 0x00000028
+#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_LSB 18
+#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_MASK 0x00040000
+
+#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET 0x00000028
+#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB 19
+#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK 0x00080000
+
+#define RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET 0x00000028
+#define RX_MSDU_END_10_FLOW_IDX_INVALID_LSB 20
+#define RX_MSDU_END_10_FLOW_IDX_INVALID_MASK 0x00100000
+
+#define RX_MSDU_END_10_WIFI_PARSER_ERROR_OFFSET 0x00000028
+#define RX_MSDU_END_10_WIFI_PARSER_ERROR_LSB 21
+#define RX_MSDU_END_10_WIFI_PARSER_ERROR_MASK 0x00200000
+
+#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_OFFSET 0x00000028
+#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_LSB 22
+#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_MASK 0x00400000
+
+#define RX_MSDU_END_10_SA_IS_VALID_OFFSET 0x00000028
+#define RX_MSDU_END_10_SA_IS_VALID_LSB 23
+#define RX_MSDU_END_10_SA_IS_VALID_MASK 0x00800000
+
+#define RX_MSDU_END_10_DA_IS_VALID_OFFSET 0x00000028
+#define RX_MSDU_END_10_DA_IS_VALID_LSB 24
+#define RX_MSDU_END_10_DA_IS_VALID_MASK 0x01000000
+
+#define RX_MSDU_END_10_DA_IS_MCBC_OFFSET 0x00000028
+#define RX_MSDU_END_10_DA_IS_MCBC_LSB 25
+#define RX_MSDU_END_10_DA_IS_MCBC_MASK 0x02000000
+
+#define RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET 0x00000028
+#define RX_MSDU_END_10_L3_HEADER_PADDING_LSB 26
+#define RX_MSDU_END_10_L3_HEADER_PADDING_MASK 0x0c000000
+
+#define RX_MSDU_END_10_FIRST_MSDU_OFFSET 0x00000028
+#define RX_MSDU_END_10_FIRST_MSDU_LSB 28
+#define RX_MSDU_END_10_FIRST_MSDU_MASK 0x10000000
+
+#define RX_MSDU_END_10_LAST_MSDU_OFFSET 0x00000028
+#define RX_MSDU_END_10_LAST_MSDU_LSB 29
+#define RX_MSDU_END_10_LAST_MSDU_MASK 0x20000000
+
+#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028
+#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_MASK 0x40000000
+
+#define RX_MSDU_END_10_IP_CHKSUM_FAIL_OFFSET 0x00000028
+#define RX_MSDU_END_10_IP_CHKSUM_FAIL_LSB 31
+#define RX_MSDU_END_10_IP_CHKSUM_FAIL_MASK 0x80000000
+
+#define RX_MSDU_END_11_SA_IDX_OFFSET 0x0000002c
+#define RX_MSDU_END_11_SA_IDX_LSB 0
+#define RX_MSDU_END_11_SA_IDX_MASK 0x0000ffff
+
+#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000002c
+#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB 16
+#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000
+
+#define RX_MSDU_END_12_MSDU_DROP_OFFSET 0x00000030
+#define RX_MSDU_END_12_MSDU_DROP_LSB 0
+#define RX_MSDU_END_12_MSDU_DROP_MASK 0x00000001
+
+#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_OFFSET 0x00000030
+#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_LSB 1
+#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_MASK 0x0000003e
+
+#define RX_MSDU_END_12_FLOW_IDX_OFFSET 0x00000030
+#define RX_MSDU_END_12_FLOW_IDX_LSB 6
+#define RX_MSDU_END_12_FLOW_IDX_MASK 0x03ffffc0
+
+#define RX_MSDU_END_12_RESERVED_12A_OFFSET 0x00000030
+#define RX_MSDU_END_12_RESERVED_12A_LSB 26
+#define RX_MSDU_END_12_RESERVED_12A_MASK 0xfc000000
+
+#define RX_MSDU_END_13_FSE_METADATA_OFFSET 0x00000034
+#define RX_MSDU_END_13_FSE_METADATA_LSB 0
+#define RX_MSDU_END_13_FSE_METADATA_MASK 0xffffffff
+
+#define RX_MSDU_END_14_CCE_METADATA_OFFSET 0x00000038
+#define RX_MSDU_END_14_CCE_METADATA_LSB 0
+#define RX_MSDU_END_14_CCE_METADATA_MASK 0x0000ffff
+
+#define RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET 0x00000038
+#define RX_MSDU_END_14_SA_SW_PEER_ID_LSB 16
+#define RX_MSDU_END_14_SA_SW_PEER_ID_MASK 0xffff0000
+
+#define RX_MSDU_END_15_AGGREGATION_COUNT_OFFSET 0x0000003c
+#define RX_MSDU_END_15_AGGREGATION_COUNT_LSB 0
+#define RX_MSDU_END_15_AGGREGATION_COUNT_MASK 0x000000ff
+
+#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000003c
+#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_LSB 8
+#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_MASK 0x00000100
+
+#define RX_MSDU_END_15_FISA_TIMEOUT_OFFSET 0x0000003c
+#define RX_MSDU_END_15_FISA_TIMEOUT_LSB 9
+#define RX_MSDU_END_15_FISA_TIMEOUT_MASK 0x00000200
+
+#define RX_MSDU_END_15_RESERVED_15A_OFFSET 0x0000003c
+#define RX_MSDU_END_15_RESERVED_15A_LSB 10
+#define RX_MSDU_END_15_RESERVED_15A_MASK 0xfffffc00
+
+#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000040
+#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_LSB 0
+#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff
+
+#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_OFFSET 0x00000040
+#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_LSB 16
+#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_MASK 0xffff0000
+
+#endif
diff --git a/hw/wcn6450/v1/rx_msdu_link.h b/hw/wcn6450/v1/rx_msdu_link.h
new file mode 100644
index 0000000..f068d4b
--- /dev/null
+++ b/hw/wcn6450/v1/rx_msdu_link.h
@@ -0,0 +1,659 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MSDU_LINK_H_
+#define _RX_MSDU_LINK_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_descriptor_header.h"
+#include "buffer_addr_info.h"
+#include "rx_msdu_details.h"
+
+#define NUM_OF_DWORDS_RX_MSDU_LINK 32
+
+struct rx_msdu_link {
+ struct uniform_descriptor_header descriptor_header;
+ struct buffer_addr_info next_msdu_link_desc_addr_info;
+ uint32_t receive_queue_number : 16,
+ first_rx_msdu_link_struct : 1,
+ reserved_3a : 15;
+ uint32_t pn_31_0 : 32;
+ uint32_t pn_63_32 : 32;
+ uint32_t pn_95_64 : 32;
+ uint32_t pn_127_96 : 32;
+ struct rx_msdu_details msdu_0;
+ struct rx_msdu_details msdu_1;
+ struct rx_msdu_details msdu_2;
+ struct rx_msdu_details msdu_3;
+ struct rx_msdu_details msdu_4;
+ struct rx_msdu_details msdu_5;
+};
+
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_LSB 0
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
+
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
+
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00
+
+#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004
+#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c
+#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_LSB 0
+#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff
+
+#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c
+#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_LSB 16
+#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000
+
+#define RX_MSDU_LINK_3_RESERVED_3A_OFFSET 0x0000000c
+#define RX_MSDU_LINK_3_RESERVED_3A_LSB 17
+#define RX_MSDU_LINK_3_RESERVED_3A_MASK 0xfffe0000
+
+#define RX_MSDU_LINK_4_PN_31_0_OFFSET 0x00000010
+#define RX_MSDU_LINK_4_PN_31_0_LSB 0
+#define RX_MSDU_LINK_4_PN_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_5_PN_63_32_OFFSET 0x00000014
+#define RX_MSDU_LINK_5_PN_63_32_LSB 0
+#define RX_MSDU_LINK_5_PN_63_32_MASK 0xffffffff
+
+#define RX_MSDU_LINK_6_PN_95_64_OFFSET 0x00000018
+#define RX_MSDU_LINK_6_PN_95_64_LSB 0
+#define RX_MSDU_LINK_6_PN_95_64_MASK 0xffffffff
+
+#define RX_MSDU_LINK_7_PN_127_96_OFFSET 0x0000001c
+#define RX_MSDU_LINK_7_PN_127_96_LSB 0
+#define RX_MSDU_LINK_7_PN_127_96_MASK 0xffffffff
+
+#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020
+#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000002c
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000002c
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000002c
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000
+
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000002c
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000
+
+#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030
+#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000003c
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000003c
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000003c
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000
+
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000003c
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000
+
+#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040
+#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000004c
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000004c
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000004c
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000
+
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000004c
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000
+
+#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050
+#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000005c
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000005c
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000005c
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000
+
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000005c
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000
+
+#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060
+#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000006c
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000006c
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000006c
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000
+
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000006c
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000
+
+#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070
+#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000007c
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000007c
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000007c
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000
+
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000007c
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000
+
+#endif
diff --git a/hw/wcn6450/v1/rx_msdu_start.h b/hw/wcn6450/v1/rx_msdu_start.h
new file mode 100644
index 0000000..44aec32
--- /dev/null
+++ b/hw/wcn6450/v1/rx_msdu_start.h
@@ -0,0 +1,232 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MSDU_START_H_
+#define _RX_MSDU_START_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_MSDU_START 9
+
+struct rx_msdu_start {
+ uint32_t rxpcu_mpdu_filter_in_category : 2,
+ sw_frame_group_id : 7,
+ reserved_0 : 7,
+ phy_ppdu_id : 16;
+ uint32_t msdu_length : 14,
+ reserved_1a : 1,
+ ipsec_esp : 1,
+ l3_offset : 7,
+ ipsec_ah : 1,
+ l4_offset : 8;
+ uint32_t msdu_number : 8,
+ decap_format : 2,
+ ipv4_proto : 1,
+ ipv6_proto : 1,
+ tcp_proto : 1,
+ udp_proto : 1,
+ ip_frag : 1,
+ tcp_only_ack : 1,
+ da_is_bcast_mcast : 1,
+ toeplitz_hash_sel : 2,
+ ip_fixed_header_valid : 1,
+ ip_extn_header_valid : 1,
+ tcp_udp_header_valid : 1,
+ mesh_control_present : 1,
+ ldpc : 1,
+ ip4_protocol_ip6_next_header : 8;
+ uint32_t toeplitz_hash_2_or_4 : 32;
+ uint32_t flow_id_toeplitz : 32;
+ uint32_t user_rssi : 8,
+ pkt_type : 4,
+ stbc : 1,
+ sgi : 2,
+ rate_mcs : 4,
+ receive_bandwidth : 2,
+ reception_type : 3,
+ mimo_ss_bitmap : 8;
+ uint32_t ppdu_start_timestamp : 32;
+ uint32_t sw_phy_meta_data : 32;
+ uint32_t vlan_ctag_ci : 16,
+ vlan_stag_ci : 16;
+};
+
+#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000
+#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000
+#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_LSB 2
+#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+#define RX_MSDU_START_0_RESERVED_0_OFFSET 0x00000000
+#define RX_MSDU_START_0_RESERVED_0_LSB 9
+#define RX_MSDU_START_0_RESERVED_0_MASK 0x0000fe00
+
+#define RX_MSDU_START_0_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_MSDU_START_0_PHY_PPDU_ID_LSB 16
+#define RX_MSDU_START_0_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RX_MSDU_START_1_MSDU_LENGTH_OFFSET 0x00000004
+#define RX_MSDU_START_1_MSDU_LENGTH_LSB 0
+#define RX_MSDU_START_1_MSDU_LENGTH_MASK 0x00003fff
+
+#define RX_MSDU_START_1_RESERVED_1A_OFFSET 0x00000004
+#define RX_MSDU_START_1_RESERVED_1A_LSB 14
+#define RX_MSDU_START_1_RESERVED_1A_MASK 0x00004000
+
+#define RX_MSDU_START_1_IPSEC_ESP_OFFSET 0x00000004
+#define RX_MSDU_START_1_IPSEC_ESP_LSB 15
+#define RX_MSDU_START_1_IPSEC_ESP_MASK 0x00008000
+
+#define RX_MSDU_START_1_L3_OFFSET_OFFSET 0x00000004
+#define RX_MSDU_START_1_L3_OFFSET_LSB 16
+#define RX_MSDU_START_1_L3_OFFSET_MASK 0x007f0000
+
+#define RX_MSDU_START_1_IPSEC_AH_OFFSET 0x00000004
+#define RX_MSDU_START_1_IPSEC_AH_LSB 23
+#define RX_MSDU_START_1_IPSEC_AH_MASK 0x00800000
+
+#define RX_MSDU_START_1_L4_OFFSET_OFFSET 0x00000004
+#define RX_MSDU_START_1_L4_OFFSET_LSB 24
+#define RX_MSDU_START_1_L4_OFFSET_MASK 0xff000000
+
+#define RX_MSDU_START_2_MSDU_NUMBER_OFFSET 0x00000008
+#define RX_MSDU_START_2_MSDU_NUMBER_LSB 0
+#define RX_MSDU_START_2_MSDU_NUMBER_MASK 0x000000ff
+
+#define RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008
+#define RX_MSDU_START_2_DECAP_FORMAT_LSB 8
+#define RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300
+
+#define RX_MSDU_START_2_IPV4_PROTO_OFFSET 0x00000008
+#define RX_MSDU_START_2_IPV4_PROTO_LSB 10
+#define RX_MSDU_START_2_IPV4_PROTO_MASK 0x00000400
+
+#define RX_MSDU_START_2_IPV6_PROTO_OFFSET 0x00000008
+#define RX_MSDU_START_2_IPV6_PROTO_LSB 11
+#define RX_MSDU_START_2_IPV6_PROTO_MASK 0x00000800
+
+#define RX_MSDU_START_2_TCP_PROTO_OFFSET 0x00000008
+#define RX_MSDU_START_2_TCP_PROTO_LSB 12
+#define RX_MSDU_START_2_TCP_PROTO_MASK 0x00001000
+
+#define RX_MSDU_START_2_UDP_PROTO_OFFSET 0x00000008
+#define RX_MSDU_START_2_UDP_PROTO_LSB 13
+#define RX_MSDU_START_2_UDP_PROTO_MASK 0x00002000
+
+#define RX_MSDU_START_2_IP_FRAG_OFFSET 0x00000008
+#define RX_MSDU_START_2_IP_FRAG_LSB 14
+#define RX_MSDU_START_2_IP_FRAG_MASK 0x00004000
+
+#define RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET 0x00000008
+#define RX_MSDU_START_2_TCP_ONLY_ACK_LSB 15
+#define RX_MSDU_START_2_TCP_ONLY_ACK_MASK 0x00008000
+
+#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_OFFSET 0x00000008
+#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_LSB 16
+#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_MASK 0x00010000
+
+#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_OFFSET 0x00000008
+#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_LSB 17
+#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_MASK 0x00060000
+
+#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_OFFSET 0x00000008
+#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_LSB 19
+#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_MASK 0x00080000
+
+#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_OFFSET 0x00000008
+#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_LSB 20
+#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_MASK 0x00100000
+
+#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_OFFSET 0x00000008
+#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_LSB 21
+#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_MASK 0x00200000
+
+#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_OFFSET 0x00000008
+#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_LSB 22
+#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_MASK 0x00400000
+
+#define RX_MSDU_START_2_LDPC_OFFSET 0x00000008
+#define RX_MSDU_START_2_LDPC_LSB 23
+#define RX_MSDU_START_2_LDPC_MASK 0x00800000
+
+#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x00000008
+#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24
+#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff000000
+
+#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000c
+#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_LSB 0
+#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff
+
+#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET 0x00000010
+#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB 0
+#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK 0xffffffff
+
+#define RX_MSDU_START_5_USER_RSSI_OFFSET 0x00000014
+#define RX_MSDU_START_5_USER_RSSI_LSB 0
+#define RX_MSDU_START_5_USER_RSSI_MASK 0x000000ff
+
+#define RX_MSDU_START_5_PKT_TYPE_OFFSET 0x00000014
+#define RX_MSDU_START_5_PKT_TYPE_LSB 8
+#define RX_MSDU_START_5_PKT_TYPE_MASK 0x00000f00
+
+#define RX_MSDU_START_5_STBC_OFFSET 0x00000014
+#define RX_MSDU_START_5_STBC_LSB 12
+#define RX_MSDU_START_5_STBC_MASK 0x00001000
+
+#define RX_MSDU_START_5_SGI_OFFSET 0x00000014
+#define RX_MSDU_START_5_SGI_LSB 13
+#define RX_MSDU_START_5_SGI_MASK 0x00006000
+
+#define RX_MSDU_START_5_RATE_MCS_OFFSET 0x00000014
+#define RX_MSDU_START_5_RATE_MCS_LSB 15
+#define RX_MSDU_START_5_RATE_MCS_MASK 0x00078000
+
+#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET 0x00000014
+#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB 19
+#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK 0x00180000
+
+#define RX_MSDU_START_5_RECEPTION_TYPE_OFFSET 0x00000014
+#define RX_MSDU_START_5_RECEPTION_TYPE_LSB 21
+#define RX_MSDU_START_5_RECEPTION_TYPE_MASK 0x00e00000
+
+#define RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET 0x00000014
+#define RX_MSDU_START_5_MIMO_SS_BITMAP_LSB 24
+#define RX_MSDU_START_5_MIMO_SS_BITMAP_MASK 0xff000000
+
+#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_OFFSET 0x00000018
+#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_LSB 0
+#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_MASK 0xffffffff
+
+#define RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET 0x0000001c
+#define RX_MSDU_START_7_SW_PHY_META_DATA_LSB 0
+#define RX_MSDU_START_7_SW_PHY_META_DATA_MASK 0xffffffff
+
+#define RX_MSDU_START_8_VLAN_CTAG_CI_OFFSET 0x00000020
+#define RX_MSDU_START_8_VLAN_CTAG_CI_LSB 0
+#define RX_MSDU_START_8_VLAN_CTAG_CI_MASK 0x0000ffff
+
+#define RX_MSDU_START_8_VLAN_STAG_CI_OFFSET 0x00000020
+#define RX_MSDU_START_8_VLAN_STAG_CI_LSB 16
+#define RX_MSDU_START_8_VLAN_STAG_CI_MASK 0xffff0000
+
+#endif
diff --git a/hw/wcn6450/v1/rx_ppdu_end_user_stats.h b/hw/wcn6450/v1/rx_ppdu_end_user_stats.h
new file mode 100644
index 0000000..f7b1ed9
--- /dev/null
+++ b/hw/wcn6450/v1/rx_ppdu_end_user_stats.h
@@ -0,0 +1,406 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_PPDU_END_USER_STATS_H_
+#define _RX_PPDU_END_USER_STATS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_rxpcu_classification_overview.h"
+
+#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 23
+
+struct rx_ppdu_end_user_stats {
+ struct rx_rxpcu_classification_overview rxpcu_classification_details;
+ uint32_t sta_full_aid : 13,
+ mcs : 4,
+ nss : 3,
+ ofdma_info_valid : 1,
+ dl_ofdma_ru_start_index : 7,
+ reserved_1a : 4;
+ uint32_t dl_ofdma_ru_width : 7,
+ reserved_2a : 1,
+ user_receive_quality : 8,
+ mpdu_cnt_fcs_err : 10,
+ wbm2rxdma_buf_source_used : 1,
+ fw2rxdma_buf_source_used : 1,
+ sw2rxdma_buf_source_used : 1,
+ reserved_2b : 3;
+ uint32_t mpdu_cnt_fcs_ok : 9,
+ frame_control_info_valid : 1,
+ qos_control_info_valid : 1,
+ ht_control_info_valid : 1,
+ data_sequence_control_info_valid: 1,
+ ht_control_info_null_valid : 1,
+ reserved_3a : 2,
+ rxdma2reo_ring_used : 1,
+ rxdma2fw_ring_used : 1,
+ rxdma2sw_ring_used : 1,
+ rxdma_release_ring_used : 1,
+ ht_control_field_pkt_type : 4,
+ reserved_3b : 8;
+ uint32_t ast_index : 16,
+ frame_control_field : 16;
+ uint32_t first_data_seq_ctrl : 16,
+ qos_control_field : 16;
+ uint32_t ht_control_field : 32;
+ uint32_t fcs_ok_bitmap_31_0 : 32;
+ uint32_t fcs_ok_bitmap_63_32 : 32;
+ uint32_t udp_msdu_count : 16,
+ tcp_msdu_count : 16;
+ uint32_t other_msdu_count : 16,
+ tcp_ack_msdu_count : 16;
+ uint32_t sw_response_reference_ptr : 32;
+ uint32_t received_qos_data_tid_bitmap : 16,
+ received_qos_data_tid_eosp_bitmap: 16;
+ uint32_t qosctrl_15_8_tid0 : 8,
+ qosctrl_15_8_tid1 : 8,
+ qosctrl_15_8_tid2 : 8,
+ qosctrl_15_8_tid3 : 8;
+ uint32_t qosctrl_15_8_tid4 : 8,
+ qosctrl_15_8_tid5 : 8,
+ qosctrl_15_8_tid6 : 8,
+ qosctrl_15_8_tid7 : 8;
+ uint32_t qosctrl_15_8_tid8 : 8,
+ qosctrl_15_8_tid9 : 8,
+ qosctrl_15_8_tid10 : 8,
+ qosctrl_15_8_tid11 : 8;
+ uint32_t qosctrl_15_8_tid12 : 8,
+ qosctrl_15_8_tid13 : 8,
+ qosctrl_15_8_tid14 : 8,
+ qosctrl_15_8_tid15 : 8;
+ uint32_t mpdu_ok_byte_count : 25,
+ ampdu_delim_ok_count_6_0 : 7;
+ uint32_t ampdu_delim_err_count : 25,
+ ampdu_delim_ok_count_13_7 : 7;
+ uint32_t mpdu_err_byte_count : 25,
+ ampdu_delim_ok_count_20_14 : 7;
+ uint32_t non_consecutive_delimiter_err : 16,
+ reserved_20a : 16;
+ uint32_t ht_control_null_field : 32;
+ uint32_t sw_response_reference_ptr_ext : 32;
+};
+
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001
+
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
+
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004
+
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
+
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010
+
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
+
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040
+
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000ff80
+
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_LSB 0
+#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_MASK 0x00001fff
+
+#define RX_PPDU_END_USER_STATS_1_MCS_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_1_MCS_LSB 13
+#define RX_PPDU_END_USER_STATS_1_MCS_MASK 0x0001e000
+
+#define RX_PPDU_END_USER_STATS_1_NSS_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_1_NSS_LSB 17
+#define RX_PPDU_END_USER_STATS_1_NSS_MASK 0x000e0000
+
+#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_LSB 20
+#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_MASK 0x00100000
+
+#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_LSB 21
+#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_MASK 0x0fe00000
+
+#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_LSB 28
+#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_MASK 0xf0000000
+
+#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_LSB 0
+#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_MASK 0x0000007f
+
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_LSB 7
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_MASK 0x00000080
+
+#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_LSB 8
+#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_MASK 0x0000ff00
+
+#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_LSB 16
+#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_MASK 0x03ff0000
+
+#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_LSB 26
+#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_MASK 0x04000000
+
+#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_LSB 27
+#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_MASK 0x08000000
+
+#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_LSB 28
+#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_MASK 0x10000000
+
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_LSB 29
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_MASK 0xe0000000
+
+#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_LSB 0
+#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_MASK 0x000001ff
+
+#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_LSB 9
+#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_MASK 0x00000200
+
+#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_LSB 10
+#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_MASK 0x00000400
+
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_LSB 11
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_MASK 0x00000800
+
+#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 12
+#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x00001000
+
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_LSB 13
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_MASK 0x00002000
+
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_LSB 14
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_MASK 0x0000c000
+
+#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_LSB 16
+#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_MASK 0x00010000
+
+#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_LSB 17
+#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_MASK 0x00020000
+
+#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_LSB 18
+#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_MASK 0x00040000
+
+#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_LSB 19
+#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_MASK 0x00080000
+
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_LSB 20
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x00f00000
+
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_LSB 24
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_MASK 0xff000000
+
+#define RX_PPDU_END_USER_STATS_4_AST_INDEX_OFFSET 0x00000010
+#define RX_PPDU_END_USER_STATS_4_AST_INDEX_LSB 0
+#define RX_PPDU_END_USER_STATS_4_AST_INDEX_MASK 0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_OFFSET 0x00000010
+#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_LSB 16
+#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_OFFSET 0x00000014
+#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_LSB 0
+#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_OFFSET 0x00000014
+#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_LSB 16
+#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_OFFSET 0x00000018
+#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_LSB 0
+#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_OFFSET 0x0000001c
+#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_LSB 0
+#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_OFFSET 0x00000020
+#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_LSB 0
+#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_OFFSET 0x00000024
+#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_LSB 0
+#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_MASK 0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_OFFSET 0x00000024
+#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_LSB 16
+#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_OFFSET 0x00000028
+#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_LSB 0
+#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_MASK 0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_OFFSET 0x00000028
+#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_LSB 16
+#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000002c
+#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_LSB 0
+#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x00000030
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x00000030
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_OFFSET 0x00000034
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_LSB 0
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_MASK 0x000000ff
+
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_OFFSET 0x00000034
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_LSB 8
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_MASK 0x0000ff00
+
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_OFFSET 0x00000034
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_LSB 16
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_MASK 0x00ff0000
+
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_OFFSET 0x00000034
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_LSB 24
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_MASK 0xff000000
+
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_OFFSET 0x00000038
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_LSB 0
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_MASK 0x000000ff
+
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_OFFSET 0x00000038
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_LSB 8
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_MASK 0x0000ff00
+
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_OFFSET 0x00000038
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_LSB 16
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_MASK 0x00ff0000
+
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_OFFSET 0x00000038
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_LSB 24
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_MASK 0xff000000
+
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_OFFSET 0x0000003c
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_LSB 0
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_MASK 0x000000ff
+
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_OFFSET 0x0000003c
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_LSB 8
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_MASK 0x0000ff00
+
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_OFFSET 0x0000003c
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_LSB 16
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_MASK 0x00ff0000
+
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_OFFSET 0x0000003c
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_LSB 24
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_MASK 0xff000000
+
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_OFFSET 0x00000040
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_LSB 0
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_MASK 0x000000ff
+
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_OFFSET 0x00000040
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_LSB 8
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_MASK 0x0000ff00
+
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_OFFSET 0x00000040
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_LSB 16
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_MASK 0x00ff0000
+
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_OFFSET 0x00000040
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_LSB 24
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_MASK 0xff000000
+
+#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_OFFSET 0x00000044
+#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_LSB 0
+#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff
+
+#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x00000044
+#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_LSB 25
+#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe000000
+
+#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_OFFSET 0x00000048
+#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_LSB 0
+#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_MASK 0x01ffffff
+
+#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x00000048
+#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_LSB 25
+#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_MASK 0xfe000000
+
+#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000004c
+#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_LSB 0
+#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff
+
+#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000004c
+#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_LSB 25
+#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe000000
+
+#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x00000050
+#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0
+#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_OFFSET 0x00000050
+#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_LSB 16
+#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_OFFSET 0x00000054
+#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_LSB 0
+#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x00000058
+#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0
+#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/rx_ppdu_end_user_stats_ext.h b/hw/wcn6450/v1/rx_ppdu_end_user_stats_ext.h
new file mode 100644
index 0000000..15a74c9
--- /dev/null
+++ b/hw/wcn6450/v1/rx_ppdu_end_user_stats_ext.h
@@ -0,0 +1,101 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_PPDU_END_USER_STATS_EXT_H_
+#define _RX_PPDU_END_USER_STATS_EXT_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_rxpcu_classification_overview.h"
+
+#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 7
+
+struct rx_ppdu_end_user_stats_ext {
+ struct rx_rxpcu_classification_overview rxpcu_classification_details;
+ uint32_t fcs_ok_bitmap_95_64 : 32;
+ uint32_t fcs_ok_bitmap_127_96 : 32;
+ uint32_t fcs_ok_bitmap_159_128 : 32;
+ uint32_t fcs_ok_bitmap_191_160 : 32;
+ uint32_t fcs_ok_bitmap_223_192 : 32;
+ uint32_t fcs_ok_bitmap_255_224 : 32;
+};
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000ff80
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_OFFSET 0x00000010
+#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_OFFSET 0x00000014
+#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_OFFSET 0x00000018
+#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/rx_ppdu_start.h b/hw/wcn6450/v1/rx_ppdu_start.h
new file mode 100644
index 0000000..3873d3b
--- /dev/null
+++ b/hw/wcn6450/v1/rx_ppdu_start.h
@@ -0,0 +1,52 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_PPDU_START_H_
+#define _RX_PPDU_START_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_PPDU_START 3
+
+struct rx_ppdu_start {
+ uint32_t phy_ppdu_id : 16,
+ reserved_15 : 16;
+ uint32_t sw_phy_meta_data : 32;
+ uint32_t ppdu_start_timestamp : 32;
+};
+
+#define RX_PPDU_START_0_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_PPDU_START_0_PHY_PPDU_ID_LSB 0
+#define RX_PPDU_START_0_PHY_PPDU_ID_MASK 0x0000ffff
+
+#define RX_PPDU_START_0_RESERVED_15_OFFSET 0x00000000
+#define RX_PPDU_START_0_RESERVED_15_LSB 16
+#define RX_PPDU_START_0_RESERVED_15_MASK 0xffff0000
+
+#define RX_PPDU_START_1_SW_PHY_META_DATA_OFFSET 0x00000004
+#define RX_PPDU_START_1_SW_PHY_META_DATA_LSB 0
+#define RX_PPDU_START_1_SW_PHY_META_DATA_MASK 0xffffffff
+
+#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_OFFSET 0x00000008
+#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_LSB 0
+#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/rx_ppdu_start_user_info.h b/hw/wcn6450/v1/rx_ppdu_start_user_info.h
new file mode 100644
index 0000000..149db67
--- /dev/null
+++ b/hw/wcn6450/v1/rx_ppdu_start_user_info.h
@@ -0,0 +1,95 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_PPDU_START_USER_INFO_H_
+#define _RX_PPDU_START_USER_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "receive_user_info.h"
+
+#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 3
+
+struct rx_ppdu_start_user_info {
+ struct receive_user_info receive_user_info_details;
+};
+
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff
+
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000
+
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000
+
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000
+
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000
+
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f
+
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030
+
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 6
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000c0
+
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00
+
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_LSB 16
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_MASK 0x00ff0000
+
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_LSB 24
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_MASK 0x7f000000
+
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_LSB 31
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_MASK 0x80000000
+
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 0
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00000001
+
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_LSB 1
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_MASK 0x000000fe
+
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 8
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0xffffff00
+
+#endif
diff --git a/hw/wcn6450/v1/rx_reo_queue.h b/hw/wcn6450/v1/rx_reo_queue.h
new file mode 100644
index 0000000..1d9d693
--- /dev/null
+++ b/hw/wcn6450/v1/rx_reo_queue.h
@@ -0,0 +1,362 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_REO_QUEUE_H_
+#define _RX_REO_QUEUE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_descriptor_header.h"
+
+#define NUM_OF_DWORDS_RX_REO_QUEUE 32
+
+struct rx_reo_queue {
+ struct uniform_descriptor_header descriptor_header;
+ uint32_t receive_queue_number : 16,
+ reserved_1b : 16;
+ uint32_t vld : 1,
+ associated_link_descriptor_counter: 2,
+ disable_duplicate_detection : 1,
+ soft_reorder_enable : 1,
+ ac : 2,
+ bar : 1,
+ rty : 1,
+ chk_2k_mode : 1,
+ oor_mode : 1,
+ ba_window_size : 8,
+ pn_check_needed : 1,
+ pn_shall_be_even : 1,
+ pn_shall_be_uneven : 1,
+ pn_handling_enable : 1,
+ pn_size : 2,
+ ignore_ampdu_flag : 1,
+ reserved_2b : 6;
+ uint32_t svld : 1,
+ ssn : 12,
+ current_index : 8,
+ seq_2k_error_detected_flag : 1,
+ pn_error_detected_flag : 1,
+ reserved_3a : 8,
+ pn_valid : 1;
+ uint32_t pn_31_0 : 32;
+ uint32_t pn_63_32 : 32;
+ uint32_t pn_95_64 : 32;
+ uint32_t pn_127_96 : 32;
+ uint32_t last_rx_enqueue_timestamp : 32;
+ uint32_t last_rx_dequeue_timestamp : 32;
+ uint32_t ptr_to_next_aging_queue_31_0 : 32;
+ uint32_t ptr_to_next_aging_queue_39_32 : 8,
+ reserved_11a : 24;
+ uint32_t ptr_to_previous_aging_queue_31_0: 32;
+ uint32_t ptr_to_previous_aging_queue_39_32: 8,
+ reserved_13a : 24;
+ uint32_t rx_bitmap_31_0 : 32;
+ uint32_t rx_bitmap_63_32 : 32;
+ uint32_t rx_bitmap_95_64 : 32;
+ uint32_t rx_bitmap_127_96 : 32;
+ uint32_t rx_bitmap_159_128 : 32;
+ uint32_t rx_bitmap_191_160 : 32;
+ uint32_t rx_bitmap_223_192 : 32;
+ uint32_t rx_bitmap_255_224 : 32;
+ uint32_t current_mpdu_count : 7,
+ current_msdu_count : 25;
+ uint32_t reserved_23 : 4,
+ timeout_count : 6,
+ forward_due_to_bar_count : 6,
+ duplicate_count : 16;
+ uint32_t frames_in_order_count : 24,
+ bar_received_count : 8;
+ uint32_t mpdu_frames_processed_count : 32;
+ uint32_t msdu_frames_processed_count : 32;
+ uint32_t total_processed_byte_count : 32;
+ uint32_t late_receive_mpdu_count : 12,
+ window_jump_2k : 4,
+ hole_count : 16;
+ uint32_t reserved_29 : 32;
+ uint32_t reserved_30 : 32;
+ uint32_t reserved_31 : 32;
+};
+
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_LSB 0
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
+
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
+
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00
+
+#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004
+#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_LSB 0
+#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff
+
+#define RX_REO_QUEUE_1_RESERVED_1B_OFFSET 0x00000004
+#define RX_REO_QUEUE_1_RESERVED_1B_LSB 16
+#define RX_REO_QUEUE_1_RESERVED_1B_MASK 0xffff0000
+
+#define RX_REO_QUEUE_2_VLD_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_VLD_LSB 0
+#define RX_REO_QUEUE_2_VLD_MASK 0x00000001
+
+#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1
+#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006
+
+#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_LSB 3
+#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008
+
+#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_LSB 4
+#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_MASK 0x00000010
+
+#define RX_REO_QUEUE_2_AC_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_AC_LSB 5
+#define RX_REO_QUEUE_2_AC_MASK 0x00000060
+
+#define RX_REO_QUEUE_2_BAR_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_BAR_LSB 7
+#define RX_REO_QUEUE_2_BAR_MASK 0x00000080
+
+#define RX_REO_QUEUE_2_RTY_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_RTY_LSB 8
+#define RX_REO_QUEUE_2_RTY_MASK 0x00000100
+
+#define RX_REO_QUEUE_2_CHK_2K_MODE_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_CHK_2K_MODE_LSB 9
+#define RX_REO_QUEUE_2_CHK_2K_MODE_MASK 0x00000200
+
+#define RX_REO_QUEUE_2_OOR_MODE_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_OOR_MODE_LSB 10
+#define RX_REO_QUEUE_2_OOR_MODE_MASK 0x00000400
+
+#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_LSB 11
+#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_MASK 0x0007f800
+
+#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_LSB 19
+#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_MASK 0x00080000
+
+#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_LSB 20
+#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_MASK 0x00100000
+
+#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_LSB 21
+#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_MASK 0x00200000
+
+#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_LSB 22
+#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_MASK 0x00400000
+
+#define RX_REO_QUEUE_2_PN_SIZE_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_PN_SIZE_LSB 23
+#define RX_REO_QUEUE_2_PN_SIZE_MASK 0x01800000
+
+#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_LSB 25
+#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_MASK 0x02000000
+
+#define RX_REO_QUEUE_2_RESERVED_2B_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_RESERVED_2B_LSB 26
+#define RX_REO_QUEUE_2_RESERVED_2B_MASK 0xfc000000
+
+#define RX_REO_QUEUE_3_SVLD_OFFSET 0x0000000c
+#define RX_REO_QUEUE_3_SVLD_LSB 0
+#define RX_REO_QUEUE_3_SVLD_MASK 0x00000001
+
+#define RX_REO_QUEUE_3_SSN_OFFSET 0x0000000c
+#define RX_REO_QUEUE_3_SSN_LSB 1
+#define RX_REO_QUEUE_3_SSN_MASK 0x00001ffe
+
+#define RX_REO_QUEUE_3_CURRENT_INDEX_OFFSET 0x0000000c
+#define RX_REO_QUEUE_3_CURRENT_INDEX_LSB 13
+#define RX_REO_QUEUE_3_CURRENT_INDEX_MASK 0x001fe000
+
+#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c
+#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_LSB 21
+#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00200000
+
+#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c
+#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_LSB 22
+#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_MASK 0x00400000
+
+#define RX_REO_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c
+#define RX_REO_QUEUE_3_RESERVED_3A_LSB 23
+#define RX_REO_QUEUE_3_RESERVED_3A_MASK 0x7f800000
+
+#define RX_REO_QUEUE_3_PN_VALID_OFFSET 0x0000000c
+#define RX_REO_QUEUE_3_PN_VALID_LSB 31
+#define RX_REO_QUEUE_3_PN_VALID_MASK 0x80000000
+
+#define RX_REO_QUEUE_4_PN_31_0_OFFSET 0x00000010
+#define RX_REO_QUEUE_4_PN_31_0_LSB 0
+#define RX_REO_QUEUE_4_PN_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_5_PN_63_32_OFFSET 0x00000014
+#define RX_REO_QUEUE_5_PN_63_32_LSB 0
+#define RX_REO_QUEUE_5_PN_63_32_MASK 0xffffffff
+
+#define RX_REO_QUEUE_6_PN_95_64_OFFSET 0x00000018
+#define RX_REO_QUEUE_6_PN_95_64_LSB 0
+#define RX_REO_QUEUE_6_PN_95_64_MASK 0xffffffff
+
+#define RX_REO_QUEUE_7_PN_127_96_OFFSET 0x0000001c
+#define RX_REO_QUEUE_7_PN_127_96_LSB 0
+#define RX_REO_QUEUE_7_PN_127_96_MASK 0xffffffff
+
+#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020
+#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0
+#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff
+
+#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024
+#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0
+#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff
+
+#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028
+#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0
+#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c
+#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0
+#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_11_RESERVED_11A_OFFSET 0x0000002c
+#define RX_REO_QUEUE_11_RESERVED_11A_LSB 8
+#define RX_REO_QUEUE_11_RESERVED_11A_MASK 0xffffff00
+
+#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030
+#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0
+#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034
+#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0
+#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_13_RESERVED_13A_OFFSET 0x00000034
+#define RX_REO_QUEUE_13_RESERVED_13A_LSB 8
+#define RX_REO_QUEUE_13_RESERVED_13A_MASK 0xffffff00
+
+#define RX_REO_QUEUE_14_RX_BITMAP_31_0_OFFSET 0x00000038
+#define RX_REO_QUEUE_14_RX_BITMAP_31_0_LSB 0
+#define RX_REO_QUEUE_14_RX_BITMAP_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_15_RX_BITMAP_63_32_OFFSET 0x0000003c
+#define RX_REO_QUEUE_15_RX_BITMAP_63_32_LSB 0
+#define RX_REO_QUEUE_15_RX_BITMAP_63_32_MASK 0xffffffff
+
+#define RX_REO_QUEUE_16_RX_BITMAP_95_64_OFFSET 0x00000040
+#define RX_REO_QUEUE_16_RX_BITMAP_95_64_LSB 0
+#define RX_REO_QUEUE_16_RX_BITMAP_95_64_MASK 0xffffffff
+
+#define RX_REO_QUEUE_17_RX_BITMAP_127_96_OFFSET 0x00000044
+#define RX_REO_QUEUE_17_RX_BITMAP_127_96_LSB 0
+#define RX_REO_QUEUE_17_RX_BITMAP_127_96_MASK 0xffffffff
+
+#define RX_REO_QUEUE_18_RX_BITMAP_159_128_OFFSET 0x00000048
+#define RX_REO_QUEUE_18_RX_BITMAP_159_128_LSB 0
+#define RX_REO_QUEUE_18_RX_BITMAP_159_128_MASK 0xffffffff
+
+#define RX_REO_QUEUE_19_RX_BITMAP_191_160_OFFSET 0x0000004c
+#define RX_REO_QUEUE_19_RX_BITMAP_191_160_LSB 0
+#define RX_REO_QUEUE_19_RX_BITMAP_191_160_MASK 0xffffffff
+
+#define RX_REO_QUEUE_20_RX_BITMAP_223_192_OFFSET 0x00000050
+#define RX_REO_QUEUE_20_RX_BITMAP_223_192_LSB 0
+#define RX_REO_QUEUE_20_RX_BITMAP_223_192_MASK 0xffffffff
+
+#define RX_REO_QUEUE_21_RX_BITMAP_255_224_OFFSET 0x00000054
+#define RX_REO_QUEUE_21_RX_BITMAP_255_224_LSB 0
+#define RX_REO_QUEUE_21_RX_BITMAP_255_224_MASK 0xffffffff
+
+#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_OFFSET 0x00000058
+#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_LSB 0
+#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_MASK 0x0000007f
+
+#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_OFFSET 0x00000058
+#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_LSB 7
+#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_MASK 0xffffff80
+
+#define RX_REO_QUEUE_23_RESERVED_23_OFFSET 0x0000005c
+#define RX_REO_QUEUE_23_RESERVED_23_LSB 0
+#define RX_REO_QUEUE_23_RESERVED_23_MASK 0x0000000f
+
+#define RX_REO_QUEUE_23_TIMEOUT_COUNT_OFFSET 0x0000005c
+#define RX_REO_QUEUE_23_TIMEOUT_COUNT_LSB 4
+#define RX_REO_QUEUE_23_TIMEOUT_COUNT_MASK 0x000003f0
+
+#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000005c
+#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_LSB 10
+#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00
+
+#define RX_REO_QUEUE_23_DUPLICATE_COUNT_OFFSET 0x0000005c
+#define RX_REO_QUEUE_23_DUPLICATE_COUNT_LSB 16
+#define RX_REO_QUEUE_23_DUPLICATE_COUNT_MASK 0xffff0000
+
+#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000060
+#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_LSB 0
+#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff
+
+#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_OFFSET 0x00000060
+#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_LSB 24
+#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_MASK 0xff000000
+
+#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000064
+#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_LSB 0
+#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
+
+#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068
+#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_LSB 0
+#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
+
+#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000006c
+#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_LSB 0
+#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff
+
+#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000070
+#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_LSB 0
+#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff
+
+#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_OFFSET 0x00000070
+#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_LSB 12
+#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_MASK 0x0000f000
+
+#define RX_REO_QUEUE_28_HOLE_COUNT_OFFSET 0x00000070
+#define RX_REO_QUEUE_28_HOLE_COUNT_LSB 16
+#define RX_REO_QUEUE_28_HOLE_COUNT_MASK 0xffff0000
+
+#define RX_REO_QUEUE_29_RESERVED_29_OFFSET 0x00000074
+#define RX_REO_QUEUE_29_RESERVED_29_LSB 0
+#define RX_REO_QUEUE_29_RESERVED_29_MASK 0xffffffff
+
+#define RX_REO_QUEUE_30_RESERVED_30_OFFSET 0x00000078
+#define RX_REO_QUEUE_30_RESERVED_30_LSB 0
+#define RX_REO_QUEUE_30_RESERVED_30_MASK 0xffffffff
+
+#define RX_REO_QUEUE_31_RESERVED_31_OFFSET 0x0000007c
+#define RX_REO_QUEUE_31_RESERVED_31_LSB 0
+#define RX_REO_QUEUE_31_RESERVED_31_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/rx_reo_queue_ext.h b/hw/wcn6450/v1/rx_reo_queue_ext.h
new file mode 100644
index 0000000..fe0a9b7
--- /dev/null
+++ b/hw/wcn6450/v1/rx_reo_queue_ext.h
@@ -0,0 +1,308 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_REO_QUEUE_EXT_H_
+#define _RX_REO_QUEUE_EXT_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_descriptor_header.h"
+#include "rx_mpdu_link_ptr.h"
+
+#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32
+
+struct rx_reo_queue_ext {
+ struct uniform_descriptor_header descriptor_header;
+ uint32_t reserved_1a : 32;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_0;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_1;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_2;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_3;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_4;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_5;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_6;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_7;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_8;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_9;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_10;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_11;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_12;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_13;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_14;
+};
+
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_LSB 0
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
+
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
+
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00
+
+#define RX_REO_QUEUE_EXT_1_RESERVED_1A_OFFSET 0x00000004
+#define RX_REO_QUEUE_EXT_1_RESERVED_1A_LSB 0
+#define RX_REO_QUEUE_EXT_1_RESERVED_1A_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008
+#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010
+#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018
+#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020
+#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028
+#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030
+#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038
+#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040
+#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048
+#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050
+#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058
+#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060
+#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068
+#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070
+#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078
+#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#endif
diff --git a/hw/wcn6450/v1/rx_rxpcu_classification_overview.h b/hw/wcn6450/v1/rx_rxpcu_classification_overview.h
new file mode 100644
index 0000000..8e8ffad
--- /dev/null
+++ b/hw/wcn6450/v1/rx_rxpcu_classification_overview.h
@@ -0,0 +1,77 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
+#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1
+
+struct rx_rxpcu_classification_overview {
+ uint32_t filter_pass_mpdus : 1,
+ filter_pass_mpdus_fcs_ok : 1,
+ monitor_direct_mpdus : 1,
+ monitor_direct_mpdus_fcs_ok : 1,
+ monitor_other_mpdus : 1,
+ monitor_other_mpdus_fcs_ok : 1,
+ phyrx_abort_received : 1,
+ reserved_0 : 9,
+ phy_ppdu_id : 16;
+};
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_LSB 0
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_MASK 0x00000001
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_MASK 0x00000004
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_MASK 0x00000010
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_MASK 0x00000040
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_LSB 7
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_MASK 0x0000ff80
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_LSB 16
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_MASK 0xffff0000
+
+#endif
diff --git a/hw/wcn6450/v1/rx_timing_offset_info.h b/hw/wcn6450/v1/rx_timing_offset_info.h
new file mode 100644
index 0000000..14e630e
--- /dev/null
+++ b/hw/wcn6450/v1/rx_timing_offset_info.h
@@ -0,0 +1,42 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_TIMING_OFFSET_INFO_H_
+#define _RX_TIMING_OFFSET_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_TIMING_OFFSET_INFO 1
+
+struct rx_timing_offset_info {
+ uint32_t residual_phase_offset : 12,
+ reserved : 20;
+};
+
+#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000000
+#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_LSB 0
+#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
+
+#define RX_TIMING_OFFSET_INFO_0_RESERVED_OFFSET 0x00000000
+#define RX_TIMING_OFFSET_INFO_0_RESERVED_LSB 12
+#define RX_TIMING_OFFSET_INFO_0_RESERVED_MASK 0xfffff000
+
+#endif
diff --git a/hw/wcn6450/v1/rxpcu_ppdu_end_info.h b/hw/wcn6450/v1/rxpcu_ppdu_end_info.h
new file mode 100644
index 0000000..2db6848
--- /dev/null
+++ b/hw/wcn6450/v1/rxpcu_ppdu_end_info.h
@@ -0,0 +1,278 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RXPCU_PPDU_END_INFO_H_
+#define _RXPCU_PPDU_END_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "phyrx_abort_request_info.h"
+#include "macrx_abort_request_info.h"
+
+#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 14
+
+struct rxpcu_ppdu_end_info {
+ uint32_t wb_timestamp_lower_32 : 32;
+ uint32_t wb_timestamp_upper_32 : 32;
+ uint32_t rx_antenna : 24,
+ tx_ht_vht_ack : 1,
+ unsupported_mu_nc : 1,
+ otp_txbf_disable : 1,
+ previous_tlv_corrupted : 1,
+ phyrx_abort_request_info_valid : 1,
+ macrx_abort_request_info_valid : 1,
+ reserved : 2;
+ uint32_t coex_bt_tx_from_start_of_rx : 1,
+ coex_bt_tx_after_start_of_rx : 1,
+ coex_wan_tx_from_start_of_rx : 1,
+ coex_wan_tx_after_start_of_rx : 1,
+ coex_wlan_tx_from_start_of_rx : 1,
+ coex_wlan_tx_after_start_of_rx : 1,
+ mpdu_delimiter_errors_seen : 1,
+ __reserved_g_0012 : 2,
+ dialog_token : 8,
+ follow_up_dialog_token : 8,
+ bb_captured_channel : 1,
+ bb_captured_reason : 3,
+ bb_captured_timeout : 1,
+ reserved_3 : 2;
+ uint32_t before_mpdu_count_passing_fcs : 10,
+ before_mpdu_count_failing_fcs : 10,
+ after_mpdu_count_passing_fcs : 10,
+ reserved_4 : 2;
+ uint32_t after_mpdu_count_failing_fcs : 10,
+ reserved_5 : 22;
+ uint32_t phy_timestamp_tx_lower_32 : 32;
+ uint32_t phy_timestamp_tx_upper_32 : 32;
+ uint32_t bb_length : 16,
+ bb_data : 1,
+ reserved_8 : 3,
+ first_bt_broadcast_status_details: 12;
+ uint32_t rx_ppdu_duration : 24,
+ reserved_9 : 8;
+ uint32_t ast_index : 16,
+ ast_index_valid : 1,
+ reserved_10 : 3,
+ second_bt_broadcast_status_details: 12;
+ struct phyrx_abort_request_info phyrx_abort_request_info_details;
+ struct macrx_abort_request_info macrx_abort_request_info_details;
+ uint16_t pre_bt_broadcast_status_details : 12,
+ reserved_12a : 4;
+ uint32_t rx_ppdu_end_marker : 32;
+};
+
+#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_OFFSET 0x00000000
+#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_LSB 0
+#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_MASK 0xffffffff
+
+#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_OFFSET 0x00000004
+#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_LSB 0
+#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff
+
+#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_LSB 0
+#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_MASK 0x00ffffff
+
+#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_LSB 24
+#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_MASK 0x01000000
+
+#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_LSB 25
+#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_MASK 0x02000000
+
+#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_LSB 26
+#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_MASK 0x04000000
+
+#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_LSB 27
+#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_MASK 0x08000000
+
+#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28
+#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000
+
+#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29
+#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x20000000
+
+#define RXPCU_PPDU_END_INFO_2_RESERVED_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_2_RESERVED_LSB 30
+#define RXPCU_PPDU_END_INFO_2_RESERVED_MASK 0xc0000000
+
+#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_LSB 0
+#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_MASK 0x00000001
+
+#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_LSB 1
+#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x00000002
+
+#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_LSB 2
+#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x00000004
+
+#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_LSB 3
+#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x00000008
+
+#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_LSB 4
+#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x00000010
+
+#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 5
+#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x00000020
+
+#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_LSB 6
+#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x00000040
+
+#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_LSB 9
+#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_MASK 0x0001fe00
+
+#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_LSB 17
+#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe0000
+
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_LSB 25
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_MASK 0x02000000
+
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_LSB 26
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_MASK 0x1c000000
+
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_LSB 29
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_MASK 0x20000000
+
+#define RXPCU_PPDU_END_INFO_3_RESERVED_3_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_RESERVED_3_LSB 30
+#define RXPCU_PPDU_END_INFO_3_RESERVED_3_MASK 0xc0000000
+
+#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010
+#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0
+#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x000003ff
+
+#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000010
+#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10
+#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x000ffc00
+
+#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010
+#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20
+#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x3ff00000
+
+#define RXPCU_PPDU_END_INFO_4_RESERVED_4_OFFSET 0x00000010
+#define RXPCU_PPDU_END_INFO_4_RESERVED_4_LSB 30
+#define RXPCU_PPDU_END_INFO_4_RESERVED_4_MASK 0xc0000000
+
+#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000014
+#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_LSB 0
+#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff
+
+#define RXPCU_PPDU_END_INFO_5_RESERVED_5_OFFSET 0x00000014
+#define RXPCU_PPDU_END_INFO_5_RESERVED_5_LSB 10
+#define RXPCU_PPDU_END_INFO_5_RESERVED_5_MASK 0xfffffc00
+
+#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x00000018
+#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_LSB 0
+#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_MASK 0xffffffff
+
+#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000001c
+#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_LSB 0
+#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff
+
+#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_OFFSET 0x00000020
+#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_LSB 0
+#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_MASK 0x0000ffff
+
+#define RXPCU_PPDU_END_INFO_8_BB_DATA_OFFSET 0x00000020
+#define RXPCU_PPDU_END_INFO_8_BB_DATA_LSB 16
+#define RXPCU_PPDU_END_INFO_8_BB_DATA_MASK 0x00010000
+
+#define RXPCU_PPDU_END_INFO_8_RESERVED_8_OFFSET 0x00000020
+#define RXPCU_PPDU_END_INFO_8_RESERVED_8_LSB 17
+#define RXPCU_PPDU_END_INFO_8_RESERVED_8_MASK 0x000e0000
+
+#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000020
+#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20
+#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000
+
+#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 0x00000024
+#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 0
+#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 0x00ffffff
+
+#define RXPCU_PPDU_END_INFO_9_RESERVED_9_OFFSET 0x00000024
+#define RXPCU_PPDU_END_INFO_9_RESERVED_9_LSB 24
+#define RXPCU_PPDU_END_INFO_9_RESERVED_9_MASK 0xff000000
+
+#define RXPCU_PPDU_END_INFO_10_AST_INDEX_OFFSET 0x00000028
+#define RXPCU_PPDU_END_INFO_10_AST_INDEX_LSB 0
+#define RXPCU_PPDU_END_INFO_10_AST_INDEX_MASK 0x0000ffff
+
+#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_OFFSET 0x00000028
+#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_LSB 16
+#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_MASK 0x00010000
+
+#define RXPCU_PPDU_END_INFO_10_RESERVED_10_OFFSET 0x00000028
+#define RXPCU_PPDU_END_INFO_10_RESERVED_10_LSB 17
+#define RXPCU_PPDU_END_INFO_10_RESERVED_10_MASK 0x000e0000
+
+#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000028
+#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20
+#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000
+
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 0
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff
+
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 8
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x00000100
+
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 9
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x00000200
+
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 10
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc00
+
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 16
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff0000
+
+#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000030
+#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0
+#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x000000ff
+
+#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x00000030
+#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8
+#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000ff00
+
+#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_OFFSET 0x00000034
+#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_LSB 0
+#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/rxpt_classify_info.h b/hw/wcn6450/v1/rxpt_classify_info.h
new file mode 100644
index 0000000..8f2d34d
--- /dev/null
+++ b/hw/wcn6450/v1/rxpt_classify_info.h
@@ -0,0 +1,77 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RXPT_CLASSIFY_INFO_H_
+#define _RXPT_CLASSIFY_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1
+
+struct rxpt_classify_info {
+ uint32_t reo_destination_indication : 5,
+ lmac_peer_id_msb : 2,
+ use_flow_id_toeplitz_clfy : 1,
+ pkt_selection_fp_ucast_data : 1,
+ pkt_selection_fp_mcast_data : 1,
+ pkt_selection_fp_1000 : 1,
+ rxdma0_source_ring_selection : 2,
+ rxdma0_destination_ring_selection: 2,
+ reserved_0b : 17;
+};
+
+#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_LSB 0
+#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_LSB 5
+#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_MASK 0x00000060
+
+#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
+#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080
+
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_LSB 8
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100
+
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_LSB 9
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200
+
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_LSB 10
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_MASK 0x00000400
+
+#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_LSB 11
+#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800
+
+#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_LSB 13
+#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000
+
+#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_LSB 15
+#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_MASK 0xffff8000
+
+#endif
diff --git a/hw/wcn6450/v1/seq_hwio.h b/hw/wcn6450/v1/seq_hwio.h
new file mode 100644
index 0000000..6da3193
--- /dev/null
+++ b/hw/wcn6450/v1/seq_hwio.h
@@ -0,0 +1,57 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef __SEQ_H__
+#define __SEQ_H__
+
+#include "HALhwio.h"
+
+#define SEQ_INH(base, regtype, reg) \
+ SEQ_##regtype##_INH(base, reg)
+
+#define SEQ_INMH(base, regtype, reg, mask) \
+ SEQ_##regtype##_INMH(base, reg, mask)
+
+#define SEQ_INFH(base, regtype, reg, fld) \
+ (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld))
+
+#define SEQ_OUTH(base, regtype, reg, val) \
+ SEQ_##regtype##_OUTH(base, reg, val)
+
+#define SEQ_OUTMH(base, regtype, reg, mask, val) \
+ SEQ_##regtype##_OUTMH(base, reg, mask, val)
+
+#define SEQ_OUTFH(base, regtype, reg, fld, val) \
+ SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld))
+
+typedef enum {
+ SEC,
+ MS,
+ US,
+ NS
+} SEQ_TimeUnit;
+
+extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit);
+
+extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt);
+
+#endif
+
diff --git a/hw/wcn6450/v1/tcl_data_cmd.h b/hw/wcn6450/v1/tcl_data_cmd.h
new file mode 100644
index 0000000..bc7a04c
--- /dev/null
+++ b/hw/wcn6450/v1/tcl_data_cmd.h
@@ -0,0 +1,231 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _TCL_DATA_CMD_H_
+#define _TCL_DATA_CMD_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+
+#define NUM_OF_DWORDS_TCL_DATA_CMD 7
+
+struct tcl_data_cmd {
+ struct buffer_addr_info buf_addr_info;
+ uint32_t buf_or_ext_desc_type : 1,
+ epd : 1,
+ encap_type : 2,
+ encrypt_type : 4,
+ src_buffer_swap : 1,
+ link_meta_swap : 1,
+ tqm_no_drop : 1,
+ reserved_2a : 1,
+ search_type : 2,
+ addrx_en : 1,
+ addry_en : 1,
+ tcl_cmd_number : 16;
+ uint32_t data_length : 16,
+ ipv4_checksum_en : 1,
+ udp_over_ipv4_checksum_en : 1,
+ udp_over_ipv6_checksum_en : 1,
+ tcp_over_ipv4_checksum_en : 1,
+ tcp_over_ipv6_checksum_en : 1,
+ to_fw : 1,
+ reserved_3a : 1,
+ packet_offset : 9;
+ uint32_t buffer_timestamp : 19,
+ buffer_timestamp_valid : 1,
+ reserved_4a : 1,
+ hlos_tid_overwrite : 1,
+ hlos_tid : 4,
+ lmac_id : 2,
+ udp_flow_override : 2,
+ reserved_4b : 2;
+ uint32_t dscp_tid_table_num : 6,
+ search_index : 20,
+ cache_set_num : 4,
+ mesh_enable : 2;
+ uint32_t reserved_6a : 20,
+ ring_id : 8,
+ looping_count : 4;
+};
+
+#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 0
+#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 0x00000001
+
+#define TCL_DATA_CMD_2_EPD_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_EPD_LSB 1
+#define TCL_DATA_CMD_2_EPD_MASK 0x00000002
+
+#define TCL_DATA_CMD_2_ENCAP_TYPE_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_ENCAP_TYPE_LSB 2
+#define TCL_DATA_CMD_2_ENCAP_TYPE_MASK 0x0000000c
+
+#define TCL_DATA_CMD_2_ENCRYPT_TYPE_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_ENCRYPT_TYPE_LSB 4
+#define TCL_DATA_CMD_2_ENCRYPT_TYPE_MASK 0x000000f0
+
+#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_LSB 8
+#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_MASK 0x00000100
+
+#define TCL_DATA_CMD_2_LINK_META_SWAP_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_LINK_META_SWAP_LSB 9
+#define TCL_DATA_CMD_2_LINK_META_SWAP_MASK 0x00000200
+
+#define TCL_DATA_CMD_2_TQM_NO_DROP_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_TQM_NO_DROP_LSB 10
+#define TCL_DATA_CMD_2_TQM_NO_DROP_MASK 0x00000400
+
+#define TCL_DATA_CMD_2_RESERVED_2A_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_RESERVED_2A_LSB 11
+#define TCL_DATA_CMD_2_RESERVED_2A_MASK 0x00000800
+
+#define TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_SEARCH_TYPE_LSB 12
+#define TCL_DATA_CMD_2_SEARCH_TYPE_MASK 0x00003000
+
+#define TCL_DATA_CMD_2_ADDRX_EN_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_ADDRX_EN_LSB 14
+#define TCL_DATA_CMD_2_ADDRX_EN_MASK 0x00004000
+
+#define TCL_DATA_CMD_2_ADDRY_EN_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_ADDRY_EN_LSB 15
+#define TCL_DATA_CMD_2_ADDRY_EN_MASK 0x00008000
+
+#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_LSB 16
+#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_MASK 0xffff0000
+
+#define TCL_DATA_CMD_3_DATA_LENGTH_OFFSET 0x0000000c
+#define TCL_DATA_CMD_3_DATA_LENGTH_LSB 0
+#define TCL_DATA_CMD_3_DATA_LENGTH_MASK 0x0000ffff
+
+#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_OFFSET 0x0000000c
+#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_LSB 16
+#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_MASK 0x00010000
+
+#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c
+#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17
+#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000
+
+#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c
+#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18
+#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000
+
+#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c
+#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19
+#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000
+
+#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c
+#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20
+#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000
+
+#define TCL_DATA_CMD_3_TO_FW_OFFSET 0x0000000c
+#define TCL_DATA_CMD_3_TO_FW_LSB 21
+#define TCL_DATA_CMD_3_TO_FW_MASK 0x00200000
+
+#define TCL_DATA_CMD_3_RESERVED_3A_OFFSET 0x0000000c
+#define TCL_DATA_CMD_3_RESERVED_3A_LSB 22
+#define TCL_DATA_CMD_3_RESERVED_3A_MASK 0x00400000
+
+#define TCL_DATA_CMD_3_PACKET_OFFSET_OFFSET 0x0000000c
+#define TCL_DATA_CMD_3_PACKET_OFFSET_LSB 23
+#define TCL_DATA_CMD_3_PACKET_OFFSET_MASK 0xff800000
+
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_OFFSET 0x00000010
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_LSB 0
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_MASK 0x0007ffff
+
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000010
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_LSB 19
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_MASK 0x00080000
+
+#define TCL_DATA_CMD_4_RESERVED_4A_OFFSET 0x00000010
+#define TCL_DATA_CMD_4_RESERVED_4A_LSB 20
+#define TCL_DATA_CMD_4_RESERVED_4A_MASK 0x00100000
+
+#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_OFFSET 0x00000010
+#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_LSB 21
+#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_MASK 0x00200000
+
+#define TCL_DATA_CMD_4_HLOS_TID_OFFSET 0x00000010
+#define TCL_DATA_CMD_4_HLOS_TID_LSB 22
+#define TCL_DATA_CMD_4_HLOS_TID_MASK 0x03c00000
+
+#define TCL_DATA_CMD_4_LMAC_ID_OFFSET 0x00000010
+#define TCL_DATA_CMD_4_LMAC_ID_LSB 26
+#define TCL_DATA_CMD_4_LMAC_ID_MASK 0x0c000000
+
+#define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_OFFSET 0x00000010
+#define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_LSB 28
+#define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_MASK 0x30000000
+
+#define TCL_DATA_CMD_4_RESERVED_4B_OFFSET 0x00000010
+#define TCL_DATA_CMD_4_RESERVED_4B_LSB 30
+#define TCL_DATA_CMD_4_RESERVED_4B_MASK 0xc0000000
+
+#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_OFFSET 0x00000014
+#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_LSB 0
+#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_MASK 0x0000003f
+
+#define TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 0x00000014
+#define TCL_DATA_CMD_5_SEARCH_INDEX_LSB 6
+#define TCL_DATA_CMD_5_SEARCH_INDEX_MASK 0x03ffffc0
+
+#define TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET 0x00000014
+#define TCL_DATA_CMD_5_CACHE_SET_NUM_LSB 26
+#define TCL_DATA_CMD_5_CACHE_SET_NUM_MASK 0x3c000000
+
+#define TCL_DATA_CMD_5_MESH_ENABLE_OFFSET 0x00000014
+#define TCL_DATA_CMD_5_MESH_ENABLE_LSB 30
+#define TCL_DATA_CMD_5_MESH_ENABLE_MASK 0xc0000000
+
+#define TCL_DATA_CMD_6_RESERVED_6A_OFFSET 0x00000018
+#define TCL_DATA_CMD_6_RESERVED_6A_LSB 0
+#define TCL_DATA_CMD_6_RESERVED_6A_MASK 0x000fffff
+
+#define TCL_DATA_CMD_6_RING_ID_OFFSET 0x00000018
+#define TCL_DATA_CMD_6_RING_ID_LSB 20
+#define TCL_DATA_CMD_6_RING_ID_MASK 0x0ff00000
+
+#define TCL_DATA_CMD_6_LOOPING_COUNT_OFFSET 0x00000018
+#define TCL_DATA_CMD_6_LOOPING_COUNT_LSB 28
+#define TCL_DATA_CMD_6_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/hw/wcn6450/v1/tcl_gse_cmd.h b/hw/wcn6450/v1/tcl_gse_cmd.h
new file mode 100644
index 0000000..21edac8
--- /dev/null
+++ b/hw/wcn6450/v1/tcl_gse_cmd.h
@@ -0,0 +1,112 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _TCL_GSE_CMD_H_
+#define _TCL_GSE_CMD_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_TCL_GSE_CMD 7
+
+struct tcl_gse_cmd {
+ uint32_t control_buffer_addr_31_0 : 32;
+ uint32_t control_buffer_addr_39_32 : 8,
+ gse_ctrl : 4,
+ gse_sel : 1,
+ status_destination_ring_id : 1,
+ swap : 1,
+ index_search_en : 1,
+ cache_set_num : 4,
+ reserved_1a : 12;
+ uint32_t cmd_meta_data_31_0 : 32;
+ uint32_t cmd_meta_data_63_32 : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 20,
+ ring_id : 8,
+ looping_count : 4;
+};
+
+#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB 0
+#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB 0
+#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define TCL_GSE_CMD_1_GSE_CTRL_OFFSET 0x00000004
+#define TCL_GSE_CMD_1_GSE_CTRL_LSB 8
+#define TCL_GSE_CMD_1_GSE_CTRL_MASK 0x00000f00
+
+#define TCL_GSE_CMD_1_GSE_SEL_OFFSET 0x00000004
+#define TCL_GSE_CMD_1_GSE_SEL_LSB 12
+#define TCL_GSE_CMD_1_GSE_SEL_MASK 0x00001000
+
+#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004
+#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB 13
+#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK 0x00002000
+
+#define TCL_GSE_CMD_1_SWAP_OFFSET 0x00000004
+#define TCL_GSE_CMD_1_SWAP_LSB 14
+#define TCL_GSE_CMD_1_SWAP_MASK 0x00004000
+
+#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_OFFSET 0x00000004
+#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_LSB 15
+#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_MASK 0x00008000
+
+#define TCL_GSE_CMD_1_CACHE_SET_NUM_OFFSET 0x00000004
+#define TCL_GSE_CMD_1_CACHE_SET_NUM_LSB 16
+#define TCL_GSE_CMD_1_CACHE_SET_NUM_MASK 0x000f0000
+
+#define TCL_GSE_CMD_1_RESERVED_1A_OFFSET 0x00000004
+#define TCL_GSE_CMD_1_RESERVED_1A_LSB 20
+#define TCL_GSE_CMD_1_RESERVED_1A_MASK 0xfff00000
+
+#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET 0x00000008
+#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB 0
+#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK 0xffffffff
+
+#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET 0x0000000c
+#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB 0
+#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK 0xffffffff
+
+#define TCL_GSE_CMD_4_RESERVED_4A_OFFSET 0x00000010
+#define TCL_GSE_CMD_4_RESERVED_4A_LSB 0
+#define TCL_GSE_CMD_4_RESERVED_4A_MASK 0xffffffff
+
+#define TCL_GSE_CMD_5_RESERVED_5A_OFFSET 0x00000014
+#define TCL_GSE_CMD_5_RESERVED_5A_LSB 0
+#define TCL_GSE_CMD_5_RESERVED_5A_MASK 0xffffffff
+
+#define TCL_GSE_CMD_6_RESERVED_6A_OFFSET 0x00000018
+#define TCL_GSE_CMD_6_RESERVED_6A_LSB 0
+#define TCL_GSE_CMD_6_RESERVED_6A_MASK 0x000fffff
+
+#define TCL_GSE_CMD_6_RING_ID_OFFSET 0x00000018
+#define TCL_GSE_CMD_6_RING_ID_LSB 20
+#define TCL_GSE_CMD_6_RING_ID_MASK 0x0ff00000
+
+#define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET 0x00000018
+#define TCL_GSE_CMD_6_LOOPING_COUNT_LSB 28
+#define TCL_GSE_CMD_6_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/hw/wcn6450/v1/tcl_status_ring.h b/hw/wcn6450/v1/tcl_status_ring.h
new file mode 100644
index 0000000..29a3520
--- /dev/null
+++ b/hw/wcn6450/v1/tcl_status_ring.h
@@ -0,0 +1,112 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _TCL_STATUS_RING_H_
+#define _TCL_STATUS_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_TCL_STATUS_RING 8
+
+struct tcl_status_ring {
+ uint32_t gse_ctrl : 4,
+ ase_fse_sel : 1,
+ cache_op_res : 2,
+ index_search_en : 1,
+ msdu_cnt_n : 24;
+ uint32_t msdu_byte_cnt_n : 32;
+ uint32_t msdu_timestmp_n : 32;
+ uint32_t cmd_meta_data_31_0 : 32;
+ uint32_t cmd_meta_data_63_32 : 32;
+ uint32_t hash_indx_val : 20,
+ cache_set_num : 4,
+ reserved_5a : 8;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 20,
+ ring_id : 8,
+ looping_count : 4;
+};
+
+#define TCL_STATUS_RING_0_GSE_CTRL_OFFSET 0x00000000
+#define TCL_STATUS_RING_0_GSE_CTRL_LSB 0
+#define TCL_STATUS_RING_0_GSE_CTRL_MASK 0x0000000f
+
+#define TCL_STATUS_RING_0_ASE_FSE_SEL_OFFSET 0x00000000
+#define TCL_STATUS_RING_0_ASE_FSE_SEL_LSB 4
+#define TCL_STATUS_RING_0_ASE_FSE_SEL_MASK 0x00000010
+
+#define TCL_STATUS_RING_0_CACHE_OP_RES_OFFSET 0x00000000
+#define TCL_STATUS_RING_0_CACHE_OP_RES_LSB 5
+#define TCL_STATUS_RING_0_CACHE_OP_RES_MASK 0x00000060
+
+#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_OFFSET 0x00000000
+#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_LSB 7
+#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_MASK 0x00000080
+
+#define TCL_STATUS_RING_0_MSDU_CNT_N_OFFSET 0x00000000
+#define TCL_STATUS_RING_0_MSDU_CNT_N_LSB 8
+#define TCL_STATUS_RING_0_MSDU_CNT_N_MASK 0xffffff00
+
+#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_OFFSET 0x00000004
+#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_LSB 0
+#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_MASK 0xffffffff
+
+#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_OFFSET 0x00000008
+#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_LSB 0
+#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_MASK 0xffffffff
+
+#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_OFFSET 0x0000000c
+#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_LSB 0
+#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_MASK 0xffffffff
+
+#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_OFFSET 0x00000010
+#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_LSB 0
+#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_MASK 0xffffffff
+
+#define TCL_STATUS_RING_5_HASH_INDX_VAL_OFFSET 0x00000014
+#define TCL_STATUS_RING_5_HASH_INDX_VAL_LSB 0
+#define TCL_STATUS_RING_5_HASH_INDX_VAL_MASK 0x000fffff
+
+#define TCL_STATUS_RING_5_CACHE_SET_NUM_OFFSET 0x00000014
+#define TCL_STATUS_RING_5_CACHE_SET_NUM_LSB 20
+#define TCL_STATUS_RING_5_CACHE_SET_NUM_MASK 0x00f00000
+
+#define TCL_STATUS_RING_5_RESERVED_5A_OFFSET 0x00000014
+#define TCL_STATUS_RING_5_RESERVED_5A_LSB 24
+#define TCL_STATUS_RING_5_RESERVED_5A_MASK 0xff000000
+
+#define TCL_STATUS_RING_6_RESERVED_6A_OFFSET 0x00000018
+#define TCL_STATUS_RING_6_RESERVED_6A_LSB 0
+#define TCL_STATUS_RING_6_RESERVED_6A_MASK 0xffffffff
+
+#define TCL_STATUS_RING_7_RESERVED_7A_OFFSET 0x0000001c
+#define TCL_STATUS_RING_7_RESERVED_7A_LSB 0
+#define TCL_STATUS_RING_7_RESERVED_7A_MASK 0x000fffff
+
+#define TCL_STATUS_RING_7_RING_ID_OFFSET 0x0000001c
+#define TCL_STATUS_RING_7_RING_ID_LSB 20
+#define TCL_STATUS_RING_7_RING_ID_MASK 0x0ff00000
+
+#define TCL_STATUS_RING_7_LOOPING_COUNT_OFFSET 0x0000001c
+#define TCL_STATUS_RING_7_LOOPING_COUNT_LSB 28
+#define TCL_STATUS_RING_7_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/hw/wcn6450/v1/tlv_hdr.h b/hw/wcn6450/v1/tlv_hdr.h
new file mode 100644
index 0000000..2129cb6
--- /dev/null
+++ b/hw/wcn6450/v1/tlv_hdr.h
@@ -0,0 +1,123 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _TLV_HDR_H_
+
+#define _TLV_HDR_H_
+
+#if !defined(__ASSEMBLER__)
+
+#endif
+
+struct tlv_usr_16_hdr {
+
+ volatile uint16_t tlv_cflg_reserved : 1,
+
+ tlv_tag : 5,
+
+ tlv_len : 4,
+
+ tlv_usrid : 6;
+
+};
+
+struct tlv_16_hdr {
+
+ volatile uint16_t tlv_cflg_reserved : 1,
+
+ tlv_tag : 5,
+
+ tlv_len : 4,
+
+ tlv_reserved : 6;
+
+};
+
+struct tlv_usr_32_hdr {
+
+ volatile uint32_t tlv_cflg_reserved : 1,
+
+ tlv_tag : 9,
+
+ tlv_len : 16,
+
+ tlv_usrid : 6;
+
+};
+
+struct tlv_32_hdr {
+
+ volatile uint32_t tlv_cflg_reserved : 1,
+
+ tlv_tag : 9,
+
+ tlv_len : 16,
+
+ tlv_reserved : 6;
+
+};
+
+struct tlv_usr_42_hdr {
+
+ volatile uint64_t tlv_compression : 1,
+
+ tlv_tag : 9,
+
+ tlv_len : 16,
+
+ tlv_usrid : 6,
+
+ tlv_reserved : 10,
+
+ pad_42to64_bit : 22;
+
+};
+
+struct tlv_42_hdr {
+
+ volatile uint64_t tlv_compression : 1,
+
+ tlv_tag : 9,
+
+ tlv_len : 16,
+
+ tlv_reserved : 16,
+
+ pad_42to64_bit : 22;
+
+};
+
+struct tlv_usr_c_42_hdr {
+
+ volatile uint64_t tlv_compression : 1,
+
+ tlv_ctag : 3,
+
+ tlv_usrid : 6,
+
+ tlv_cdata : 32,
+
+ pad_42to64_bit : 22;
+
+};
+
+#endif
+
diff --git a/hw/wcn6450/v1/tlv_tag_def.h b/hw/wcn6450/v1/tlv_tag_def.h
new file mode 100644
index 0000000..817873f
--- /dev/null
+++ b/hw/wcn6450/v1/tlv_tag_def.h
@@ -0,0 +1,528 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _TLV_TAG_DEF_
+#define _TLV_TAG_DEF_
+
+typedef enum {
+
+ WIFIMACTX_CBF_START_E = 0 ,
+ WIFIPHYRX_DATA_E = 1 ,
+ WIFIPHYRX_CBF_DATA_RESP_E = 2 ,
+ WIFIPHYRX_ABORT_REQUEST_E = 3 ,
+ WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 ,
+ WIFIMACTX_DATA_RESP_E = 5 ,
+ WIFIMACTX_CBF_DATA_E = 6 ,
+ WIFIMACTX_CBF_DONE_E = 7 ,
+ WIFIMACRX_CBF_READ_REQUEST_E = 8 ,
+ WIFIMACRX_CBF_DATA_REQUEST_E = 9 ,
+ WIFIMACRX_EXPECT_NDP_RECEPTION_E = 10 ,
+ WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 11 ,
+ WIFIMACRX_NDP_TIMEOUT_E = 12 ,
+ WIFIMACRX_ABORT_ACK_E = 13 ,
+ WIFIMACRX_REQ_IMPLICIT_FB_E = 14 ,
+ WIFIMACRX_CHAIN_MASK_E = 15 ,
+ WIFIMACRX_NAP_USER_E = 16 ,
+ WIFIMACRX_ABORT_REQUEST_E = 17 ,
+ WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 18 ,
+ WIFIPHYTX_ABORT_ACK_E = 19 ,
+ WIFIPHYTX_ABORT_REQUEST_E = 20 ,
+ WIFIPHYTX_PKT_END_E = 21 ,
+ WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 22 ,
+ WIFIPHYTX_REQUEST_CTRL_INFO_E = 23 ,
+ WIFIPHYTX_DATA_REQUEST_E = 24 ,
+ WIFIPHYTX_BF_CV_LOADING_DONE_E = 25 ,
+ WIFIPHYTX_NAP_ACK_E = 26 ,
+ WIFIPHYTX_NAP_DONE_E = 27 ,
+ WIFIPHYTX_OFF_ACK_E = 28 ,
+ WIFIPHYTX_ON_ACK_E = 29 ,
+ WIFIPHYTX_SYNTH_OFF_ACK_E = 30 ,
+ WIFIPHYTX_DEBUG16_E = 31 ,
+ WIFIMACTX_ABORT_REQUEST_E = 32 ,
+ WIFIMACTX_ABORT_ACK_E = 33 ,
+ WIFIMACTX_PKT_END_E = 34 ,
+ WIFIMACTX_PRE_PHY_DESC_E = 35 ,
+ WIFIMACTX_BF_PARAMS_COMMON_E = 36 ,
+ WIFIMACTX_BF_PARAMS_PER_USER_E = 37 ,
+ WIFIMACTX_PREFETCH_CV_E = 38 ,
+ WIFIMACTX_USER_DESC_COMMON_E = 39 ,
+ WIFIMACTX_USER_DESC_PER_USER_E = 40 ,
+ WIFIEXAMPLE_USER_TLV_16_E = 41 ,
+ WIFIEXAMPLE_TLV_16_E = 42 ,
+ WIFIMACTX_PHY_OFF_E = 43 ,
+ WIFIMACTX_PHY_ON_E = 44 ,
+ WIFIMACTX_SYNTH_OFF_E = 45 ,
+ WIFIMACTX_EXPECT_CBF_COMMON_E = 46 ,
+ WIFIMACTX_EXPECT_CBF_PER_USER_E = 47 ,
+ WIFIMACTX_PHY_DESC_E = 48 ,
+ WIFIMACTX_L_SIG_A_E = 49 ,
+ WIFIMACTX_L_SIG_B_E = 50 ,
+ WIFIMACTX_HT_SIG_E = 51 ,
+ WIFIMACTX_VHT_SIG_A_E = 52 ,
+ WIFIMACTX_VHT_SIG_B_SU20_E = 53 ,
+ WIFIMACTX_VHT_SIG_B_SU40_E = 54 ,
+ WIFIMACTX_VHT_SIG_B_SU80_E = 55 ,
+ WIFIMACTX_VHT_SIG_B_SU160_E = 56 ,
+ WIFIMACTX_VHT_SIG_B_MU20_E = 57 ,
+ WIFIMACTX_VHT_SIG_B_MU40_E = 58 ,
+ WIFIMACTX_VHT_SIG_B_MU80_E = 59 ,
+ WIFIMACTX_VHT_SIG_B_MU160_E = 60 ,
+ WIFIMACTX_SERVICE_E = 61 ,
+ WIFIMACTX_HE_SIG_A_SU_E = 62 ,
+ WIFIMACTX_HE_SIG_A_MU_DL_E = 63 ,
+ WIFIMACTX_HE_SIG_A_MU_UL_E = 64 ,
+ WIFIMACTX_HE_SIG_B1_MU_E = 65 ,
+ WIFIMACTX_HE_SIG_B2_MU_E = 66 ,
+ WIFIMACTX_HE_SIG_B2_OFDMA_E = 67 ,
+ WIFIMACTX_DELETE_CV_E = 68 ,
+ WIFIMACTX_MU_UPLINK_COMMON_E = 69 ,
+ WIFIMACTX_MU_UPLINK_USER_SETUP_E = 70 ,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_E = 71 ,
+ WIFIMACTX_PHY_NAP_E = 72 ,
+ WIFIMACTX_DEBUG_E = 73 ,
+ WIFIPHYRX_ABORT_ACK_E = 74 ,
+ WIFIPHYRX_GENERATED_CBF_DETAILS_E = 75 ,
+ WIFIPHYRX_RSSI_LEGACY_E = 76 ,
+ WIFIPHYRX_RSSI_HT_E = 77 ,
+ WIFIPHYRX_USER_INFO_E = 78 ,
+ WIFIPHYRX_PKT_END_E = 79 ,
+ WIFIPHYRX_DEBUG_E = 80 ,
+ WIFIPHYRX_CBF_TRANSFER_DONE_E = 81 ,
+ WIFIPHYRX_CBF_TRANSFER_ABORT_E = 82 ,
+ WIFIPHYRX_L_SIG_A_E = 83 ,
+ WIFIPHYRX_L_SIG_B_E = 84 ,
+ WIFIPHYRX_HT_SIG_E = 85 ,
+ WIFIPHYRX_VHT_SIG_A_E = 86 ,
+ WIFIPHYRX_VHT_SIG_B_SU20_E = 87 ,
+ WIFIPHYRX_VHT_SIG_B_SU40_E = 88 ,
+ WIFIPHYRX_VHT_SIG_B_SU80_E = 89 ,
+ WIFIPHYRX_VHT_SIG_B_SU160_E = 90 ,
+ WIFIPHYRX_VHT_SIG_B_MU20_E = 91 ,
+ WIFIPHYRX_VHT_SIG_B_MU40_E = 92 ,
+ WIFIPHYRX_VHT_SIG_B_MU80_E = 93 ,
+ WIFIPHYRX_VHT_SIG_B_MU160_E = 94 ,
+ WIFIPHYRX_HE_SIG_A_SU_E = 95 ,
+ WIFIPHYRX_HE_SIG_A_MU_DL_E = 96 ,
+ WIFIPHYRX_HE_SIG_A_MU_UL_E = 97 ,
+ WIFIPHYRX_HE_SIG_B1_MU_E = 98 ,
+ WIFIPHYRX_HE_SIG_B2_MU_E = 99 ,
+ WIFIPHYRX_HE_SIG_B2_OFDMA_E = 100 ,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_E = 101 ,
+ WIFIPHYRX_COMMON_USER_INFO_E = 102 ,
+ WIFIPHYRX_DATA_DONE_E = 103 ,
+ WIFIRECEIVE_RSSI_INFO_E = 104 ,
+ WIFIRECEIVE_USER_INFO_E = 105 ,
+ WIFIMIMO_CONTROL_INFO_E = 106 ,
+ WIFIRX_LOCATION_INFO_E = 107 ,
+ WIFICOEX_TX_REQ_E = 108 ,
+ WIFIDUMMY_E = 109 ,
+ WIFIRX_TIMING_OFFSET_INFO_E = 110 ,
+ WIFIEXAMPLE_TLV_32_NAME_E = 111 ,
+ WIFIMPDU_LIMIT_E = 112 ,
+ WIFINA_LENGTH_END_E = 113 ,
+ WIFIOLE_BUF_STATUS_E = 114 ,
+ WIFIPCU_PPDU_SETUP_DONE_E = 115 ,
+ WIFIPCU_PPDU_SETUP_END_E = 116 ,
+ WIFIPCU_PPDU_SETUP_INIT_E = 117 ,
+ WIFIPCU_PPDU_SETUP_START_E = 118 ,
+ WIFIPDG_FES_SETUP_E = 119 ,
+ WIFIPDG_RESPONSE_E = 120 ,
+ WIFIPDG_TX_REQ_E = 121 ,
+ WIFISCH_WAIT_INSTR_E = 122 ,
+ WIFISCHEDULER_TLV_E = 123 ,
+ WIFITQM_FLOW_EMPTY_STATUS_E = 124 ,
+ WIFITQM_FLOW_NOT_EMPTY_STATUS_E = 125 ,
+ WIFITQM_GEN_MPDU_LENGTH_LIST_E = 126 ,
+ WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 127 ,
+ WIFITQM_GEN_MPDUS_E = 128 ,
+ WIFITQM_GEN_MPDUS_STATUS_E = 129 ,
+ WIFITQM_REMOVE_MPDU_E = 130 ,
+ WIFITQM_REMOVE_MPDU_STATUS_E = 131 ,
+ WIFITQM_REMOVE_MSDU_E = 132 ,
+ WIFITQM_REMOVE_MSDU_STATUS_E = 133 ,
+ WIFITQM_UPDATE_TX_MPDU_COUNT_E = 134 ,
+ WIFITQM_WRITE_CMD_E = 135 ,
+ WIFIOFDMA_TRIGGER_DETAILS_E = 136 ,
+ WIFITX_DATA_E = 137 ,
+ WIFITX_FES_SETUP_E = 138 ,
+ WIFIRX_PACKET_E = 139 ,
+ WIFIEXPECTED_RESPONSE_E = 140 ,
+ WIFITX_MPDU_END_E = 141 ,
+ WIFITX_MPDU_START_E = 142 ,
+ WIFITX_MSDU_END_E = 143 ,
+ WIFITX_MSDU_START_E = 144 ,
+ WIFITX_SW_MODE_SETUP_E = 145 ,
+ WIFITXPCU_BUFFER_STATUS_E = 146 ,
+ WIFITXPCU_USER_BUFFER_STATUS_E = 147 ,
+ WIFIDATA_TO_TIME_CONFIG_E = 148 ,
+ WIFIEXAMPLE_USER_TLV_32_E = 149 ,
+ WIFIMPDU_INFO_E = 150 ,
+ WIFIPDG_USER_SETUP_E = 151 ,
+ WIFITX_11AH_SETUP_E = 152 ,
+ WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 153 ,
+ WIFITX_PEER_ENTRY_E = 154 ,
+ WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 155 ,
+ WIFIEXAMPLE_STRUCT_NAME_E = 156 ,
+ WIFIPCU_PPDU_SETUP_END_INFO_E = 157 ,
+ WIFIPPDU_RATE_SETTING_E = 158 ,
+ WIFIPROT_RATE_SETTING_E = 159 ,
+ WIFIRX_MPDU_DETAILS_E = 160 ,
+ WIFIEXAMPLE_USER_TLV_42_E = 161 ,
+ WIFIRX_MSDU_LINK_E = 162 ,
+ WIFIRX_REO_QUEUE_E = 163 ,
+ WIFIADDR_SEARCH_ENTRY_E = 164 ,
+ WIFISCHEDULER_CMD_E = 165 ,
+ WIFITX_FLUSH_E = 166 ,
+ WIFITQM_ENTRANCE_RING_E = 167 ,
+ WIFITX_DATA_WORD_E = 168 ,
+ WIFITX_MPDU_DETAILS_E = 169 ,
+ WIFITX_MPDU_LINK_E = 170 ,
+ WIFITX_MPDU_LINK_PTR_E = 171 ,
+ WIFITX_MPDU_QUEUE_HEAD_E = 172 ,
+ WIFITX_MPDU_QUEUE_EXT_E = 173 ,
+ WIFITX_MPDU_QUEUE_EXT_PTR_E = 174 ,
+ WIFITX_MSDU_DETAILS_E = 175 ,
+ WIFITX_MSDU_EXTENSION_E = 176 ,
+ WIFITX_MSDU_FLOW_E = 177 ,
+ WIFITX_MSDU_LINK_E = 178 ,
+ WIFITX_MSDU_LINK_ENTRY_PTR_E = 179 ,
+ WIFIRESPONSE_RATE_SETTING_E = 180 ,
+ WIFITXPCU_BUFFER_BASICS_E = 181 ,
+ WIFIUNIFORM_DESCRIPTOR_HEADER_E = 182 ,
+ WIFIUNIFORM_TQM_CMD_HEADER_E = 183 ,
+ WIFIUNIFORM_TQM_STATUS_HEADER_E = 184 ,
+ WIFIUSER_RATE_SETTING_E = 185 ,
+ WIFIWBM_BUFFER_RING_E = 186 ,
+ WIFIWBM_LINK_DESCRIPTOR_RING_E = 187 ,
+ WIFIWBM_RELEASE_RING_E = 188 ,
+ WIFITX_FLUSH_REQ_E = 189 ,
+ WIFIRX_MSDU_DETAILS_E = 190 ,
+ WIFITQM_WRITE_CMD_STATUS_E = 191 ,
+ WIFITQM_GET_MPDU_QUEUE_STATS_E = 192 ,
+ WIFITQM_GET_MSDU_FLOW_STATS_E = 193 ,
+ WIFIEXAMPLE_USER_CTLV_32_E = 194 ,
+ WIFITX_FES_STATUS_START_E = 195 ,
+ WIFITX_FES_STATUS_USER_PPDU_E = 196 ,
+ WIFITX_FES_STATUS_USER_RESPONSE_E = 197 ,
+ WIFITX_FES_STATUS_END_E = 198 ,
+ WIFIRX_TRIG_INFO_E = 199 ,
+ WIFIRXPCU_TX_SETUP_CLEAR_E = 200 ,
+ WIFIRX_FRAME_BITMAP_REQ_E = 201 ,
+ WIFIRX_FRAME_BITMAP_ACK_E = 202 ,
+ WIFICOEX_RX_STATUS_E = 203 ,
+ WIFIRX_START_PARAM_E = 204 ,
+ WIFIRX_PPDU_START_E = 205 ,
+ WIFIRX_PPDU_END_E = 206 ,
+ WIFIRX_MPDU_START_E = 207 ,
+ WIFIRX_MPDU_END_E = 208 ,
+ WIFIRX_MSDU_START_E = 209 ,
+ WIFIRX_MSDU_END_E = 210 ,
+ WIFIRX_ATTENTION_E = 211 ,
+ WIFIRECEIVED_RESPONSE_INFO_E = 212 ,
+ WIFIRX_PHY_SLEEP_E = 213 ,
+ WIFIRX_HEADER_E = 214 ,
+ WIFIRX_PEER_ENTRY_E = 215 ,
+ WIFIRX_FLUSH_E = 216 ,
+ WIFIRX_RESPONSE_REQUIRED_INFO_E = 217 ,
+ WIFIRX_FRAMELESS_BAR_DETAILS_E = 218 ,
+ WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 219 ,
+ WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 220 ,
+ WIFITX_CBF_INFO_E = 221 ,
+ WIFIPCU_PPDU_SETUP_USER_E = 222 ,
+ WIFIRX_MPDU_PCU_START_E = 223 ,
+ WIFIRX_PM_INFO_E = 224 ,
+ WIFIRX_USER_PPDU_END_E = 225 ,
+ WIFIRX_PRE_PPDU_START_E = 226 ,
+ WIFIRX_PREAMBLE_E = 227 ,
+ WIFITX_FES_SETUP_COMPLETE_E = 228 ,
+ WIFITX_LAST_MPDU_FETCHED_E = 229 ,
+ WIFITXDMA_STOP_REQUEST_E = 230 ,
+ WIFIRXPCU_SETUP_E = 231 ,
+ WIFIRXPCU_USER_SETUP_E = 232 ,
+ WIFITX_FES_STATUS_ACK_OR_BA_E = 233 ,
+ WIFITQM_ACKED_MPDU_E = 234 ,
+ WIFICOEX_TX_RESP_E = 235 ,
+ WIFICOEX_TX_STATUS_E = 236 ,
+ WIFIMACTX_COEX_PHY_CTRL_E = 237 ,
+ WIFICOEX_STATUS_BROADCAST_E = 238 ,
+ WIFIRESPONSE_START_STATUS_E = 239 ,
+ WIFIRESPONSE_END_STATUS_E = 240 ,
+ WIFICRYPTO_STATUS_E = 241 ,
+ WIFIRECEIVED_TRIGGER_INFO_E = 242 ,
+ WIFIREO_ENTRANCE_RING_E = 243 ,
+ WIFIRX_MPDU_LINK_E = 244 ,
+ WIFICOEX_TX_STOP_CTRL_E = 245 ,
+ WIFIRX_PPDU_ACK_REPORT_E = 246 ,
+ WIFIRX_PPDU_NO_ACK_REPORT_E = 247 ,
+ WIFISCH_COEX_STATUS_E = 248 ,
+ WIFISCHEDULER_COMMAND_STATUS_E = 249 ,
+ WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 250 ,
+ WIFITX_FES_STATUS_PROT_E = 251 ,
+ WIFITX_FES_STATUS_START_PPDU_E = 252 ,
+ WIFITX_FES_STATUS_START_PROT_E = 253 ,
+ WIFITXPCU_PHYTX_DEBUG32_E = 254 ,
+ WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 255 ,
+ WIFITX_MPDU_COUNT_TRANSFER_END_E = 256 ,
+ WIFIWHO_ANCHOR_OFFSET_E = 257 ,
+ WIFIWHO_ANCHOR_VALUE_E = 258 ,
+ WIFIWHO_CCE_INFO_E = 259 ,
+ WIFIWHO_COMMIT_E = 260 ,
+ WIFIWHO_COMMIT_DONE_E = 261 ,
+ WIFIWHO_FLUSH_E = 262 ,
+ WIFIWHO_L2_LLC_E = 263 ,
+ WIFIWHO_L2_PAYLOAD_E = 264 ,
+ WIFIWHO_L3_CHECKSUM_E = 265 ,
+ WIFIWHO_L3_INFO_E = 266 ,
+ WIFIWHO_L4_CHECKSUM_E = 267 ,
+ WIFIWHO_L4_INFO_E = 268 ,
+ WIFIWHO_MSDU_E = 269 ,
+ WIFIWHO_MSDU_MISC_E = 270 ,
+ WIFIWHO_PACKET_DATA_E = 271 ,
+ WIFIWHO_PACKET_HDR_E = 272 ,
+ WIFIWHO_PPDU_END_E = 273 ,
+ WIFIWHO_PPDU_START_E = 274 ,
+ WIFIWHO_TSO_E = 275 ,
+ WIFIWHO_WMAC_HEADER_PV0_E = 276 ,
+ WIFIWHO_WMAC_HEADER_PV1_E = 277 ,
+ WIFIWHO_WMAC_IV_E = 278 ,
+ WIFIMPDU_INFO_END_E = 279 ,
+ WIFIMPDU_INFO_BITMAP_E = 280 ,
+ WIFITX_QUEUE_EXTENSION_E = 281 ,
+ WIFIRX_PEER_ENTRY_DETAILS_E = 282 ,
+ WIFIRX_REO_QUEUE_REFERENCE_E = 283 ,
+ WIFIRX_REO_QUEUE_EXT_E = 284 ,
+ WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 285 ,
+ WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 286 ,
+ WIFITQM_ACKED_MPDU_STATUS_E = 287 ,
+ WIFITQM_ADD_MSDU_STATUS_E = 288 ,
+ WIFIRX_MPDU_LINK_PTR_E = 289 ,
+ WIFIREO_DESTINATION_RING_E = 290 ,
+ WIFITQM_LIST_GEN_DONE_E = 291 ,
+ WIFIWHO_TERMINATE_E = 292 ,
+ WIFITX_LAST_MPDU_END_E = 293 ,
+ WIFITX_CV_DATA_E = 294 ,
+ WIFITCL_ENTRANCE_FROM_PPE_RING_E = 295 ,
+ WIFIPPDU_TX_END_E = 296 ,
+ WIFIPROT_TX_END_E = 297 ,
+ WIFIPDG_RESPONSE_RATE_SETTING_E = 298 ,
+ WIFIMPDU_INFO_GLOBAL_END_E = 299 ,
+ WIFITQM_SCH_INSTR_GLOBAL_END_E = 300 ,
+ WIFIRX_PPDU_END_USER_STATS_E = 301 ,
+ WIFIRX_PPDU_END_USER_STATS_EXT_E = 302 ,
+ WIFINO_ACK_REPORT_E = 303 ,
+ WIFIACK_REPORT_E = 304 ,
+ WIFIUNIFORM_REO_CMD_HEADER_E = 305 ,
+ WIFIREO_GET_QUEUE_STATS_E = 306 ,
+ WIFIREO_FLUSH_QUEUE_E = 307 ,
+ WIFIREO_FLUSH_CACHE_E = 308 ,
+ WIFIREO_UNBLOCK_CACHE_E = 309 ,
+ WIFIUNIFORM_REO_STATUS_HEADER_E = 310 ,
+ WIFIREO_GET_QUEUE_STATS_STATUS_E = 311 ,
+ WIFIREO_FLUSH_QUEUE_STATUS_E = 312 ,
+ WIFIREO_FLUSH_CACHE_STATUS_E = 313 ,
+ WIFIREO_UNBLOCK_CACHE_STATUS_E = 314 ,
+ WIFITQM_FLUSH_CACHE_E = 315 ,
+ WIFITQM_UNBLOCK_CACHE_E = 316 ,
+ WIFITQM_FLUSH_CACHE_STATUS_E = 317 ,
+ WIFITQM_UNBLOCK_CACHE_STATUS_E = 318 ,
+ WIFIRX_PPDU_END_STATUS_DONE_E = 319 ,
+ WIFIRX_STATUS_BUFFER_DONE_E = 320 ,
+ WIFIBUFFER_ADDR_INFO_E = 321 ,
+ WIFIRX_MSDU_DESC_INFO_E = 322 ,
+ WIFIRX_MPDU_DESC_INFO_E = 323 ,
+ WIFITCL_DATA_CMD_E = 324 ,
+ WIFITCL_GSE_CMD_E = 325 ,
+ WIFITCL_EXIT_BASE_E = 326 ,
+ WIFITCL_COMPACT_EXIT_RING_E = 327 ,
+ WIFITCL_REGULAR_EXIT_RING_E = 328 ,
+ WIFITCL_EXTENDED_EXIT_RING_E = 329 ,
+ WIFIUPLINK_COMMON_INFO_E = 330 ,
+ WIFIUPLINK_USER_SETUP_INFO_E = 331 ,
+ WIFITX_DATA_SYNC_E = 332 ,
+ WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 333 ,
+ WIFITCL_STATUS_RING_E = 334 ,
+ WIFITQM_GET_MPDU_HEAD_INFO_E = 335 ,
+ WIFITQM_SYNC_CMD_E = 336 ,
+ WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 337 ,
+ WIFITQM_SYNC_CMD_STATUS_E = 338 ,
+ WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 339 ,
+ WIFITQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 340 ,
+ WIFIREO_FLUSH_TIMEOUT_LIST_E = 341 ,
+ WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 342 ,
+ WIFIREO_TO_PPE_RING_E = 343 ,
+ WIFIRX_MPDU_INFO_E = 344 ,
+ WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 345 ,
+ WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 346 ,
+ WIFIEXAMPLE_USER_TLV_32_NAME_E = 347 ,
+ WIFIRX_PPDU_START_USER_INFO_E = 348 ,
+ WIFIRX_RXPCU_CLASSIFICATION_OVERVIEW_E = 349 ,
+ WIFIRX_RING_MASK_E = 350 ,
+ WIFIWHO_CLASSIFY_INFO_E = 351 ,
+ WIFITXPT_CLASSIFY_INFO_E = 352 ,
+ WIFIRXPT_CLASSIFY_INFO_E = 353 ,
+ WIFITX_FLOW_SEARCH_ENTRY_E = 354 ,
+ WIFIRX_FLOW_SEARCH_ENTRY_E = 355 ,
+ WIFIRECEIVED_TRIGGER_INFO_DETAILS_E = 356 ,
+ WIFICOEX_MAC_NAP_E = 357 ,
+ WIFIMACRX_ABORT_REQUEST_INFO_E = 358 ,
+ WIFIMACTX_ABORT_REQUEST_INFO_E = 359 ,
+ WIFIPHYRX_ABORT_REQUEST_INFO_E = 360 ,
+ WIFIPHYTX_ABORT_REQUEST_INFO_E = 361 ,
+ WIFIRXPCU_PPDU_END_INFO_E = 362 ,
+ WIFIWHO_MESH_CONTROL_E = 363 ,
+ WIFIL_SIG_A_INFO_E = 364 ,
+ WIFIL_SIG_B_INFO_E = 365 ,
+ WIFIHT_SIG_INFO_E = 366 ,
+ WIFIVHT_SIG_A_INFO_E = 367 ,
+ WIFIVHT_SIG_B_SU20_INFO_E = 368 ,
+ WIFIVHT_SIG_B_SU40_INFO_E = 369 ,
+ WIFIVHT_SIG_B_SU80_INFO_E = 370 ,
+ WIFIVHT_SIG_B_SU160_INFO_E = 371 ,
+ WIFIVHT_SIG_B_MU20_INFO_E = 372 ,
+ WIFIVHT_SIG_B_MU40_INFO_E = 373 ,
+ WIFIVHT_SIG_B_MU80_INFO_E = 374 ,
+ WIFIVHT_SIG_B_MU160_INFO_E = 375 ,
+ WIFISERVICE_INFO_E = 376 ,
+ WIFIHE_SIG_A_SU_INFO_E = 377 ,
+ WIFIHE_SIG_A_MU_DL_INFO_E = 378 ,
+ WIFIHE_SIG_A_MU_UL_INFO_E = 379 ,
+ WIFIHE_SIG_B1_MU_INFO_E = 380 ,
+ WIFIHE_SIG_B2_MU_INFO_E = 381 ,
+ WIFIHE_SIG_B2_OFDMA_INFO_E = 382 ,
+ WIFIPDG_SW_MODE_BW_START_E = 383 ,
+ WIFIPDG_SW_MODE_BW_END_E = 384 ,
+ WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 385 ,
+ WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 386 ,
+ WIFISCHEDULER_END_E = 387 ,
+ WIFIPEER_TABLE_ENTRY_E = 388 ,
+ WIFISW_PEER_INFO_E = 389 ,
+ WIFIRXOLE_CCE_CLASSIFY_INFO_E = 390 ,
+ WIFITCL_CCE_CLASSIFY_INFO_E = 391 ,
+ WIFIRXOLE_CCE_INFO_E = 392 ,
+ WIFITCL_CCE_INFO_E = 393 ,
+ WIFITCL_CCE_SUPERRULE_E = 394 ,
+ WIFICCE_RULE_E = 395 ,
+ WIFIRX_PPDU_START_DROPPED_E = 396 ,
+ WIFIRX_PPDU_END_DROPPED_E = 397 ,
+ WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 398 ,
+ WIFIRX_MPDU_START_DROPPED_E = 399 ,
+ WIFIRX_MSDU_START_DROPPED_E = 400 ,
+ WIFIRX_MSDU_END_DROPPED_E = 401 ,
+ WIFIRX_MPDU_END_DROPPED_E = 402 ,
+ WIFIRX_ATTENTION_DROPPED_E = 403 ,
+ WIFITXPCU_USER_SETUP_E = 404 ,
+ WIFIRXPCU_USER_SETUP_EXT_E = 405 ,
+ WIFICE_SRC_DESC_E = 406 ,
+ WIFICE_STAT_DESC_E = 407 ,
+ WIFIRXOLE_CCE_SUPERRULE_E = 408 ,
+ WIFITX_RATE_STATS_INFO_E = 409 ,
+ WIFICMD_PART_0_END_E = 410 ,
+ WIFIMACTX_SYNTH_ON_E = 411 ,
+ WIFISCH_CRITICAL_TLV_REFERENCE_E = 412 ,
+ WIFITQM_MPDU_GLOBAL_START_E = 413 ,
+ WIFIEXAMPLE_TLV_32_E = 414 ,
+ WIFITQM_UPDATE_TX_MSDU_FLOW_E = 415 ,
+ WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 416 ,
+ WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 417 ,
+ WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 418 ,
+ WIFIREO_UPDATE_RX_REO_QUEUE_E = 419 ,
+ WIFICE_DST_DESC_E = 420 ,
+ WIFITQM_MPDU_QUEUE_EMPTY_STATUS_E = 421 ,
+ WIFITQM_2_SCH_MPDU_AVAILABLE_E = 422 ,
+ WIFIPDG_TRIG_RESPONSE_E = 423 ,
+ WIFITRIGGER_RESPONSE_TX_DONE_E = 424 ,
+ WIFIABORT_FROM_PHYRX_DETAILS_E = 425 ,
+ WIFISCH_TQM_CMD_WRAPPER_E = 426 ,
+ WIFIMPDUS_AVAILABLE_E = 427 ,
+ WIFIRECEIVED_RESPONSE_INFO_PART2_E = 428 ,
+ WIFIPHYRX_PKT_END_INFO_E = 429 ,
+ WIFIPHYRX_TX_START_TIMING_E = 430 ,
+ WIFITXPCU_PREAMBLE_DONE_E = 431 ,
+ WIFINDP_PREAMBLE_DONE_E = 432 ,
+ WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 433 ,
+ WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 434 ,
+ WIFIMACTX_CLEAR_PREV_TX_INFO_E = 435 ,
+ WIFITX_PUNCTURE_SETUP_E = 436 ,
+ WIFITX_PUNCTURE_PATTERN_E = 437 ,
+ WIFIR2R_STATUS_END_E = 438 ,
+ WIFIMACTX_PREFETCH_CV_COMMON_E = 439 ,
+ WIFIEND_OF_FLUSH_MARKER_E = 440 ,
+ WIFIUPLINK_COMMON_INFO_PUNC_E = 441 ,
+ WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 442 ,
+ WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 443 ,
+ WIFIRECEIVED_RESPONSE_USER_7_0_E = 444 ,
+ WIFIRECEIVED_RESPONSE_USER_15_8_E = 445 ,
+ WIFIRECEIVED_RESPONSE_USER_23_16_E = 446 ,
+ WIFIRECEIVED_RESPONSE_USER_31_24_E = 447 ,
+ WIFIRECEIVED_RESPONSE_USER_36_32_E = 448 ,
+ WIFIRECEIVED_RESPONSE_USER_INFO_E = 449 ,
+ WIFITX_LOOPBACK_SETUP_E = 450 ,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 451 ,
+ WIFISCH_WAIT_INSTR_TX_PATH_E = 452 ,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 453 ,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 454 ,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 455 ,
+ WIFITX_WUR_DATA_E = 456 ,
+ WIFIRX_PPDU_END_START_E = 457 ,
+ WIFIRX_PPDU_END_MIDDLE_E = 458 ,
+ WIFIRX_PPDU_END_LAST_E = 459 ,
+ WIFIRECEIVE_USER_INFO_L1_E = 460 ,
+ WIFIMIMO_CONTROL_INFO_L1_E = 461 ,
+ WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 462 ,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 463 ,
+ WIFISRP_INFO_E = 464 ,
+ WIFIOBSS_SR_INFO_E = 465 ,
+ WIFISCHEDULER_SW_MSG_STATUS_E = 466 ,
+ WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 467 ,
+ WIFIRXPCU_SETUP_COMPLETE_E = 468 ,
+ WIFISNOOP_PPDU_START_E = 469 ,
+ WIFISNOOP_MPDU_USR_DBG_INFO_E = 470 ,
+ WIFISNOOP_MSDU_USR_DBG_INFO_E = 471 ,
+ WIFISNOOP_MSDU_USR_DATA_E = 472 ,
+ WIFISNOOP_MPDU_USR_STAT_INFO_E = 473 ,
+ WIFISNOOP_PPDU_END_E = 474 ,
+ WIFISNOOP_SPARE_E = 475 ,
+ WIFIMACTX_PREFETCH_CV_BULK_E = 476 ,
+ WIFIMACTX_PREFETCH_CV_BULK_USER_E = 477 ,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 478 ,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 479 ,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 480 ,
+ WIFISW_MONITOR_RING_E = 481 ,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 482 ,
+ WIFISCH_TLV_WRAPPER_E = 483 ,
+ WIFISCHEDULER_STATUS_WRAPPER_E = 484 ,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_EXPECT_RX_E = 485 ,
+ WIFITX_HW_MPDU_LINK_E = 486 ,
+ WIFITX_HW_MPDU_LINK_PTR_E = 487 ,
+ WIFITX_HW_MPDU_QUEUE_EXT_E = 488 ,
+ WIFITX_HW_MPDU_QUEUE_HEAD_E = 489 ,
+ WIFITQM_ADD_MPDUS_E = 490 ,
+ WIFITQM_WRITE_BACK_MPDU_INFO_E = 491 ,
+ WIFIUNIFORM_TQM_LITE_STATUS_HEADER_E = 492 ,
+ WIFITQM_ADD_MPDUS_STATUS_E = 493 ,
+ WIFITQM_MPDU_RELEASE_STATUS_E = 494 ,
+ WIFITQM_WRITE_BACK_MPDU_INFO_STATUS_E = 495 ,
+ WIFITX_HW_MPDU_DETAILS_E = 496 ,
+ WIFITLV_BASE_E = 511
+
+} tlv_tag_def__e;
+
+#endif
diff --git a/hw/wcn6450/v1/tx_msdu_extension.h b/hw/wcn6450/v1/tx_msdu_extension.h
new file mode 100644
index 0000000..f4822ae
--- /dev/null
+++ b/hw/wcn6450/v1/tx_msdu_extension.h
@@ -0,0 +1,247 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _TX_MSDU_EXTENSION_H_
+#define _TX_MSDU_EXTENSION_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18
+
+struct tx_msdu_extension {
+ uint32_t tso_enable : 1,
+ reserved_0a : 6,
+ tcp_flag : 9,
+ tcp_flag_mask : 9,
+ reserved_0b : 7;
+ uint32_t l2_length : 16,
+ ip_length : 16;
+ uint32_t tcp_seq_number : 32;
+ uint32_t ip_identification : 16,
+ udp_length : 16;
+ uint32_t checksum_offset : 14,
+ partial_checksum_en : 1,
+ reserved_4a : 1,
+ payload_start_offset : 14,
+ reserved_4b : 2;
+ uint32_t payload_end_offset : 14,
+ reserved_5a : 2,
+ wds : 1,
+ reserved_5b : 15;
+ uint32_t buf0_ptr_31_0 : 32;
+ uint32_t buf0_ptr_39_32 : 8,
+ reserved_7a : 8,
+ buf0_len : 16;
+ uint32_t buf1_ptr_31_0 : 32;
+ uint32_t buf1_ptr_39_32 : 8,
+ reserved_9a : 8,
+ buf1_len : 16;
+ uint32_t buf2_ptr_31_0 : 32;
+ uint32_t buf2_ptr_39_32 : 8,
+ reserved_11a : 8,
+ buf2_len : 16;
+ uint32_t buf3_ptr_31_0 : 32;
+ uint32_t buf3_ptr_39_32 : 8,
+ reserved_13a : 8,
+ buf3_len : 16;
+ uint32_t buf4_ptr_31_0 : 32;
+ uint32_t buf4_ptr_39_32 : 8,
+ reserved_15a : 8,
+ buf4_len : 16;
+ uint32_t buf5_ptr_31_0 : 32;
+ uint32_t buf5_ptr_39_32 : 8,
+ reserved_17a : 8,
+ buf5_len : 16;
+};
+
+#define TX_MSDU_EXTENSION_0_TSO_ENABLE_OFFSET 0x00000000
+#define TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB 0
+#define TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK 0x00000001
+
+#define TX_MSDU_EXTENSION_0_RESERVED_0A_OFFSET 0x00000000
+#define TX_MSDU_EXTENSION_0_RESERVED_0A_LSB 1
+#define TX_MSDU_EXTENSION_0_RESERVED_0A_MASK 0x0000007e
+
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_OFFSET 0x00000000
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_LSB 7
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK 0x0000ff80
+
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_OFFSET 0x00000000
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_LSB 16
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_MASK 0x01ff0000
+
+#define TX_MSDU_EXTENSION_0_RESERVED_0B_OFFSET 0x00000000
+#define TX_MSDU_EXTENSION_0_RESERVED_0B_LSB 25
+#define TX_MSDU_EXTENSION_0_RESERVED_0B_MASK 0xfe000000
+
+#define TX_MSDU_EXTENSION_1_L2_LENGTH_OFFSET 0x00000004
+#define TX_MSDU_EXTENSION_1_L2_LENGTH_LSB 0
+#define TX_MSDU_EXTENSION_1_L2_LENGTH_MASK 0x0000ffff
+
+#define TX_MSDU_EXTENSION_1_IP_LENGTH_OFFSET 0x00000004
+#define TX_MSDU_EXTENSION_1_IP_LENGTH_LSB 16
+#define TX_MSDU_EXTENSION_1_IP_LENGTH_MASK 0xffff0000
+
+#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_OFFSET 0x00000008
+#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_LSB 0
+#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_MASK 0xffffffff
+
+#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_OFFSET 0x0000000c
+#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_LSB 0
+#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_MASK 0x0000ffff
+
+#define TX_MSDU_EXTENSION_3_UDP_LENGTH_OFFSET 0x0000000c
+#define TX_MSDU_EXTENSION_3_UDP_LENGTH_LSB 16
+#define TX_MSDU_EXTENSION_3_UDP_LENGTH_MASK 0xffff0000
+
+#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_OFFSET 0x00000010
+#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_LSB 0
+#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_MASK 0x00003fff
+
+#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010
+#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_LSB 14
+#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_MASK 0x00004000
+
+#define TX_MSDU_EXTENSION_4_RESERVED_4A_OFFSET 0x00000010
+#define TX_MSDU_EXTENSION_4_RESERVED_4A_LSB 15
+#define TX_MSDU_EXTENSION_4_RESERVED_4A_MASK 0x00008000
+
+#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_OFFSET 0x00000010
+#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_LSB 16
+#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_MASK 0x3fff0000
+
+#define TX_MSDU_EXTENSION_4_RESERVED_4B_OFFSET 0x00000010
+#define TX_MSDU_EXTENSION_4_RESERVED_4B_LSB 30
+#define TX_MSDU_EXTENSION_4_RESERVED_4B_MASK 0xc0000000
+
+#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_OFFSET 0x00000014
+#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_LSB 0
+#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_MASK 0x00003fff
+
+#define TX_MSDU_EXTENSION_5_RESERVED_5A_OFFSET 0x00000014
+#define TX_MSDU_EXTENSION_5_RESERVED_5A_LSB 14
+#define TX_MSDU_EXTENSION_5_RESERVED_5A_MASK 0x0000c000
+
+#define TX_MSDU_EXTENSION_5_WDS_OFFSET 0x00000014
+#define TX_MSDU_EXTENSION_5_WDS_LSB 16
+#define TX_MSDU_EXTENSION_5_WDS_MASK 0x00010000
+
+#define TX_MSDU_EXTENSION_5_RESERVED_5B_OFFSET 0x00000014
+#define TX_MSDU_EXTENSION_5_RESERVED_5B_LSB 17
+#define TX_MSDU_EXTENSION_5_RESERVED_5B_MASK 0xfffe0000
+
+#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 0x00000018
+#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_LSB 0
+#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 0xffffffff
+
+#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_OFFSET 0x0000001c
+#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_LSB 0
+#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 0x000000ff
+
+#define TX_MSDU_EXTENSION_7_RESERVED_7A_OFFSET 0x0000001c
+#define TX_MSDU_EXTENSION_7_RESERVED_7A_LSB 8
+#define TX_MSDU_EXTENSION_7_RESERVED_7A_MASK 0x0000ff00
+
+#define TX_MSDU_EXTENSION_7_BUF0_LEN_OFFSET 0x0000001c
+#define TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 16
+#define TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 0xffff0000
+
+#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_OFFSET 0x00000020
+#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_LSB 0
+#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_MASK 0xffffffff
+
+#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_OFFSET 0x00000024
+#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_LSB 0
+#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_MASK 0x000000ff
+
+#define TX_MSDU_EXTENSION_9_RESERVED_9A_OFFSET 0x00000024
+#define TX_MSDU_EXTENSION_9_RESERVED_9A_LSB 8
+#define TX_MSDU_EXTENSION_9_RESERVED_9A_MASK 0x0000ff00
+
+#define TX_MSDU_EXTENSION_9_BUF1_LEN_OFFSET 0x00000024
+#define TX_MSDU_EXTENSION_9_BUF1_LEN_LSB 16
+#define TX_MSDU_EXTENSION_9_BUF1_LEN_MASK 0xffff0000
+
+#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_OFFSET 0x00000028
+#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_LSB 0
+#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_MASK 0xffffffff
+
+#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_OFFSET 0x0000002c
+#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_LSB 0
+#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_MASK 0x000000ff
+
+#define TX_MSDU_EXTENSION_11_RESERVED_11A_OFFSET 0x0000002c
+#define TX_MSDU_EXTENSION_11_RESERVED_11A_LSB 8
+#define TX_MSDU_EXTENSION_11_RESERVED_11A_MASK 0x0000ff00
+
+#define TX_MSDU_EXTENSION_11_BUF2_LEN_OFFSET 0x0000002c
+#define TX_MSDU_EXTENSION_11_BUF2_LEN_LSB 16
+#define TX_MSDU_EXTENSION_11_BUF2_LEN_MASK 0xffff0000
+
+#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_OFFSET 0x00000030
+#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_LSB 0
+#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_MASK 0xffffffff
+
+#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_OFFSET 0x00000034
+#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_LSB 0
+#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_MASK 0x000000ff
+
+#define TX_MSDU_EXTENSION_13_RESERVED_13A_OFFSET 0x00000034
+#define TX_MSDU_EXTENSION_13_RESERVED_13A_LSB 8
+#define TX_MSDU_EXTENSION_13_RESERVED_13A_MASK 0x0000ff00
+
+#define TX_MSDU_EXTENSION_13_BUF3_LEN_OFFSET 0x00000034
+#define TX_MSDU_EXTENSION_13_BUF3_LEN_LSB 16
+#define TX_MSDU_EXTENSION_13_BUF3_LEN_MASK 0xffff0000
+
+#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_OFFSET 0x00000038
+#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_LSB 0
+#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_MASK 0xffffffff
+
+#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_OFFSET 0x0000003c
+#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_LSB 0
+#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_MASK 0x000000ff
+
+#define TX_MSDU_EXTENSION_15_RESERVED_15A_OFFSET 0x0000003c
+#define TX_MSDU_EXTENSION_15_RESERVED_15A_LSB 8
+#define TX_MSDU_EXTENSION_15_RESERVED_15A_MASK 0x0000ff00
+
+#define TX_MSDU_EXTENSION_15_BUF4_LEN_OFFSET 0x0000003c
+#define TX_MSDU_EXTENSION_15_BUF4_LEN_LSB 16
+#define TX_MSDU_EXTENSION_15_BUF4_LEN_MASK 0xffff0000
+
+#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_OFFSET 0x00000040
+#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_LSB 0
+#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_MASK 0xffffffff
+
+#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_OFFSET 0x00000044
+#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_LSB 0
+#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_MASK 0x000000ff
+
+#define TX_MSDU_EXTENSION_17_RESERVED_17A_OFFSET 0x00000044
+#define TX_MSDU_EXTENSION_17_RESERVED_17A_LSB 8
+#define TX_MSDU_EXTENSION_17_RESERVED_17A_MASK 0x0000ff00
+
+#define TX_MSDU_EXTENSION_17_BUF5_LEN_OFFSET 0x00000044
+#define TX_MSDU_EXTENSION_17_BUF5_LEN_LSB 16
+#define TX_MSDU_EXTENSION_17_BUF5_LEN_MASK 0xffff0000
+
+#endif
diff --git a/hw/wcn6450/v1/tx_rate_stats_info.h b/hw/wcn6450/v1/tx_rate_stats_info.h
new file mode 100644
index 0000000..0e18d62
--- /dev/null
+++ b/hw/wcn6450/v1/tx_rate_stats_info.h
@@ -0,0 +1,87 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _TX_RATE_STATS_INFO_H_
+#define _TX_RATE_STATS_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2
+
+struct tx_rate_stats_info {
+ uint32_t tx_rate_stats_info_valid : 1,
+ transmit_bw : 2,
+ transmit_pkt_type : 4,
+ transmit_stbc : 1,
+ transmit_ldpc : 1,
+ transmit_sgi : 2,
+ transmit_mcs : 4,
+ ofdma_transmission : 1,
+ tones_in_ru : 12,
+ reserved_0a : 4;
+ uint32_t ppdu_transmission_tsf : 32;
+};
+
+#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_LSB 0
+#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_MASK 0x00000001
+
+#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_LSB 1
+#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_MASK 0x00000006
+
+#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_LSB 3
+#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_MASK 0x00000078
+
+#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_LSB 7
+#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_MASK 0x00000080
+
+#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_LSB 8
+#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_MASK 0x00000100
+
+#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_LSB 9
+#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_MASK 0x00000600
+
+#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_LSB 11
+#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_MASK 0x00007800
+
+#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_LSB 15
+#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_MASK 0x00008000
+
+#define TX_RATE_STATS_INFO_0_TONES_IN_RU_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_TONES_IN_RU_LSB 16
+#define TX_RATE_STATS_INFO_0_TONES_IN_RU_MASK 0x0fff0000
+
+#define TX_RATE_STATS_INFO_0_RESERVED_0A_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_RESERVED_0A_LSB 28
+#define TX_RATE_STATS_INFO_0_RESERVED_0A_MASK 0xf0000000
+
+#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004
+#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_LSB 0
+#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/uniform_descriptor_header.h b/hw/wcn6450/v1/uniform_descriptor_header.h
new file mode 100644
index 0000000..d68432f
--- /dev/null
+++ b/hw/wcn6450/v1/uniform_descriptor_header.h
@@ -0,0 +1,47 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
+#define _UNIFORM_DESCRIPTOR_HEADER_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1
+
+struct uniform_descriptor_header {
+ uint32_t owner : 4,
+ buffer_type : 4,
+ reserved_0a : 24;
+};
+
+#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_OFFSET 0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_LSB 0
+#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_MASK 0x0000000f
+
+#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_OFFSET 0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_LSB 4
+#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_MASK 0x000000f0
+
+#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_OFFSET 0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_LSB 8
+#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_MASK 0xffffff00
+
+#endif
diff --git a/hw/wcn6450/v1/uniform_reo_cmd_header.h b/hw/wcn6450/v1/uniform_reo_cmd_header.h
new file mode 100644
index 0000000..fdc8da7
--- /dev/null
+++ b/hw/wcn6450/v1/uniform_reo_cmd_header.h
@@ -0,0 +1,47 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _UNIFORM_REO_CMD_HEADER_H_
+#define _UNIFORM_REO_CMD_HEADER_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1
+
+struct uniform_reo_cmd_header {
+ uint32_t reo_cmd_number : 16,
+ reo_status_required : 1,
+ reserved_0a : 15;
+};
+
+#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_OFFSET 0x00000000
+#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_LSB 0
+#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_MASK 0x0000ffff
+
+#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_LSB 16
+#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_MASK 0x00010000
+
+#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_OFFSET 0x00000000
+#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_LSB 17
+#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_MASK 0xfffe0000
+
+#endif
diff --git a/hw/wcn6450/v1/uniform_reo_status_header.h b/hw/wcn6450/v1/uniform_reo_status_header.h
new file mode 100644
index 0000000..0f6014b
--- /dev/null
+++ b/hw/wcn6450/v1/uniform_reo_status_header.h
@@ -0,0 +1,57 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _UNIFORM_REO_STATUS_HEADER_H_
+#define _UNIFORM_REO_STATUS_HEADER_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2
+
+struct uniform_reo_status_header {
+ uint32_t reo_status_number : 16,
+ cmd_execution_time : 10,
+ reo_cmd_execution_status : 2,
+ reserved_0a : 4;
+ uint32_t timestamp : 32;
+};
+
+#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_LSB 0
+#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_LSB 16
+#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_LSB 26
+#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_OFFSET 0x00000000
+#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_LSB 28
+#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_MASK 0xf0000000
+
+#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_OFFSET 0x00000004
+#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_LSB 0
+#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_MASK 0xffffffff
+
+#endif
diff --git a/hw/wcn6450/v1/vht_sig_a_info.h b/hw/wcn6450/v1/vht_sig_a_info.h
new file mode 100644
index 0000000..16bc396
--- /dev/null
+++ b/hw/wcn6450/v1/vht_sig_a_info.h
@@ -0,0 +1,117 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _VHT_SIG_A_INFO_H_
+#define _VHT_SIG_A_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2
+
+struct vht_sig_a_info {
+ uint32_t bandwidth : 2,
+ vhta_reserved_0 : 1,
+ stbc : 1,
+ group_id : 6,
+ n_sts : 12,
+ txop_ps_not_allowed : 1,
+ vhta_reserved_0b : 1,
+ reserved_0 : 8;
+ uint32_t gi_setting : 2,
+ su_mu_coding : 1,
+ ldpc_extra_symbol : 1,
+ mcs : 4,
+ beamformed : 1,
+ vhta_reserved_1 : 1,
+ crc : 8,
+ tail : 6,
+ reserved_1 : 8;
+};
+
+#define VHT_SIG_A_INFO_0_BANDWIDTH_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_0_BANDWIDTH_LSB 0
+#define VHT_SIG_A_INFO_0_BANDWIDTH_MASK 0x00000003
+
+#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_LSB 2
+#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_MASK 0x00000004
+
+#define VHT_SIG_A_INFO_0_STBC_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_0_STBC_LSB 3
+#define VHT_SIG_A_INFO_0_STBC_MASK 0x00000008
+
+#define VHT_SIG_A_INFO_0_GROUP_ID_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_0_GROUP_ID_LSB 4
+#define VHT_SIG_A_INFO_0_GROUP_ID_MASK 0x000003f0
+
+#define VHT_SIG_A_INFO_0_N_STS_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_0_N_STS_LSB 10
+#define VHT_SIG_A_INFO_0_N_STS_MASK 0x003ffc00
+
+#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_LSB 22
+#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_MASK 0x00400000
+
+#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_LSB 23
+#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_MASK 0x00800000
+
+#define VHT_SIG_A_INFO_0_RESERVED_0_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_0_RESERVED_0_LSB 24
+#define VHT_SIG_A_INFO_0_RESERVED_0_MASK 0xff000000
+
+#define VHT_SIG_A_INFO_1_GI_SETTING_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_1_GI_SETTING_LSB 0
+#define VHT_SIG_A_INFO_1_GI_SETTING_MASK 0x00000003
+
+#define VHT_SIG_A_INFO_1_SU_MU_CODING_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_1_SU_MU_CODING_LSB 2
+#define VHT_SIG_A_INFO_1_SU_MU_CODING_MASK 0x00000004
+
+#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_LSB 3
+#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000008
+
+#define VHT_SIG_A_INFO_1_MCS_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_1_MCS_LSB 4
+#define VHT_SIG_A_INFO_1_MCS_MASK 0x000000f0
+
+#define VHT_SIG_A_INFO_1_BEAMFORMED_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_1_BEAMFORMED_LSB 8
+#define VHT_SIG_A_INFO_1_BEAMFORMED_MASK 0x00000100
+
+#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_LSB 9
+#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_MASK 0x00000200
+
+#define VHT_SIG_A_INFO_1_CRC_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_1_CRC_LSB 10
+#define VHT_SIG_A_INFO_1_CRC_MASK 0x0003fc00
+
+#define VHT_SIG_A_INFO_1_TAIL_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_1_TAIL_LSB 18
+#define VHT_SIG_A_INFO_1_TAIL_MASK 0x00fc0000
+
+#define VHT_SIG_A_INFO_1_RESERVED_1_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_1_RESERVED_1_LSB 24
+#define VHT_SIG_A_INFO_1_RESERVED_1_MASK 0xff000000
+
+#endif
diff --git a/hw/wcn6450/v1/wbm_buffer_ring.h b/hw/wcn6450/v1/wbm_buffer_ring.h
new file mode 100644
index 0000000..bfb268f
--- /dev/null
+++ b/hw/wcn6450/v1/wbm_buffer_ring.h
@@ -0,0 +1,51 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _WBM_BUFFER_RING_H_
+#define _WBM_BUFFER_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+
+#define NUM_OF_DWORDS_WBM_BUFFER_RING 2
+
+struct wbm_buffer_ring {
+ struct buffer_addr_info buf_addr_info;
+};
+
+#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#endif
diff --git a/hw/wcn6450/v1/wbm_link_descriptor_ring.h b/hw/wcn6450/v1/wbm_link_descriptor_ring.h
new file mode 100644
index 0000000..70820a1
--- /dev/null
+++ b/hw/wcn6450/v1/wbm_link_descriptor_ring.h
@@ -0,0 +1,51 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _WBM_LINK_DESCRIPTOR_RING_H_
+#define _WBM_LINK_DESCRIPTOR_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+
+#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2
+
+struct wbm_link_descriptor_ring {
+ struct buffer_addr_info desc_addr_info;
+};
+
+#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#endif
diff --git a/hw/wcn6450/v1/wbm_release_ring.h b/hw/wcn6450/v1/wbm_release_ring.h
new file mode 100644
index 0000000..37e37b0
--- /dev/null
+++ b/hw/wcn6450/v1/wbm_release_ring.h
@@ -0,0 +1,217 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _WBM_RELEASE_RING_H_
+#define _WBM_RELEASE_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+#include "tx_rate_stats_info.h"
+
+#define NUM_OF_DWORDS_WBM_RELEASE_RING 8
+
+struct wbm_release_ring {
+ struct buffer_addr_info released_buff_or_desc_addr_info;
+ uint32_t release_source_module : 3,
+ bm_action : 3,
+ buffer_or_desc_type : 3,
+ first_msdu_index : 4,
+ tqm_release_reason : 4,
+ rxdma_push_reason : 2,
+ rxdma_error_code : 5,
+ reo_push_reason : 2,
+ reo_error_code : 5,
+ wbm_internal_error : 1;
+ uint32_t tqm_status_number : 24,
+ transmit_count : 7,
+ msdu_continuation : 1;
+ uint32_t ack_frame_rssi : 8,
+ sw_release_details_valid : 1,
+ first_msdu : 1,
+ last_msdu : 1,
+ msdu_part_of_amsdu : 1,
+ fw_tx_notify_frame : 1,
+ buffer_timestamp : 19;
+ struct tx_rate_stats_info tx_rate_stats;
+ uint32_t sw_peer_id : 16,
+ tid : 4,
+ ring_id : 8,
+ looping_count : 4;
+};
+
+#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB 0
+#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK 0x00000007
+
+#define WBM_RELEASE_RING_2_BM_ACTION_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_BM_ACTION_LSB 3
+#define WBM_RELEASE_RING_2_BM_ACTION_MASK 0x00000038
+
+#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB 6
+#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK 0x000001c0
+
+#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_LSB 9
+#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_MASK 0x00001e00
+
+#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB 13
+#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK 0x0001e000
+
+#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB 17
+#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK 0x00060000
+
+#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB 19
+#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK 0x00f80000
+
+#define WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB 24
+#define WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK 0x03000000
+
+#define WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB 26
+#define WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK 0x7c000000
+
+#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_LSB 31
+#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_MASK 0x80000000
+
+#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_LSB 0
+#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_MASK 0x00ffffff
+
+#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_LSB 24
+#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_MASK 0x7f000000
+
+#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB 31
+#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK 0x80000000
+
+#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_OFFSET 0x00000010
+#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_LSB 0
+#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_MASK 0x000000ff
+
+#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_OFFSET 0x00000010
+#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_LSB 8
+#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_MASK 0x00000100
+
+#define WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET 0x00000010
+#define WBM_RELEASE_RING_4_FIRST_MSDU_LSB 9
+#define WBM_RELEASE_RING_4_FIRST_MSDU_MASK 0x00000200
+
+#define WBM_RELEASE_RING_4_LAST_MSDU_OFFSET 0x00000010
+#define WBM_RELEASE_RING_4_LAST_MSDU_LSB 10
+#define WBM_RELEASE_RING_4_LAST_MSDU_MASK 0x00000400
+
+#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_OFFSET 0x00000010
+#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_LSB 11
+#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_MASK 0x00000800
+
+#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010
+#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_LSB 12
+#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_MASK 0x00001000
+
+#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_OFFSET 0x00000010
+#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_LSB 13
+#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_MASK 0xffffe000
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_LSB 1
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_MASK 0x00000006
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 3
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x00000078
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_LSB 7
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000080
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_LSB 8
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000100
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_LSB 9
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000600
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_LSB 11
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x00007800
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 15
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00008000
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_LSB 16
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_MASK 0x0fff0000
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_LSB 28
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_MASK 0xf0000000
+
+#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018
+#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0
+#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff
+
+#define WBM_RELEASE_RING_7_SW_PEER_ID_OFFSET 0x0000001c
+#define WBM_RELEASE_RING_7_SW_PEER_ID_LSB 0
+#define WBM_RELEASE_RING_7_SW_PEER_ID_MASK 0x0000ffff
+
+#define WBM_RELEASE_RING_7_TID_OFFSET 0x0000001c
+#define WBM_RELEASE_RING_7_TID_LSB 16
+#define WBM_RELEASE_RING_7_TID_MASK 0x000f0000
+
+#define WBM_RELEASE_RING_7_RING_ID_OFFSET 0x0000001c
+#define WBM_RELEASE_RING_7_RING_ID_LSB 20
+#define WBM_RELEASE_RING_7_RING_ID_MASK 0x0ff00000
+
+#define WBM_RELEASE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c
+#define WBM_RELEASE_RING_7_LOOPING_COUNT_LSB 28
+#define WBM_RELEASE_RING_7_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/hw/wcn6450/v1/wcss_seq_hwiobase.h b/hw/wcn6450/v1/wcss_seq_hwiobase.h
new file mode 100644
index 0000000..65de18e
--- /dev/null
+++ b/hw/wcn6450/v1/wcss_seq_hwiobase.h
@@ -0,0 +1,609 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef __WCSS_SEQ_BASE_H__
+#define __WCSS_SEQ_BASE_H__
+
+#ifdef SCALE_INCLUDES
+ #include "HALhwio.h"
+#else
+ #include "msmhwio.h"
+#endif
+
+#ifndef SOC_WCSS_BASE_ADDR
+ #if defined(WCSS_BASE)
+ #if ( WCSS_BASE != 0x0 )
+ #error WCSS_BASE incorrectly redefined!
+ #endif
+ #endif
+
+ #define SOC_WCSS_BASE_ADDR 0x0
+#else
+ #if ( SOC_WCSS_BASE_ADDR != 0x0 )
+ #error SOC_WCSS_BASE_ADDR incorrectly redefined!
+ #endif
+#endif
+
+#define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000
+#define SEQ_WCSS_PHYA_OFFSET 0x00300000
+#define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00300000
+#define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00338000
+#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00338400
+#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00338800
+#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00338c00
+#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00339000
+#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00339400
+#define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00339800
+#define SEQ_WCSS_PHYA_WFAX_PCSS_IUSS_REG_MAP_OFFSET 0x0033f400
+#define SEQ_WCSS_PHYA_WFAX_PCSS_IUSS_COMMON_REG_MAP_OFFSET 0x0033f600
+#define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET 0x00388000
+#define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET 0x00390000
+#define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET 0x003a0000
+#define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET 0x003b0000
+#define SEQ_WCSS_PHYA_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00400000
+#define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET 0x00480000
+#define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET 0x004b0000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_OFFSET 0x005c0000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET 0x005c0000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET 0x005cf000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET 0x005cf400
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x005cf800
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x005cfc00
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET 0x005c0000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x005c5000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET 0x005d1000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x005d1000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OTP_OFFSET 0x005d1038
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OFFSET 0x005d10cc
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x005c7000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x005c9b00
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x005c7000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x005cb000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SW_RST_OFFSET 0x005d41fc
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_RAH_OFFSET 0x005d4204
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4300
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x005d43c0
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_CAL_OFFSET 0x005d4424
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x005d4800
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x005d4880
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4c00
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x005d5c00
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6800
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6840
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6900
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d6940
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6980
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d69c0
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d7000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d7040
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d7100
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d7140
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d7180
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d71c0
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x005d7c00
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET 0x005d7400
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x005d7400
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x005d7438
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OFFSET 0x005d74cc
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_OFFSET 0x005d8000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_MC_OFFSET 0x005d8000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_RX_OFFSET 0x005d8400
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET 0x005d8800
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x005d8880
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x005d88c0
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET 0x005d8940
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET 0x005d8980
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x005dc000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x005dc000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DRM_REG_OFFSET 0x005dc400
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXBB_OFFSET 0x005dc800
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_OFFSET 0x005dcc00
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_OFFSET 0x005dd000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_OFFSET 0x005dd400
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x005dd800
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x005dd980
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x005dd9c0
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x005ddac0
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x005dfc00
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x005dfc40
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x005dfc80
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x005dfcc0
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x005dfd40
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x005e0000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x005e0000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x005e021c
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x005e1000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x005e1300
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x005e21b8
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x005e4000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x005e8000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x005e821c
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x005e8400
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x005e8800
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x005e9000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x005e9300
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x005ea000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x005ec000
+#define SEQ_WCSS_UMAC_OFFSET 0x00a00000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000
+#define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000
+#define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000
+#define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000
+#define SEQ_WCSS_WMAC0_OFFSET 0x00a80000
+#define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000
+#define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000
+#define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000
+#define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000
+#define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000
+#define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000
+#define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000
+#define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000
+#define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000
+#define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000
+#define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000
+#define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000
+#define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000
+#define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000
+#define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000
+#define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000
+#define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000
+#define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000
+#define SEQ_WCSS_TOP_CMN_OFFSET 0x00b50000
+#define SEQ_WCSS_WCMN_CORE_OFFSET 0x00b58000
+#define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000
+#define SEQ_WCSS_PMM_TOP_OFFSET 0x00b70000
+#define SEQ_WCSS_MSIP_OFFSET 0x00b80000
+#define SEQ_WCSS_MSIP_RBIST_TX_CH0_OFFSET 0x00b80000
+#define SEQ_WCSS_MSIP_WL_DAC_CH0_OFFSET 0x00b80180
+#define SEQ_WCSS_MSIP_WL_DAC_CALIB_CH0_OFFSET 0x00b80190
+#define SEQ_WCSS_MSIP_WL_DAC_REGARRAY_CH0_OFFSET 0x00b80200
+#define SEQ_WCSS_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x00b802c0
+#define SEQ_WCSS_MSIP_WL_ADC_CH0_OFFSET 0x00b80400
+#define SEQ_WCSS_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x00b80434
+#define SEQ_WCSS_MSIP_MSIP_SHD_OTP_OFFSET 0x00b8d000
+#define SEQ_WCSS_MSIP_MSIP_TMUX_OFFSET 0x00b8d040
+#define SEQ_WCSS_MSIP_MSIP_OTP_OFFSET 0x00b8d080
+#define SEQ_WCSS_MSIP_MSIP_LDO_CTRL_OFFSET 0x00b8d0b4
+#define SEQ_WCSS_MSIP_MSIP_CLKGEN_OFFSET 0x00b8d100
+#define SEQ_WCSS_MSIP_MSIP_BIAS_OFFSET 0x00b8e000
+#define SEQ_WCSS_MSIP_BBPLL_OFFSET 0x00b8f000
+#define SEQ_WCSS_MSIP_WL_CLKGEN_OFFSET 0x00b8f800
+#define SEQ_WCSS_MSIP_MSIP_DRM_REG_OFFSET 0x00b8fc00
+#define SEQ_WCSS_DBG_OFFSET 0x00b90000
+#define SEQ_WCSS_DBG_WCSS_DBG_ROM_TABLE_OFFSET 0x00b90000
+#define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000
+#define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000
+#define SEQ_WCSS_DBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00b94000
+#define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000
+#define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000
+#define SEQ_WCSS_DBG_EVENT_MACEVENT_OFFSET 0x00bb0000
+#define SEQ_WCSS_DBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb1000
+#define SEQ_WCSS_DBG_TLV_MACTLV_OFFSET 0x00bb2000
+#define SEQ_WCSS_DBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb3000
+#define SEQ_WCSS_DBG_TBUS_MACTBUS_OFFSET 0x00bb4000
+#define SEQ_WCSS_DBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb5000
+#define SEQ_WCSS_DBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00bb6000
+#define SEQ_WCSS_DBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00bb8000
+#define SEQ_WCSS_DBG_TPDM_OFFSET 0x00bb9000
+#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00bb9280
+#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00bb9000
+#define SEQ_WCSS_DBG_TPDA_OFFSET 0x00bba000
+#define SEQ_WCSS_DBG_CXATBFUNNEL_128W8SP_OFFSET 0x00bbb000
+#define SEQ_WCSS_DBG_TMC_CXTMC_F128W32K_OFFSET 0x00bbc000
+#define SEQ_WCSS_DBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbe000
+#define SEQ_WCSS_DBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbf000
+#define SEQ_WCSS_DBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00bc0000
+#define SEQ_WCSS_DBG_TRCCNTRS_OFFSET 0x00bc1000
+#define SEQ_WCSS_DBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00bc4000
+#define SEQ_WCSS_DBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00bc5000
+#define SEQ_WCSS_DBG_BTSS_PMM_FUN_CXATBFUNNEL_32W2SP_OFFSET 0x00bc9000
+#define SEQ_WCSS_DBG_UNOC_UMAC_NOC_OFFSET 0x00bd0000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_OFFSET 0x00be0000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00be0000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00be4000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00be5000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00be6000
+#define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00c31000
+#define SEQ_WCSS_RET_AHB_OFFSET 0x00c90000
+#define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00ca0000
+#define SEQ_WCSS_CC_OFFSET 0x00cb0000
+#define SEQ_WCSS_UMAC_ACMT_OFFSET 0x00cc0000
+
+#define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000
+#define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00038000
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00038400
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00038800
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00038c00
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00039000
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00039400
+#define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00039800
+#define SEQ_WFAX_TOP_WFAX_PCSS_IUSS_REG_MAP_OFFSET 0x0003f400
+#define SEQ_WFAX_TOP_WFAX_PCSS_IUSS_COMMON_REG_MAP_OFFSET 0x0003f600
+#define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00088000
+#define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00090000
+#define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x000a0000
+#define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x000b0000
+#define SEQ_WFAX_TOP_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00100000
+#define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x00180000
+#define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x001b0000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET 0x002c0000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET 0x002c0000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET 0x002cf000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET 0x002cf400
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x002cf800
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x002cfc00
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET 0x002c0000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x002c5000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET 0x002d1000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x002d1000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OTP_OFFSET 0x002d1038
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OFFSET 0x002d10cc
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x002c7000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x002c9b00
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x002c7000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x002cb000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x002d4000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x002d4000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SW_RST_OFFSET 0x002d41fc
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_RAH_OFFSET 0x002d4204
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x002d4300
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x002d43c0
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_CAL_OFFSET 0x002d4424
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x002d4800
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x002d4880
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x002d4c00
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x002d5c00
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x002d6800
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x002d6840
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x002d6900
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x002d6940
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x002d6980
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x002d69c0
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x002d7000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x002d7040
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x002d7100
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x002d7140
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x002d7180
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x002d71c0
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x002d7c00
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET 0x002d7400
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x002d7400
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x002d7438
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OFFSET 0x002d74cc
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_OFFSET 0x002d8000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_MC_OFFSET 0x002d8000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_RX_OFFSET 0x002d8400
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET 0x002d8800
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x002d8880
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x002d88c0
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET 0x002d8940
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET 0x002d8980
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x002dc000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x002dc000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DRM_REG_OFFSET 0x002dc400
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXBB_OFFSET 0x002dc800
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_OFFSET 0x002dcc00
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_OFFSET 0x002dd000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_OFFSET 0x002dd400
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x002dd800
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x002dd980
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x002dd9c0
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x002ddac0
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x002dfc00
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x002dfc40
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x002dfc80
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x002dfcc0
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x002dfd40
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x002e0000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x002e0000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x002e021c
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x002e1000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x002e1300
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x002e21b8
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x002e4000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x002e8000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x002e821c
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x002e8400
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x002e8800
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x002e9000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x002e9300
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x002ea000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x002ec000
+
+#define SEQ_RFA_FROM_WSI_RFA_SOC_OFFSET 0x00000000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_SYSCTRL_OFFSET 0x0000f000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_TLMM_OFFSET 0x0000f400
+#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x0000f800
+#define SEQ_RFA_FROM_WSI_RFA_SOC_AON_1P8_REG_OFFSET 0x0000fc00
+#define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_TLMM_OFFSET 0x00000000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x00005000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_OFFSET 0x00011000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x00011000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_PMU_OTP_OFFSET 0x00011038
+#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_PMU_OFFSET 0x000110cc
+#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x00007000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x00009b00
+#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x00007000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x0000b000
+#define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000
+#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000
+#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SW_RST_OFFSET 0x000141fc
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_RAH_OFFSET 0x00014204
+#define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300
+#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET 0x000143c0
+#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_CAL_OFFSET 0x00014424
+#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00014800
+#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET 0x00014880
+#define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014c00
+#define SEQ_RFA_FROM_WSI_RFA_CMN_BTFMPLL_OFFSET 0x00015c00
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016800
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016840
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016900
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016940
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016980
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000169c0
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00017000
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00017040
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00017100
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00017140
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00017180
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x000171c0
+#define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00017c00
+#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_OFFSET 0x00017400
+#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x00017400
+#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x00017438
+#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_PMU_OFFSET 0x000174cc
+#define SEQ_RFA_FROM_WSI_RFA_FM_OFFSET 0x00018000
+#define SEQ_RFA_FROM_WSI_RFA_FM_FM_MC_OFFSET 0x00018000
+#define SEQ_RFA_FROM_WSI_RFA_FM_FM_RX_OFFSET 0x00018400
+#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_BS_OFFSET 0x00018800
+#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x00018880
+#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_BIST_OFFSET 0x000188c0
+#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_PC_OFFSET 0x00018940
+#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_AC_OFFSET 0x00018980
+#define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET 0x0001c000
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TOP_OFFSET 0x0001c000
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DRM_REG_OFFSET 0x0001c400
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TXBB_OFFSET 0x0001c800
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TXFE_OFFSET 0x0001cc00
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXBB_OFFSET 0x0001d000
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXFE_OFFSET 0x0001d400
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x0001d800
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_OFFSET 0x0001d980
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x0001d9c0
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_MISC_OFFSET 0x0001dac0
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET 0x0001fc00
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET 0x0001fc40
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET 0x0001fc80
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET 0x0001fcc0
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x0001fd40
+#define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET 0x00020000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00020000
+#define SEQ_RFA_FROM_WSI_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x0002021c
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00021000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00021300
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x000221b8
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x00024000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00028000
+#define SEQ_RFA_FROM_WSI_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x0002821c
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH0_OFFSET 0x00028400
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH0_OFFSET 0x00028800
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00029000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00029300
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0002a000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x0002c000
+
+#define SEQ_RFA_SOC_AO_SYSCTRL_OFFSET 0x0000f000
+#define SEQ_RFA_SOC_AO_TLMM_OFFSET 0x0000f400
+#define SEQ_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x0000f800
+#define SEQ_RFA_SOC_AON_1P8_REG_OFFSET 0x0000fc00
+#define SEQ_RFA_SOC_HZ_TLMM_OFFSET 0x00000000
+#define SEQ_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x00005000
+#define SEQ_RFA_SOC_PMU_OFFSET 0x00011000
+#define SEQ_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x00011000
+#define SEQ_RFA_SOC_PMU_PMU_OTP_OFFSET 0x00011038
+#define SEQ_RFA_SOC_PMU_PMU_OFFSET 0x000110cc
+#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x00007000
+#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x00009b00
+#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x00007000
+#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x0000b000
+
+#define SEQ_PMU_TOP_PMU_SHD_OTP_OFFSET 0x00000000
+#define SEQ_PMU_TOP_PMU_OTP_OFFSET 0x00000038
+#define SEQ_PMU_TOP_PMU_OFFSET 0x000000cc
+
+#define SEQ_SECURITY_CONTROL_BT_CMN_SECURITY_CONTROL_CORE_OFFSET 0x00002b00
+#define SEQ_SECURITY_CONTROL_BT_CMN_QFPROM_RAW_FUSE_OFFSET 0x00000000
+#define SEQ_SECURITY_CONTROL_BT_CMN_QFPROM_CORR_FUSE_OFFSET 0x00004000
+
+#define SEQ_RFA_CMN_AON_OFFSET 0x00000000
+#define SEQ_RFA_CMN_RFA_SW_RST_OFFSET 0x000001fc
+#define SEQ_RFA_CMN_WL_RAH_OFFSET 0x00000204
+#define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300
+#define SEQ_RFA_CMN_AON_COEX_OFFSET 0x000003c0
+#define SEQ_RFA_CMN_AON_COEX_CAL_OFFSET 0x00000424
+#define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00000800
+#define SEQ_RFA_CMN_RFA_OTP_OFFSET 0x00000880
+#define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000c00
+#define SEQ_RFA_CMN_BTFMPLL_OFFSET 0x00001c00
+#define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002800
+#define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002840
+#define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002900
+#define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002940
+#define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002980
+#define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000029c0
+#define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00003000
+#define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00003040
+#define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00003100
+#define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00003140
+#define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00003180
+#define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x000031c0
+#define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00003c00
+#define SEQ_RFA_CMN_PMU_TEST_OFFSET 0x00003400
+#define SEQ_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x00003400
+#define SEQ_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x00003438
+#define SEQ_RFA_CMN_PMU_TEST_PMU_OFFSET 0x000034cc
+
+#define SEQ_RFA_FM_FM_MC_OFFSET 0x00000000
+#define SEQ_RFA_FM_FM_RX_OFFSET 0x00000400
+#define SEQ_RFA_FM_FM_SYNTH_BS_OFFSET 0x00000800
+#define SEQ_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x00000880
+#define SEQ_RFA_FM_FM_SYNTH_BIST_OFFSET 0x000008c0
+#define SEQ_RFA_FM_FM_SYNTH_PC_OFFSET 0x00000940
+#define SEQ_RFA_FM_FM_SYNTH_AC_OFFSET 0x00000980
+
+#define SEQ_RFA_BT_BT_TOP_OFFSET 0x00000000
+#define SEQ_RFA_BT_BT_DRM_REG_OFFSET 0x00000400
+#define SEQ_RFA_BT_BT_TXBB_OFFSET 0x00000800
+#define SEQ_RFA_BT_BT_TXFE_OFFSET 0x00000c00
+#define SEQ_RFA_BT_BT_RXBB_OFFSET 0x00001000
+#define SEQ_RFA_BT_BT_RXFE_OFFSET 0x00001400
+#define SEQ_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x00001800
+#define SEQ_RFA_BT_BT_DAC_OFFSET 0x00001980
+#define SEQ_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x000019c0
+#define SEQ_RFA_BT_BT_DAC_MISC_OFFSET 0x00001ac0
+#define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET 0x00003c00
+#define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET 0x00003c40
+#define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET 0x00003c80
+#define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET 0x00003cc0
+#define SEQ_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x00003d40
+
+#define SEQ_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00000000
+#define SEQ_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x0000021c
+#define SEQ_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00001000
+#define SEQ_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00001300
+#define SEQ_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x000021b8
+#define SEQ_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x00004000
+#define SEQ_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00008000
+#define SEQ_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x0000821c
+#define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00008400
+#define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00008800
+#define SEQ_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00009000
+#define SEQ_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00009300
+#define SEQ_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0000a000
+#define SEQ_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x0000c000
+
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000
+#define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000
+#define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000
+#define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000
+
+#define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000
+#define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000
+#define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000
+#define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000
+#define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000
+#define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000
+
+#define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000
+#define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000
+#define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000
+#define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000
+#define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000
+#define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000
+#define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000
+#define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000
+#define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000
+#define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000
+#define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000
+#define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000
+#define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000
+#define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000
+#define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000
+#define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000
+#define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000
+
+#define SEQ_MSIP_RBIST_TX_CH0_OFFSET 0x00000000
+#define SEQ_MSIP_WL_DAC_CH0_OFFSET 0x00000180
+#define SEQ_MSIP_WL_DAC_CALIB_CH0_OFFSET 0x00000190
+#define SEQ_MSIP_WL_DAC_REGARRAY_CH0_OFFSET 0x00000200
+#define SEQ_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x000002c0
+#define SEQ_MSIP_WL_ADC_CH0_OFFSET 0x00000400
+#define SEQ_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x00000434
+#define SEQ_MSIP_MSIP_SHD_OTP_OFFSET 0x0000d000
+#define SEQ_MSIP_MSIP_TMUX_OFFSET 0x0000d040
+#define SEQ_MSIP_MSIP_OTP_OFFSET 0x0000d080
+#define SEQ_MSIP_MSIP_LDO_CTRL_OFFSET 0x0000d0b4
+#define SEQ_MSIP_MSIP_CLKGEN_OFFSET 0x0000d100
+#define SEQ_MSIP_MSIP_BIAS_OFFSET 0x0000e000
+#define SEQ_MSIP_BBPLL_OFFSET 0x0000f000
+#define SEQ_MSIP_WL_CLKGEN_OFFSET 0x0000f800
+#define SEQ_MSIP_MSIP_DRM_REG_OFFSET 0x0000fc00
+
+#define SEQ_WCSSDBG_WCSS_DBG_ROM_TABLE_OFFSET 0x00000000
+#define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000
+#define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000
+#define SEQ_WCSSDBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00004000
+#define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000
+#define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000
+#define SEQ_WCSSDBG_EVENT_MACEVENT_OFFSET 0x00020000
+#define SEQ_WCSSDBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00021000
+#define SEQ_WCSSDBG_TLV_MACTLV_OFFSET 0x00022000
+#define SEQ_WCSSDBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00023000
+#define SEQ_WCSSDBG_TBUS_MACTBUS_OFFSET 0x00024000
+#define SEQ_WCSSDBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00025000
+#define SEQ_WCSSDBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00026000
+#define SEQ_WCSSDBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00028000
+#define SEQ_WCSSDBG_TPDM_OFFSET 0x00029000
+#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00029280
+#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00029000
+#define SEQ_WCSSDBG_TPDA_OFFSET 0x0002a000
+#define SEQ_WCSSDBG_CXATBFUNNEL_128W8SP_OFFSET 0x0002b000
+#define SEQ_WCSSDBG_TMC_CXTMC_F128W32K_OFFSET 0x0002c000
+#define SEQ_WCSSDBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002e000
+#define SEQ_WCSSDBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002f000
+#define SEQ_WCSSDBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00030000
+#define SEQ_WCSSDBG_TRCCNTRS_OFFSET 0x00031000
+#define SEQ_WCSSDBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00034000
+#define SEQ_WCSSDBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00035000
+#define SEQ_WCSSDBG_BTSS_PMM_FUN_CXATBFUNNEL_32W2SP_OFFSET 0x00039000
+#define SEQ_WCSSDBG_UNOC_UMAC_NOC_OFFSET 0x00040000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_OFFSET 0x00050000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00050000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00054000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00055000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00056000
+#define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET 0x000a1000
+
+#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280
+#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000
+
+#define SEQ_PHYA_DBG_PHYA_NOC_OFFSET 0x00000000
+#define SEQ_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00004000
+#define SEQ_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00005000
+#define SEQ_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00006000
+
+#endif
+
diff --git a/hw/wcn6450/v1/wcss_version.h b/hw/wcn6450/v1/wcss_version.h
new file mode 100644
index 0000000..1fe87c6
--- /dev/null
+++ b/hw/wcn6450/v1/wcss_version.h
@@ -0,0 +1,20 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#define WCSS_VERSION 33
