src/llvm-project/llvm/test/CodeGen/Thumb2/bti-const-island.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv7m-arm-none-eabi -run-pass=arm-cp-islands %s -o - | FileCheck %s

# This test checks that the ARM Constant Island pass correctly handles BTI
# instructions when adding new BBs to jump tables.
#
# Specifically the pass will replace bb.1.bb42.i in the jump table with a new
# BB which will contain an unconditional branch to bb.1.bb42.i.
# We expect that a BTI instruction will be added to the new BB and removed from
# bb.1.bb42.i.

--- |
  declare noalias ptr @calloc(i32, i32)

  define internal i32 @test(i32 %argc, ptr nocapture %argv) {
  entry:
    br label %bb42.i

  bb5.i:
    %0 = or i32 %argc, 32
    br label %bb42.i

  bb35.i:
    %1 = call noalias ptr @calloc(i32 20, i32 1)
    unreachable

  bb37.i:
    %2 = call noalias ptr @calloc(i32 14, i32 1)
    unreachable

  bb39.i:
    %3 = call noalias ptr @calloc(i32 17, i32 1)
    unreachable

  bb42.i:
    switch i32 %argc, label %bb39.i [
      i32 70, label %bb35.i
      i32 77, label %bb37.i
      i32 100, label %bb5.i
      i32 101, label %bb42.i
      i32 116, label %bb42.i
    ]
  }

  !llvm.module.flags = !{!0}
  !0 = !{i32 8, !"branch-target-enforcement", i32 1}

...
---
name:            test
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$r0' }
frameInfo:
  stackSize:       8
  maxAlignment:    4
  adjustsStack:    true
  hasCalls:        true
  maxCallFrameSize: 0
stack:
  - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$lr' }
  - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$r7' }
machineFunctionInfo: {}
jumpTable:
  kind:            inline
  entries:
    - id:              0
      blocks:          [ '%bb.3', '%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.5',
                         '%bb.5', '%bb.4', '%bb.5', '%bb.5', '%bb.5', '%bb.5',
                         '%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.5',
                         '%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.5',
                         '%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.5',
                         '%bb.1', '%bb.1', '%bb.5', '%bb.5', '%bb.5', '%bb.5',
                         '%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.5',
                         '%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.1' ]
body:             |
  ; CHECK-LABEL: name: test
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $r0, $r7, $lr
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 70, 14 /* CC::al */, $noreg
  ; CHECK: bb.1.bb42.i (align 4):
  ; CHECK:   successors: %bb.6(0x40000000), %bb.2(0x40000000)
  ; CHECK:   liveins: $r0
  ; CHECK:   tCMPi8 renamable $r0, 46, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   tBcc %bb.6, 8 /* CC::hi */, killed $cpsr
  ; CHECK: bb.2.bb42.i:
  ; CHECK:   successors: %bb.5(0x20000000), %bb.6(0x20000000), %bb.7(0x20000000), %bb.4(0x20000000)
  ; CHECK:   liveins: $r0
  ; CHECK:   t2TBB_JT $pc, $r0, %jump-table.0, 0
  ; CHECK: bb.3:
  ; CHECK:   successors:
  ; CHECK:   JUMPTABLE_TBB 0, %jump-table.0, 188
  ; CHECK: bb.4.bb42.i:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $r0
  ; CHECK:   t2BTI
  ; CHECK:   tB %bb.1, 14 /* CC::al */, $noreg
  ; CHECK: bb.5.bb35.i:
  ; CHECK:   successors:
  ; CHECK:   t2BTI
  ; CHECK:   $r0, dead $cpsr = tMOVi8 20, 14 /* CC::al */, $noreg
  ; CHECK:   $r1, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
  ; CHECK:   tBL 14 /* CC::al */, $noreg, @calloc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def dead $r0
  ; CHECK: bb.6.bb39.i:
  ; CHECK:   successors:
  ; CHECK:   t2BTI
  ; CHECK:   $r0, dead $cpsr = tMOVi8 17, 14 /* CC::al */, $noreg
  ; CHECK:   $r1, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
  ; CHECK:   tBL 14 /* CC::al */, $noreg, @calloc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def dead $r0
  ; CHECK: bb.7.bb37.i:
  ; CHECK:   t2BTI
  ; CHECK:   $r0, dead $cpsr = tMOVi8 14, 14 /* CC::al */, $noreg
  ; CHECK:   $r1, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
  ; CHECK:   tBL 14 /* CC::al */, $noreg, @calloc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def dead $r0
  bb.0.entry:
    liveins: $r0, $r7, $lr

    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 70, 14 /* CC::al */, $noreg

  bb.1.bb42.i (align 4):
    successors: %bb.5, %bb.2
    liveins: $r0

    t2BTI
    tCMPi8 renamable $r0, 46, 14 /* CC::al */, $noreg, implicit-def $cpsr
    t2Bcc %bb.5, 8 /* CC::hi */, killed $cpsr

  bb.2.bb42.i:
    successors: %bb.3, %bb.5, %bb.4, %bb.1
    liveins: $r0

    renamable $r1 = t2LEApcrelJT %jump-table.0, 14 /* CC::al */, $noreg
    renamable $r1 = t2ADDrs killed renamable $r1, renamable $r0, 18, 14 /* CC::al */, $noreg, $noreg
    t2BR_JT killed renamable $r1, renamable $r0, %jump-table.0

  bb.3.bb35.i:
    successors:

    t2BTI
    $r0, dead $cpsr = tMOVi8 20, 14 /* CC::al */, $noreg
    $r1, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
    tBL 14 /* CC::al */, $noreg, @calloc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def dead $r0

  bb.5.bb39.i:
    successors:

    t2BTI
    $r0, dead $cpsr = tMOVi8 17, 14 /* CC::al */, $noreg
    $r1, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
    tBL 14 /* CC::al */, $noreg, @calloc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def dead $r0

  bb.4.bb37.i:
    t2BTI
    $r0, dead $cpsr = tMOVi8 14, 14 /* CC::al */, $noreg
    $r1, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
    tBL 14 /* CC::al */, $noreg, @calloc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def dead $r0

...