src/llvm-emscripten/test/CodeGen/X86/GlobalISel/select-and-scalar.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL

--- |
  define i8 @test_and_i8(i8 %arg1, i8 %arg2) {
    %ret = and i8 %arg1, %arg2
    ret i8 %ret
  }

  define i16 @test_and_i16(i16 %arg1, i16 %arg2) {
    %ret = and i16 %arg1, %arg2
    ret i16 %ret
  }

  define i32 @test_and_i32(i32 %arg1, i32 %arg2) {
    %ret = and i32 %arg1, %arg2
    ret i32 %ret
  }

  define i64 @test_and_i64(i64 %arg1, i64 %arg2) {
    %ret = and i64 %arg1, %arg2
    ret i64 %ret
  }

...
---
name:            test_and_i8
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr, preferred-register: '' }
  - { id: 1, class: gpr, preferred-register: '' }
  - { id: 2, class: gpr, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body:             |
  bb.1 (%ir-block.0):
    liveins: %edi, %esi

    ; ALL-LABEL: name: test_and_i8
    ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY %dil
    ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY %sil
    ; ALL: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[COPY]], [[COPY1]], implicit-def %eflags
    ; ALL: %al = COPY [[AND8rr]]
    ; ALL: RET 0, implicit %al
    %0(s8) = COPY %dil
    %1(s8) = COPY %sil
    %2(s8) = G_AND %0, %1
    %al = COPY %2(s8)
    RET 0, implicit %al

...
---
name:            test_and_i16
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr, preferred-register: '' }
  - { id: 1, class: gpr, preferred-register: '' }
  - { id: 2, class: gpr, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body:             |
  bb.1 (%ir-block.0):
    liveins: %edi, %esi

    ; ALL-LABEL: name: test_and_i16
    ; ALL: [[COPY:%[0-9]+]]:gr16 = COPY %di
    ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY %si
    ; ALL: [[AND16rr:%[0-9]+]]:gr16 = AND16rr [[COPY]], [[COPY1]], implicit-def %eflags
    ; ALL: %ax = COPY [[AND16rr]]
    ; ALL: RET 0, implicit %ax
    %0(s16) = COPY %di
    %1(s16) = COPY %si
    %2(s16) = G_AND %0, %1
    %ax = COPY %2(s16)
    RET 0, implicit %ax

...
---
name:            test_and_i32
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr, preferred-register: '' }
  - { id: 1, class: gpr, preferred-register: '' }
  - { id: 2, class: gpr, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body:             |
  bb.1 (%ir-block.0):
    liveins: %edi, %esi

    ; ALL-LABEL: name: test_and_i32
    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY %edi
    ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
    ; ALL: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[COPY]], [[COPY1]], implicit-def %eflags
    ; ALL: %eax = COPY [[AND32rr]]
    ; ALL: RET 0, implicit %eax
    %0(s32) = COPY %edi
    %1(s32) = COPY %esi
    %2(s32) = G_AND %0, %1
    %eax = COPY %2(s32)
    RET 0, implicit %eax

...
---
name:            test_and_i64
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr, preferred-register: '' }
  - { id: 1, class: gpr, preferred-register: '' }
  - { id: 2, class: gpr, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body:             |
  bb.1 (%ir-block.0):
    liveins: %rdi, %rsi

    ; ALL-LABEL: name: test_and_i64
    ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
    ; ALL: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi
    ; ALL: [[AND64rr:%[0-9]+]]:gr64 = AND64rr [[COPY]], [[COPY1]], implicit-def %eflags
    ; ALL: %rax = COPY [[AND64rr]]
    ; ALL: RET 0, implicit %rax
    %0(s64) = COPY %rdi
    %1(s64) = COPY %rsi
    %2(s64) = G_AND %0, %1
    %rax = COPY %2(s64)
    RET 0, implicit %rax

...