| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py |
| // RUN: %clang_cc1 -triple riscv64 -target-feature +zksed -emit-llvm %s -o - \ |
| // RUN: | FileCheck %s -check-prefix=RV64ZKSED |
| |
| // RV64ZKSED-LABEL: @sm4ks( |
| // RV64ZKSED-NEXT: entry: |
| // RV64ZKSED-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8 |
| // RV64ZKSED-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8 |
| // RV64ZKSED-NEXT: store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8 |
| // RV64ZKSED-NEXT: store i64 [[RS2:%.*]], ptr [[RS2_ADDR]], align 8 |
| // RV64ZKSED-NEXT: [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8 |
| // RV64ZKSED-NEXT: [[TMP1:%.*]] = load i64, ptr [[RS2_ADDR]], align 8 |
| // RV64ZKSED-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.sm4ks.i64(i64 [[TMP0]], i64 [[TMP1]], i8 0) |
| // RV64ZKSED-NEXT: ret i64 [[TMP2]] |
| // |
| long sm4ks(long rs1, long rs2) { |
| return __builtin_riscv_sm4ks(rs1, rs2, 0); |
| } |
| |
| // RV64ZKSED-LABEL: @sm4ed( |
| // RV64ZKSED-NEXT: entry: |
| // RV64ZKSED-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8 |
| // RV64ZKSED-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8 |
| // RV64ZKSED-NEXT: store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8 |
| // RV64ZKSED-NEXT: store i64 [[RS2:%.*]], ptr [[RS2_ADDR]], align 8 |
| // RV64ZKSED-NEXT: [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8 |
| // RV64ZKSED-NEXT: [[TMP1:%.*]] = load i64, ptr [[RS2_ADDR]], align 8 |
| // RV64ZKSED-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.sm4ed.i64(i64 [[TMP0]], i64 [[TMP1]], i8 0) |
| // RV64ZKSED-NEXT: ret i64 [[TMP2]] |
| // |
| long sm4ed(long rs1, long rs2) { |
| return __builtin_riscv_sm4ed(rs1, rs2, 0); |
| } |
