Add Goldfish interrupt controller
The following was taken from AOSP emulator documentation :
<AOSP>/external/qemu/GOLDFISH-VIRTUAL-HARDWARE.TXT
$QEMU=qemu-android : new code base QEMU with ranchu machine
$KERNEL=https://android.googlesource.com/kernel/goldfish.git
Relevant files:
$QEMU/hw/intc/goldfish_pic.c
$KERNEL/arch/mips/goldfish/goldfish-interrupt.c
Device properties:
Name: goldfish_pic
Id: -1
IrqCount: 0 (uses parent CPU IRQ instead).
32-bit I/O registers :
0x00 R STATUS : Read the number of pending interrupts.
0x04 R NUMBER : Read the lowest pending interrupt index.
0x08 W DISABLE_ALL : Clear all pending interrupts
0x0c W DISABLE : Disable a given interrupt.
0x10 W ENABLE : Enable a given interrupt.
Goldfish provides its own interrupt controller that can
manage up to 32 distinct maskable interrupt request lines.
The controller itself is cascaded from a parent CPU IRQ.
What this means in practice:
- Each IRQ has a 'level' that is either 'high' (1) or 'low' (0).
- Each IRQ also has a binary 'enable' flag.
- Whenever (level == 1 && enabled == 1) is reached due
to a state change, the controller raises its parent
IRQ. This typically interrupts the CPU and forces the
kernel to deal with the interrupt request.
- Raised/Enabled interrupts that have not been serviced yet
are called "pending". Raised/Disabled interrupts are called
"masked" and are essentially silent until enabled.
Change-Id: Ib5eb3c82cf89f86c9ff81ec303e3ab6acca155aa
3 files changed